ACPI: Drop typedef global_nvs_t
Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.
Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/include/acpi/acpi_gnvs.h b/src/include/acpi/acpi_gnvs.h
index cc0c471..6173fa1 100644
--- a/src/include/acpi/acpi_gnvs.h
+++ b/src/include/acpi/acpi_gnvs.h
@@ -16,4 +16,21 @@
uint32_t *gnvs_cbmc_ptr(void);
void *gnvs_chromeos_ptr(void);
+/*
+ * Creates acpi gnvs and adds it to the DSDT table.
+ * GNVS creation is chipset specific and is done in soc specific acpi.c file.
+ */
+struct device;
+void southbridge_inject_dsdt(const struct device *device);
+
+/*
+ * This function populates the gnvs structure in acpi table.
+ * Defined as weak in common acpi as gnvs structure definition is
+ * chipset specific.
+ */
+struct global_nvs;
+
+void acpi_create_gnvs(struct global_nvs *gnvs);
+void acpi_init_gnvs(struct global_nvs *gnvs);
+
#endif
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index cdc6901..56352c5 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -86,6 +86,7 @@
typedef asmlinkage void (*smm_handler_t)(void *);
/* SMM Runtime helpers. */
+struct global_nvs *smm_get_gnvs(void);
/* Entry point for SMM modules. */
asmlinkage void smm_handler_start(void *params);
diff --git a/src/mainboard/apple/macbook21/acpi_tables.c b/src/mainboard/apple/macbook21/acpi_tables.c
index 39ccb01..52c2fbb 100644
--- a/src/mainboard/apple/macbook21/acpi_tables.c
+++ b/src/mainboard/apple/macbook21/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Enable both COM ports */
gnvs->cmap = 0x01;
diff --git a/src/mainboard/apple/macbookair4_2/gnvs.c b/src/mainboard/apple/macbookair4_2/gnvs.c
index 55f9eb2..846f079 100644
--- a/src/mainboard/apple/macbookair4_2/gnvs.c
+++ b/src/mainboard/apple/macbookair4_2/gnvs.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Disable USB ports in S3 by default */
gnvs->s3u0 = 0;
diff --git a/src/mainboard/asrock/b75pro3-m/acpi_tables.c b/src/mainboard/asrock/b75pro3-m/acpi_tables.c
index 33feed2..28c9d8e 100644
--- a/src/mainboard/asrock/b75pro3-m/acpi_tables.c
+++ b/src/mainboard/asrock/b75pro3-m/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->tcrt = 100;
gnvs->tpsv = 90;
diff --git a/src/mainboard/asrock/b85m_pro4/acpi_tables.c b/src/mainboard/asrock/b85m_pro4/acpi_tables.c
index f00b3e7..eed290d 100644
--- a/src/mainboard/asrock/b85m_pro4/acpi_tables.c
+++ b/src/mainboard/asrock/b85m_pro4/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/lynxpoint/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->tcrt = 100;
gnvs->tpsv = 90;
diff --git a/src/mainboard/asrock/g41c-gs/acpi_tables.c b/src/mainboard/asrock/g41c-gs/acpi_tables.c
index ec9420c..9eef159 100644
--- a/src/mainboard/asrock/g41c-gs/acpi_tables.c
+++ b/src/mainboard/asrock/g41c-gs/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->cmap = 0x01; /* Enable COM 1 port */
diff --git a/src/mainboard/asrock/h81m-hds/acpi_tables.c b/src/mainboard/asrock/h81m-hds/acpi_tables.c
index 3bc9340..8ec5b11 100644
--- a/src/mainboard/asrock/h81m-hds/acpi_tables.c
+++ b/src/mainboard/asrock/h81m-hds/acpi_tables.c
@@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/lynxpoint/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
}
diff --git a/src/mainboard/asus/h61m-cs/acpi_tables.c b/src/mainboard/asus/h61m-cs/acpi_tables.c
index 47cf3c2..852b0b4 100644
--- a/src/mainboard/asus/h61m-cs/acpi_tables.c
+++ b/src/mainboard/asus/h61m-cs/acpi_tables.c
@@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
}
diff --git a/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c b/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c
index 1dd16ab..14a79f8 100644
--- a/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c
+++ b/src/mainboard/asus/maximus_iv_gene-z/acpi_tables.c
@@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
}
diff --git a/src/mainboard/asus/p5gc-mx/acpi_tables.c b/src/mainboard/asus/p5gc-mx/acpi_tables.c
index 5583462..496d419 100644
--- a/src/mainboard/asus/p5gc-mx/acpi_tables.c
+++ b/src/mainboard/asus/p5gc-mx/acpi_tables.c
@@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
}
diff --git a/src/mainboard/asus/p5qc/acpi_tables.c b/src/mainboard/asus/p5qc/acpi_tables.c
index 8b1303e..65db55f 100644
--- a/src/mainboard/asus/p5qc/acpi_tables.c
+++ b/src/mainboard/asus/p5qc/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801jx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
diff --git a/src/mainboard/asus/p5ql-em/acpi_tables.c b/src/mainboard/asus/p5ql-em/acpi_tables.c
index b65ca71..4f59ed0 100644
--- a/src/mainboard/asus/p5ql-em/acpi_tables.c
+++ b/src/mainboard/asus/p5ql-em/acpi_tables.c
@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpigen.h>
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801jx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
diff --git a/src/mainboard/asus/p5qpl-am/acpi_tables.c b/src/mainboard/asus/p5qpl-am/acpi_tables.c
index ec9420c..9eef159 100644
--- a/src/mainboard/asus/p5qpl-am/acpi_tables.c
+++ b/src/mainboard/asus/p5qpl-am/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->cmap = 0x01; /* Enable COM 1 port */
diff --git a/src/mainboard/asus/p8h61-m_lx/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx/acpi_tables.c
index 1dd16ab..14a79f8 100644
--- a/src/mainboard/asus/p8h61-m_lx/acpi_tables.c
+++ b/src/mainboard/asus/p8h61-m_lx/acpi_tables.c
@@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
}
diff --git a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c
index 33feed2..28c9d8e 100644
--- a/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c
+++ b/src/mainboard/asus/p8h61-m_lx3_r2_0/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->tcrt = 100;
gnvs->tpsv = 90;
diff --git a/src/mainboard/asus/p8h61-m_pro/acpi_tables.c b/src/mainboard/asus/p8h61-m_pro/acpi_tables.c
index 33feed2..28c9d8e 100644
--- a/src/mainboard/asus/p8h61-m_pro/acpi_tables.c
+++ b/src/mainboard/asus/p8h61-m_pro/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->tcrt = 100;
gnvs->tpsv = 90;
diff --git a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c
index 6c1b4da0..e401b65 100644
--- a/src/mainboard/asus/p8z77-m_pro/acpi_tables.c
+++ b/src/mainboard/asus/p8z77-m_pro/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* critical temp that will shutdown the pc == 95C degrees */
gnvs->tcrt = 95;
diff --git a/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c
index 33feed2..28c9d8e 100644
--- a/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c
+++ b/src/mainboard/asus/p8z77-v_lx2/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->tcrt = 100;
gnvs->tpsv = 90;
diff --git a/src/mainboard/compulab/intense_pc/acpi_tables.c b/src/mainboard/compulab/intense_pc/acpi_tables.c
index 126708c..f905187 100644
--- a/src/mainboard/compulab/intense_pc/acpi_tables.c
+++ b/src/mainboard/compulab/intense_pc/acpi_tables.c
@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
/* FIXME: check this function. */
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->tcrt = 100;
gnvs->tpsv = 90;
diff --git a/src/mainboard/dell/optiplex_9010/acpi_tables.c b/src/mainboard/dell/optiplex_9010/acpi_tables.c
index 33feed2..28c9d8e 100644
--- a/src/mainboard/dell/optiplex_9010/acpi_tables.c
+++ b/src/mainboard/dell/optiplex_9010/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->tcrt = 100;
gnvs->tpsv = 90;
diff --git a/src/mainboard/emulation/qemu-q35/acpi_tables.c b/src/mainboard/emulation/qemu-q35/acpi_tables.c
index d3492f7..51baae5 100644
--- a/src/mainboard/emulation/qemu-q35/acpi_tables.c
+++ b/src/mainboard/emulation/qemu-q35/acpi_tables.c
@@ -3,6 +3,7 @@
#include <types.h>
#include <string.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
@@ -13,7 +14,7 @@
#include "../qemu-i440fx/acpi.h"
#include <southbridge/intel/i82801ix/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
diff --git a/src/mainboard/facebook/fbg1701/acpi_tables.c b/src/mainboard/facebook/fbg1701/acpi_tables.c
index e98df14..5fe4a42 100644
--- a/src/mainboard/facebook/fbg1701/acpi_tables.c
+++ b/src/mainboard/facebook/fbg1701/acpi_tables.c
@@ -1,11 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <arch/ioapic.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
acpi_init_gnvs(gnvs);
diff --git a/src/mainboard/foxconn/d41s/acpi_tables.c b/src/mainboard/foxconn/d41s/acpi_tables.c
index 5583462..496d419 100644
--- a/src/mainboard/foxconn/d41s/acpi_tables.c
+++ b/src/mainboard/foxconn/d41s/acpi_tables.c
@@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
}
diff --git a/src/mainboard/foxconn/g41s-k/acpi_tables.c b/src/mainboard/foxconn/g41s-k/acpi_tables.c
index 6580505..781abcc 100644
--- a/src/mainboard/foxconn/g41s-k/acpi_tables.c
+++ b/src/mainboard/foxconn/g41s-k/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->cmap = 1; /* COM 1 port */
diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c
index 3abf8aa..d555c10 100644
--- a/src/mainboard/getac/p470/acpi_tables.c
+++ b/src/mainboard/getac/p470/acpi_tables.c
@@ -4,12 +4,13 @@
#include <string.h>
#include <console/console.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <device/device.h>
#include <southbridge/intel/i82801gx/nvs.h>
#include "mainboard.h"
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Enable COM port(s) */
gnvs->cmap = 0x01;
diff --git a/src/mainboard/getac/p470/smihandler.c b/src/mainboard/getac/p470/smihandler.c
index 4172e94..145c942 100644
--- a/src/mainboard/getac/p470/smihandler.c
+++ b/src/mainboard/getac/p470/smihandler.c
@@ -14,7 +14,7 @@
/* The southbridge SMI handler checks whether gnvs has a
* valid pointer before calling the trap handler
*/
-extern global_nvs_t *gnvs;
+extern struct global_nvs *gnvs;
int mainboard_io_trap_handler(int smif)
{
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c
index 5583462..496d419 100644
--- a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c
@@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
}
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
index a889b9f..3012052 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c
index 68d0e8e..f7296e1 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->lptp = 0; /* LPT port */
diff --git a/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c b/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c
index 47cf3c2..852b0b4 100644
--- a/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c
+++ b/src/mainboard/gigabyte/ga-h61m-series/acpi_tables.c
@@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
}
diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c
index 4c72f3e..10dc637 100644
--- a/src/mainboard/google/auron/acpi_tables.c
+++ b/src/mainboard/google/auron/acpi_tables.c
@@ -2,11 +2,12 @@
#include <arch/ioapic.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
#include <variant/thermal.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
acpi_init_gnvs(gnvs);
diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c
index d2f7f45..a34a1e9 100644
--- a/src/mainboard/google/beltino/acpi_tables.c
+++ b/src/mainboard/google/beltino/acpi_tables.c
@@ -2,6 +2,7 @@
#include <types.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <device/device.h>
#include <ec/google/chromeec/ec.h>
#include <southbridge/intel/lynxpoint/nvs.h>
@@ -9,7 +10,7 @@
#include <vendorcode/google/chromeos/gnvs.h>
#include <variant/thermal.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Enable USB ports in S3 */
gnvs->s3u0 = 1;
diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c
index 9680e8f..7ac37b2 100644
--- a/src/mainboard/google/butterfly/acpi_tables.c
+++ b/src/mainboard/google/butterfly/acpi_tables.c
@@ -1,10 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include "thermal.h"
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Disable USB ports in S3 by default */
gnvs->s3u0 = 0;
diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/mainboard_smi.c
index d4f2b99..4d5bc4f 100644
--- a/src/mainboard/google/butterfly/mainboard_smi.c
+++ b/src/mainboard/google/butterfly/mainboard_smi.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <southbridge/intel/bd82x6x/nvs.h>
diff --git a/src/mainboard/google/cyan/acpi_tables.c b/src/mainboard/google/cyan/acpi_tables.c
index a99c413..2f2f298 100644
--- a/src/mainboard/google/cyan/acpi_tables.c
+++ b/src/mainboard/google/cyan/acpi_tables.c
@@ -1,11 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <arch/ioapic.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
acpi_init_gnvs(gnvs);
diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c
index c566d84..1b96df6 100644
--- a/src/mainboard/google/jecht/acpi_tables.c
+++ b/src/mainboard/google/jecht/acpi_tables.c
@@ -2,13 +2,14 @@
#include <types.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <arch/ioapic.h>
#include <device/device.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
#include <variant/thermal.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
acpi_init_gnvs(gnvs);
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c
index 5e1bdf4..d67cdec 100644
--- a/src/mainboard/google/kahlee/mainboard.c
+++ b/src/mainboard/google/kahlee/mainboard.c
@@ -163,7 +163,7 @@
static void mainboard_final(void *chip_info)
{
- struct global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = acpi_get_gnvs();
diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c
index 36b635e..f37f37e 100644
--- a/src/mainboard/google/link/acpi_tables.c
+++ b/src/mainboard/google/link/acpi_tables.c
@@ -1,11 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <ec/google/chromeec/ec.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include "thermal.h"
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Disable USB ports in S3 by default */
gnvs->s3u0 = 0;
diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c
index e7ec332..e60ceae 100644
--- a/src/mainboard/google/link/mainboard_smi.c
+++ b/src/mainboard/google/link/mainboard_smi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
#include <southbridge/intel/bd82x6x/nvs.h>
diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c
index 62722ec..a4d3319 100644
--- a/src/mainboard/google/parrot/acpi_tables.c
+++ b/src/mainboard/google/parrot/acpi_tables.c
@@ -2,6 +2,7 @@
#include <types.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <device/device.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <ec/compal/ene932/ec.h>
@@ -12,7 +13,7 @@
#include "thermal.h"
#include "onboard.h"
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Disable USB ports in S3 by default */
gnvs->s3u0 = 0;
diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c
index c336d53..54735ce 100644
--- a/src/mainboard/google/rambi/acpi_tables.c
+++ b/src/mainboard/google/rambi/acpi_tables.c
@@ -2,13 +2,14 @@
#include <types.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <arch/ioapic.h>
#include <device/device.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
#include <soc/iomap.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
acpi_init_gnvs(gnvs);
diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c
index f68a2c3..e6e40aa 100644
--- a/src/mainboard/google/rambi/mainboard_smi.c
+++ b/src/mainboard/google/rambi/mainboard_smi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c
index ba55647..28364c9 100644
--- a/src/mainboard/google/slippy/acpi_tables.c
+++ b/src/mainboard/google/slippy/acpi_tables.c
@@ -2,6 +2,7 @@
#include <types.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <device/device.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <ec/google/chromeec/ec.h>
@@ -10,7 +11,7 @@
#include "thermal.h"
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Enable USB ports in S3 */
gnvs->s3u0 = 1;
diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c
index 08bd4cd..101e8f1 100644
--- a/src/mainboard/google/stout/acpi_tables.c
+++ b/src/mainboard/google/stout/acpi_tables.c
@@ -2,6 +2,7 @@
#include <types.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <device/device.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <bootmode.h>
@@ -13,7 +14,7 @@
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Disable USB ports in S3 by default */
gnvs->s3u0 = 0;
diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c
index cf7fcae..0b6b227 100644
--- a/src/mainboard/google/stout/mainboard_smi.c
+++ b/src/mainboard/google/stout/mainboard_smi.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
diff --git a/src/mainboard/google/zork/mainboard.c b/src/mainboard/google/zork/mainboard.c
index 1ed3e9d..283f0e0 100644
--- a/src/mainboard/google/zork/mainboard.c
+++ b/src/mainboard/google/zork/mainboard.c
@@ -194,7 +194,7 @@
static void mainboard_final(void *chip_info)
{
- struct global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = acpi_get_gnvs();
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c b/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c
index 33feed2..28c9d8e 100644
--- a/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c
+++ b/src/mainboard/hp/compaq_8200_elite_sff/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->tcrt = 100;
gnvs->tpsv = 90;
diff --git a/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c b/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c
index 0ef3566..8999b72 100644
--- a/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c
+++ b/src/mainboard/hp/snb_ivb_laptops/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
// the lid is open by default.
gnvs->lids = 1;
diff --git a/src/mainboard/hp/z220_sff_workstation/acpi_tables.c b/src/mainboard/hp/z220_sff_workstation/acpi_tables.c
index 33feed2..28c9d8e 100644
--- a/src/mainboard/hp/z220_sff_workstation/acpi_tables.c
+++ b/src/mainboard/hp/z220_sff_workstation/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->tcrt = 100;
gnvs->tpsv = 90;
diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c
index 39ccb01..52c2fbb 100644
--- a/src/mainboard/ibase/mb899/acpi_tables.c
+++ b/src/mainboard/ibase/mb899/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Enable both COM ports */
gnvs->cmap = 0x01;
diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c
index 24edfea..d31735d 100644
--- a/src/mainboard/intel/baskingridge/acpi_tables.c
+++ b/src/mainboard/intel/baskingridge/acpi_tables.c
@@ -2,6 +2,7 @@
#include <types.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <device/device.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <southbridge/intel/lynxpoint/pch.h>
@@ -9,7 +10,7 @@
#include "thermal.h"
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Enable USB ports in S3 */
gnvs->s3u0 = 1;
diff --git a/src/mainboard/intel/d510mo/acpi_tables.c b/src/mainboard/intel/d510mo/acpi_tables.c
index 5583462..496d419 100644
--- a/src/mainboard/intel/d510mo/acpi_tables.c
+++ b/src/mainboard/intel/d510mo/acpi_tables.c
@@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
}
diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c
index 5583462..496d419 100644
--- a/src/mainboard/intel/d945gclf/acpi_tables.c
+++ b/src/mainboard/intel/d945gclf/acpi_tables.c
@@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
}
diff --git a/src/mainboard/intel/dcp847ske/acpi_tables.c b/src/mainboard/intel/dcp847ske/acpi_tables.c
index 6078e678..43e5062 100644
--- a/src/mainboard/intel/dcp847ske/acpi_tables.c
+++ b/src/mainboard/intel/dcp847ske/acpi_tables.c
@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Enable USB ports in S3 by default */
gnvs->s3u0 = 1;
diff --git a/src/mainboard/intel/dg41wv/acpi_tables.c b/src/mainboard/intel/dg41wv/acpi_tables.c
index ec9420c..9eef159 100644
--- a/src/mainboard/intel/dg41wv/acpi_tables.c
+++ b/src/mainboard/intel/dg41wv/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->cmap = 0x01; /* Enable COM 1 port */
diff --git a/src/mainboard/intel/dg43gt/acpi_tables.c b/src/mainboard/intel/dg43gt/acpi_tables.c
index 8b1303e..65db55f 100644
--- a/src/mainboard/intel/dg43gt/acpi_tables.c
+++ b/src/mainboard/intel/dg43gt/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801jx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c
index dd98883..2ae7de4 100644
--- a/src/mainboard/intel/emeraldlake2/acpi_tables.c
+++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c
@@ -2,13 +2,14 @@
#include <types.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <device/device.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Enable USB ports in S3 */
gnvs->s3u0 = 1;
diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c
index b939a81..cfe0caa 100644
--- a/src/mainboard/intel/harcuvar/acpi_tables.c
+++ b/src/mainboard/intel/harcuvar/acpi_tables.c
@@ -2,6 +2,7 @@
#include <types.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <device/device.h>
#include <cpu/x86/msr.h>
@@ -11,7 +12,7 @@
extern const unsigned char AmlCode[];
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
acpi_init_gnvs(gnvs);
diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c
index 8e26d3c..2df0d15 100644
--- a/src/mainboard/intel/strago/acpi_tables.c
+++ b/src/mainboard/intel/strago/acpi_tables.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <arch/ioapic.h>
#include <device/device.h>
#include <soc/acpi.h>
@@ -10,7 +11,7 @@
#include <boardid.h>
#include "onboard.h"
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
acpi_init_gnvs(gnvs);
diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c
index 5c7e13e..416f945 100644
--- a/src/mainboard/intel/wtm2/acpi_tables.c
+++ b/src/mainboard/intel/wtm2/acpi_tables.c
@@ -2,13 +2,14 @@
#include <types.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <arch/ioapic.h>
#include <device/device.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
#include "thermal.h"
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
acpi_init_gnvs(gnvs);
diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c
index 39ccb01..52c2fbb 100644
--- a/src/mainboard/kontron/986lcd-m/acpi_tables.c
+++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Enable both COM ports */
gnvs->cmap = 0x01;
diff --git a/src/mainboard/kontron/ktqm77/acpi_tables.c b/src/mainboard/kontron/ktqm77/acpi_tables.c
index a889b9f..3012052 100644
--- a/src/mainboard/kontron/ktqm77/acpi_tables.c
+++ b/src/mainboard/kontron/ktqm77/acpi_tables.c
@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->tcrt = CRITICAL_TEMPERATURE;
gnvs->tpsv = PASSIVE_TEMPERATURE;
diff --git a/src/mainboard/lenovo/l520/acpi_tables.c b/src/mainboard/lenovo/l520/acpi_tables.c
index 23086fc..6f69102 100644
--- a/src/mainboard/lenovo/l520/acpi_tables.c
+++ b/src/mainboard/lenovo/l520/acpi_tables.c
@@ -1,9 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* The lid is open by default */
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/s230u/acpi_tables.c b/src/mainboard/lenovo/s230u/acpi_tables.c
index a0ad250..0f32e9f 100644
--- a/src/mainboard/lenovo/s230u/acpi_tables.c
+++ b/src/mainboard/lenovo/s230u/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* The lid is open by default */
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/t400/acpi_tables.c b/src/mainboard/lenovo/t400/acpi_tables.c
index 91cf2c3..14b5a8b 100644
--- a/src/mainboard/lenovo/t400/acpi_tables.c
+++ b/src/mainboard/lenovo/t400/acpi_tables.c
@@ -2,11 +2,12 @@
#include <arch/ioapic.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
#include <southbridge/intel/i82801ix/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
diff --git a/src/mainboard/lenovo/t410/acpi_tables.c b/src/mainboard/lenovo/t410/acpi_tables.c
index 49ab9ef..f957656 100644
--- a/src/mainboard/lenovo/t410/acpi_tables.c
+++ b/src/mainboard/lenovo/t410/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/ibexpeak/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* The lid is open by default */
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/t420/acpi_tables.c b/src/mainboard/lenovo/t420/acpi_tables.c
index a0ad250..0f32e9f 100644
--- a/src/mainboard/lenovo/t420/acpi_tables.c
+++ b/src/mainboard/lenovo/t420/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* The lid is open by default */
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/t420s/acpi_tables.c b/src/mainboard/lenovo/t420s/acpi_tables.c
index a0ad250..0f32e9f 100644
--- a/src/mainboard/lenovo/t420s/acpi_tables.c
+++ b/src/mainboard/lenovo/t420s/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* The lid is open by default */
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/t430/acpi_tables.c b/src/mainboard/lenovo/t430/acpi_tables.c
index d91d8cd..5cb1fd3 100644
--- a/src/mainboard/lenovo/t430/acpi_tables.c
+++ b/src/mainboard/lenovo/t430/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* The lid is open by default */
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/t430s/acpi_tables.c b/src/mainboard/lenovo/t430s/acpi_tables.c
index a0ad250..0f32e9f 100644
--- a/src/mainboard/lenovo/t430s/acpi_tables.c
+++ b/src/mainboard/lenovo/t430s/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* The lid is open by default */
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/t440p/acpi_tables.c b/src/mainboard/lenovo/t440p/acpi_tables.c
index 11998f1..c235d12 100644
--- a/src/mainboard/lenovo/t440p/acpi_tables.c
+++ b/src/mainboard/lenovo/t440p/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/lynxpoint/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* The lid is open by default. */
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c
index a0ad250..0f32e9f 100644
--- a/src/mainboard/lenovo/t520/acpi_tables.c
+++ b/src/mainboard/lenovo/t520/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* The lid is open by default */
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/t530/acpi_tables.c b/src/mainboard/lenovo/t530/acpi_tables.c
index a0ad250..0f32e9f 100644
--- a/src/mainboard/lenovo/t530/acpi_tables.c
+++ b/src/mainboard/lenovo/t530/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* The lid is open by default */
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c
index 4361410..62fcfe9 100644
--- a/src/mainboard/lenovo/t60/acpi_tables.c
+++ b/src/mainboard/lenovo/t60/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Enable both COM ports */
gnvs->cmap = 0x01;
diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c
index ec9420c..9eef159 100644
--- a/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c
+++ b/src/mainboard/lenovo/thinkcentre_a58/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->pwrs = 1; /* Power state (AC = 1) */
gnvs->cmap = 0x01; /* Enable COM 1 port */
diff --git a/src/mainboard/lenovo/x131e/acpi_tables.c b/src/mainboard/lenovo/x131e/acpi_tables.c
index a0ad250..0f32e9f 100644
--- a/src/mainboard/lenovo/x131e/acpi_tables.c
+++ b/src/mainboard/lenovo/x131e/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* The lid is open by default */
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c
index a0ad250..0f32e9f 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c
+++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* The lid is open by default */
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/x200/acpi_tables.c b/src/mainboard/lenovo/x200/acpi_tables.c
index 91cf2c3..14b5a8b 100644
--- a/src/mainboard/lenovo/x200/acpi_tables.c
+++ b/src/mainboard/lenovo/x200/acpi_tables.c
@@ -2,11 +2,12 @@
#include <arch/ioapic.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
#include <southbridge/intel/i82801ix/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c
index 49ab9ef..f957656 100644
--- a/src/mainboard/lenovo/x201/acpi_tables.c
+++ b/src/mainboard/lenovo/x201/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/ibexpeak/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* The lid is open by default */
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/x220/acpi_tables.c b/src/mainboard/lenovo/x220/acpi_tables.c
index a0ad250..0f32e9f 100644
--- a/src/mainboard/lenovo/x220/acpi_tables.c
+++ b/src/mainboard/lenovo/x220/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* The lid is open by default */
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/x230/acpi_tables.c b/src/mainboard/lenovo/x230/acpi_tables.c
index a0ad250..0f32e9f 100644
--- a/src/mainboard/lenovo/x230/acpi_tables.c
+++ b/src/mainboard/lenovo/x230/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* The lid is open by default */
gnvs->lids = 1;
diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c
index 4361410..62fcfe9 100644
--- a/src/mainboard/lenovo/x60/acpi_tables.c
+++ b/src/mainboard/lenovo/x60/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Enable both COM ports */
gnvs->cmap = 0x01;
diff --git a/src/mainboard/msi/ms7707/acpi_tables.c b/src/mainboard/msi/ms7707/acpi_tables.c
index 33feed2..28c9d8e 100644
--- a/src/mainboard/msi/ms7707/acpi_tables.c
+++ b/src/mainboard/msi/ms7707/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->tcrt = 100;
gnvs->tpsv = 90;
diff --git a/src/mainboard/ocp/tiogapass/acpi_tables.c b/src/mainboard/ocp/tiogapass/acpi_tables.c
index 85372e5..f6947a2 100644
--- a/src/mainboard/ocp/tiogapass/acpi_tables.c
+++ b/src/mainboard/ocp/tiogapass/acpi_tables.c
@@ -1,11 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <intelblocks/acpi.h>
#include <soc/acpi.h>
extern const unsigned char AmlCode[];
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
acpi_init_gnvs(gnvs);
}
diff --git a/src/mainboard/packardbell/ms2290/acpi_tables.c b/src/mainboard/packardbell/ms2290/acpi_tables.c
index 4ecec38..17ed31e 100644
--- a/src/mainboard/packardbell/ms2290/acpi_tables.c
+++ b/src/mainboard/packardbell/ms2290/acpi_tables.c
@@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/ibexpeak/nvs.h>
-void acpi_create_gnvs(global_nvs_t * gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
}
diff --git a/src/mainboard/portwell/m107/acpi_tables.c b/src/mainboard/portwell/m107/acpi_tables.c
index e98df14..5fe4a42 100644
--- a/src/mainboard/portwell/m107/acpi_tables.c
+++ b/src/mainboard/portwell/m107/acpi_tables.c
@@ -1,11 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <arch/ioapic.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
acpi_init_gnvs(gnvs);
diff --git a/src/mainboard/protectli/vault_bsw/acpi_tables.c b/src/mainboard/protectli/vault_bsw/acpi_tables.c
index 1724c71..c40769a 100644
--- a/src/mainboard/protectli/vault_bsw/acpi_tables.c
+++ b/src/mainboard/protectli/vault_bsw/acpi_tables.c
@@ -1,10 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <acpi/acpi_gnvs.h>
#include <arch/ioapic.h>
#include <soc/acpi.h>
#include <string.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
memset(gnvs, 0, sizeof(*gnvs));
diff --git a/src/mainboard/purism/librem_bdw/acpi_tables.c b/src/mainboard/purism/librem_bdw/acpi_tables.c
index 8383f63..ca6f64b0 100644
--- a/src/mainboard/purism/librem_bdw/acpi_tables.c
+++ b/src/mainboard/purism/librem_bdw/acpi_tables.c
@@ -1,11 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <arch/ioapic.h>
#include <soc/acpi.h>
#include <soc/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
acpi_init_gnvs(gnvs);
}
diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c
index 39ccb01..52c2fbb 100644
--- a/src/mainboard/roda/rk886ex/acpi_tables.c
+++ b/src/mainboard/roda/rk886ex/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/i82801gx/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Enable both COM ports */
gnvs->cmap = 0x01;
diff --git a/src/mainboard/roda/rk9/acpi_tables.c b/src/mainboard/roda/rk9/acpi_tables.c
index 7cc2468..b0e8993 100644
--- a/src/mainboard/roda/rk9/acpi_tables.c
+++ b/src/mainboard/roda/rk9/acpi_tables.c
@@ -2,11 +2,12 @@
#include <arch/ioapic.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <arch/smp/mpspec.h>
#include <device/device.h>
#include <southbridge/intel/i82801ix/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->apic = 1;
gnvs->mpen = 1; /* Enable Multi Processing */
diff --git a/src/mainboard/roda/rv11/acpi_tables.c b/src/mainboard/roda/rv11/acpi_tables.c
index 7477796..aea50a1 100644
--- a/src/mainboard/roda/rv11/acpi_tables.c
+++ b/src/mainboard/roda/rv11/acpi_tables.c
@@ -1,10 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include <variant/thermal.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* The lid is open by default */
gnvs->lids = 1;
diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c
index c1489eb..e730bc2 100644
--- a/src/mainboard/samsung/lumpy/acpi_tables.c
+++ b/src/mainboard/samsung/lumpy/acpi_tables.c
@@ -2,6 +2,7 @@
#include <types.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <device/device.h>
#include <ec/acpi/ec.h>
#if CONFIG(CHROMEOS)
@@ -11,7 +12,7 @@
#include "thermal.h"
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/*
* Disable 3G in suspend by default.
diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c
index 9793c1c..dcdd4e5 100644
--- a/src/mainboard/samsung/stumpy/acpi_tables.c
+++ b/src/mainboard/samsung/stumpy/acpi_tables.c
@@ -2,13 +2,14 @@
#include <types.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <device/device.h>
#include <vendorcode/google/chromeos/gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
#include "thermal.h"
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Enable Front USB ports in S3 by default */
gnvs->s3u0 = 1;
diff --git a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c
index d20cbdb..ccbb75c 100644
--- a/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c
+++ b/src/mainboard/sapphire/pureplatinumh61/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->tcrt = 100;
gnvs->tpsv = 90;
diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c
index b939a81..cfe0caa 100644
--- a/src/mainboard/scaleway/tagada/acpi_tables.c
+++ b/src/mainboard/scaleway/tagada/acpi_tables.c
@@ -2,6 +2,7 @@
#include <types.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <device/device.h>
#include <cpu/x86/msr.h>
@@ -11,7 +12,7 @@
extern const unsigned char AmlCode[];
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
acpi_init_gnvs(gnvs);
diff --git a/src/mainboard/supermicro/x10slm-f/acpi_tables.c b/src/mainboard/supermicro/x10slm-f/acpi_tables.c
index 3bc9340..8ec5b11 100644
--- a/src/mainboard/supermicro/x10slm-f/acpi_tables.c
+++ b/src/mainboard/supermicro/x10slm-f/acpi_tables.c
@@ -1,7 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/lynxpoint/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
}
diff --git a/src/mainboard/supermicro/x9scl/acpi_tables.c b/src/mainboard/supermicro/x9scl/acpi_tables.c
index 33feed2..28c9d8e 100644
--- a/src/mainboard/supermicro/x9scl/acpi_tables.c
+++ b/src/mainboard/supermicro/x9scl/acpi_tables.c
@@ -1,8 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <southbridge/intel/bd82x6x/nvs.h>
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
gnvs->tcrt = 100;
gnvs->tpsv = 90;
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 3ddedce..5e18aad 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
@@ -91,7 +92,7 @@
static void lpc_read_resources(struct device *dev)
{
struct resource *res;
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Get the normal pci resources of this device */
pci_dev_read_resources(dev);
@@ -127,7 +128,7 @@
compact_resources(dev);
/* Allocate ACPI NVS in CBMEM */
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
printk(BIOS_DEBUG, "ACPI GNVS at %p\n", gnvs);
}
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c
index 75509eb..3c22f1d 100644
--- a/src/soc/amd/picasso/acpi.c
+++ b/src/soc/amd/picasso/acpi.c
@@ -7,6 +7,7 @@
#include <string.h>
#include <console/console.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <device/pci_ops.h>
#include <arch/ioapic.h>
@@ -244,7 +245,7 @@
return acpi_write_hpet(device, current, rsdp);
}
-static void acpi_create_gnvs(struct global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Clear out GNVS. */
memset(gnvs, 0, sizeof(*gnvs));
@@ -268,7 +269,7 @@
void southbridge_inject_dsdt(const struct device *device)
{
- struct global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h
index e5bc3f3..09f60d7 100644
--- a/src/soc/amd/picasso/include/soc/acpi.h
+++ b/src/soc/amd/picasso/include/soc/acpi.h
@@ -8,8 +8,6 @@
unsigned long southbridge_write_acpi_tables(const struct device *device,
unsigned long current, struct acpi_rsdp *rsdp);
-void southbridge_inject_dsdt(const struct device *device);
-
uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current,
acpi_rsdp_t *rsdp);
diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h
index 83f6afb..214ab1d 100644
--- a/src/soc/amd/picasso/include/soc/nvs.h
+++ b/src/soc/amd/picasso/include/soc/nvs.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
- * NOTE: The layout of the global_nvs_t structure below must match the layout
+ * NOTE: The layout of the global_nvs structure below must match the layout
* in soc/soc/amd/picasso/acpi/globalnvs.asl !!!
*
*/
@@ -14,7 +14,7 @@
#include <vendorcode/google/chromeos/gnvs.h>
#include <soc/southbridge.h>
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
uint8_t pcnt; /* 0x00 - Processor Count */
uint8_t ppcm; /* 0x01 - Max PPC State */
@@ -41,7 +41,8 @@
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
+
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* __SOC_PICASSO_NVS_H__ */
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 45f66d6..cb22195 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -303,7 +303,7 @@
static void set_nvs_sws(void *unused)
{
struct soc_power_reg *sws;
- struct global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
int index;
sws = cbmem_find(CBMEM_ID_POWER_STATE);
@@ -337,7 +337,7 @@
static void set_sb_final_nvs(void)
{
- struct global_nvs_t *gnvs = acpi_get_gnvs();
+ struct global_nvs *gnvs = acpi_get_gnvs();
if (gnvs == NULL)
return;
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 19dee79..81a82c7 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -7,6 +7,7 @@
#include <string.h>
#include <console/console.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <device/pci_ops.h>
#include <arch/ioapic.h>
@@ -219,7 +220,7 @@
return acpi_write_hpet(device, current, rsdp);
}
-static void acpi_create_gnvs(struct global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Clear out GNVS. */
memset(gnvs, 0, sizeof(*gnvs));
@@ -243,7 +244,7 @@
void southbridge_inject_dsdt(const struct device *device)
{
- struct global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h
index c44e934..9617b45 100644
--- a/src/soc/amd/stoneyridge/include/soc/acpi.h
+++ b/src/soc/amd/stoneyridge/include/soc/acpi.h
@@ -14,8 +14,6 @@
unsigned long southbridge_write_acpi_tables(const struct device *device,
unsigned long current, struct acpi_rsdp *rsdp);
-void southbridge_inject_dsdt(const struct device *device);
-
const char *soc_acpi_name(const struct device *dev);
#endif /* __SOC_STONEYRIDGE_ACPI_H__ */
diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h
index 2b949c9..864cfff 100644
--- a/src/soc/amd/stoneyridge/include/soc/nvs.h
+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
- * NOTE: The layout of the global_nvs_t structure below must match the layout
+ * NOTE: The layout of the global_nvs structure below must match the layout
* in soc/soc/amd/stoneyridge/acpi/globalnvs.asl !!!
*
*/
@@ -14,7 +14,7 @@
#include <vendorcode/google/chromeos/gnvs.h>
#include <soc/southbridge.h>
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
uint8_t pcnt; /* 0x00 - Processor Count */
uint8_t ppcm; /* 0x01 - Max PPC State */
@@ -46,7 +46,8 @@
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
+
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* __SOC_STONEYRIDGE_NVS_H__ */
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index f217349..15219b4 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -537,7 +537,7 @@
static void set_nvs_sws(void *unused)
{
struct soc_power_reg *sws;
- struct global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
int index;
sws = cbmem_find(CBMEM_ID_POWER_STATE);
@@ -576,7 +576,7 @@
size_t fwsize;
const struct device *sd, *sata;
- struct global_nvs_t *gnvs = acpi_get_gnvs();
+ struct global_nvs *gnvs = acpi_get_gnvs();
if (gnvs == NULL)
return;
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 595e6a2..1c7a04a 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <console/console.h>
#include <device/mmio.h>
@@ -70,7 +71,7 @@
return cstate_map;
}
-void acpi_create_gnvs(struct global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
struct soc_intel_apollolake_config *cfg;
cfg = config_of_soc();
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index f9af4f4..dd7dd1a 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -320,7 +320,7 @@
p2sb_unhide();
/* Allocate ACPI NVS in CBMEM */
- cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs_t));
+ cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
printk(BIOS_INFO, "Skip setting RAPL per configuration\n");
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index 4668e1a..45301c4 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
- * NOTE: The layout of the global_nvs_t structure below must match the layout
+ * NOTE: The layout of the global_nvs structure below must match the layout
* in soc/intel/apollolake/acpi/globalnvs.asl !!!
*
*/
@@ -12,7 +12,7 @@
#include <commonlib/helpers.h>
#include <vendorcode/google/chromeos/gnvs.h>
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
uint8_t pcnt; /* 0x00 - Processor Count */
uint8_t ppcm; /* 0x01 - Max PPC State */
@@ -38,7 +38,8 @@
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
+
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* _SOC_APOLLOLAKE_NVS_H_ */
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index 13acf86..9bcd786 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <device/mmio.h>
#include <arch/smp/mpspec.h>
@@ -57,7 +58,7 @@
}
};
-void acpi_init_gnvs(global_nvs_t *gnvs)
+void acpi_init_gnvs(struct global_nvs *gnvs)
{
/* Set unknown wake source */
gnvs->pm1i = -1;
diff --git a/src/soc/intel/baytrail/include/soc/acpi.h b/src/soc/intel/baytrail/include/soc/acpi.h
index fc8f8ab..98b8283 100644
--- a/src/soc/intel/baytrail/include/soc/acpi.h
+++ b/src/soc/intel/baytrail/include/soc/acpi.h
@@ -7,6 +7,5 @@
#include <soc/nvs.h>
unsigned long acpi_madt_irq_overrides(unsigned long current);
-void acpi_init_gnvs(global_nvs_t *gnvs);
#endif /* _BAYTRAIL_ACPI_H_ */
diff --git a/src/soc/intel/baytrail/include/soc/nvs.h b/src/soc/intel/baytrail/include/soc/nvs.h
index cc70f78..cdffc75 100644
--- a/src/soc/intel/baytrail/include/soc/nvs.h
+++ b/src/soc/intel/baytrail/include/soc/nvs.h
@@ -7,7 +7,7 @@
#include <vendorcode/google/chromeos/gnvs.h>
#include <soc/device_nvs.h>
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -53,12 +53,8 @@
/* Baytrail LPSS (0x1000) */
device_nvs_t dev;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
-void acpi_create_gnvs(global_nvs_t *gnvs);
-
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* _BAYTRAIL_NVS_H_ */
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
index 78638de..3a12a4b 100644
--- a/src/soc/intel/baytrail/lpe.c
+++ b/src/soc/intel/baytrail/lpe.c
@@ -50,7 +50,7 @@
LPE_PCICFGCTR1_ACPI_INT_EN),
REG_SCRIPT_END
};
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c
index d5c3e4d..cdf78b7 100644
--- a/src/soc/intel/baytrail/lpss.c
+++ b/src/soc/intel/baytrail/lpss.c
@@ -28,7 +28,7 @@
REG_SCRIPT_END
};
struct resource *bar;
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index d27a17d..995fe20 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -117,7 +117,7 @@
}
/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
-static void s3_save_acpi_wake_source(global_nvs_t *gnvs)
+static void s3_save_acpi_wake_source(struct global_nvs *gnvs)
{
struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE);
uint16_t pm1;
@@ -144,14 +144,14 @@
static void s3_resume_prepare(void)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (gnvs == NULL)
return;
if (!acpi_is_wakeup_s3())
- memset(gnvs, 0, sizeof(global_nvs_t));
+ memset(gnvs, 0, sizeof(struct global_nvs));
else
s3_save_acpi_wake_source(gnvs);
}
diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c
index 455f243..f178e83 100644
--- a/src/soc/intel/baytrail/scc.c
+++ b/src/soc/intel/baytrail/scc.c
@@ -81,7 +81,7 @@
REG_SCRIPT_END
};
struct resource *bar;
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 91eb6f5..2a56f84 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -19,7 +19,7 @@
#include <soc/nvs.h>
/* GNVS needs to be set by coreboot initiating a software SMI. */
-static global_nvs_t *gnvs;
+static struct global_nvs *gnvs;
static int smm_initialized;
int southbridge_io_trap_handler(int smif)
@@ -44,7 +44,7 @@
enable_smi(EOS);
}
-global_nvs_t *smm_get_gnvs(void)
+struct global_nvs *smm_get_gnvs(void)
{
return gnvs;
}
@@ -330,7 +330,7 @@
state = smi_apmc_find_state_save(reg8);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (global_nvs_t *)((uint32_t)state->rbx);
+ gnvs = (struct global_nvs *)((uint32_t)state->rbx);
smm_initialized = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 679c04d..38f51ff 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -5,6 +5,7 @@
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <bootstate.h>
#include <cbmem.h>
#include <console/console.h>
@@ -482,7 +483,7 @@
static void southcluster_inject_dsdt(const struct device *device)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 1290d62..98d7980 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <device/mmio.h>
#include <arch/smp/mpspec.h>
@@ -61,7 +62,7 @@
}
};
-void acpi_init_gnvs(global_nvs_t *gnvs)
+void acpi_init_gnvs(struct global_nvs *gnvs)
{
/* Set unknown wake source */
gnvs->pm1i = -1;
@@ -493,7 +494,7 @@
void southcluster_inject_dsdt(const struct device *device)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/soc/intel/braswell/include/soc/acpi.h b/src/soc/intel/braswell/include/soc/acpi.h
index 5bff07a..cd54f2c 100644
--- a/src/soc/intel/braswell/include/soc/acpi.h
+++ b/src/soc/intel/braswell/include/soc/acpi.h
@@ -8,7 +8,6 @@
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
unsigned long acpi_madt_irq_overrides(unsigned long current);
-void acpi_init_gnvs(global_nvs_t *gnvs);
void southcluster_inject_dsdt(const struct device *device);
unsigned long southcluster_write_acpi_tables(const struct device *device,
unsigned long current, struct acpi_rsdp *rsdp);
diff --git a/src/soc/intel/braswell/include/soc/nvs.h b/src/soc/intel/braswell/include/soc/nvs.h
index 22ea10f..35ab47a 100644
--- a/src/soc/intel/braswell/include/soc/nvs.h
+++ b/src/soc/intel/braswell/include/soc/nvs.h
@@ -7,7 +7,7 @@
#include <soc/device_nvs.h>
#include <vendorcode/google/chromeos/gnvs.h>
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -55,11 +55,8 @@
/* LPSS (0x1000) */
device_nvs_t dev;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
-void acpi_create_gnvs(global_nvs_t *gnvs);
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif /* _SOC_NVS_H_ */
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index f3391de..0fb4ca9 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -53,7 +53,7 @@
REG_SCRIPT_END
};
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c
index 8200248..d9027f5 100644
--- a/src/soc/intel/braswell/lpss.c
+++ b/src/soc/intel/braswell/lpss.c
@@ -27,7 +27,7 @@
REG_SCRIPT_END
};
struct resource *bar;
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 893a6b6..eba1527 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -137,16 +137,16 @@
static void s3_resume_prepare(void)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (!acpi_is_wakeup_s3() && gnvs)
- memset(gnvs, 0, sizeof(global_nvs_t));
+ memset(gnvs, 0, sizeof(struct global_nvs));
}
static void set_board_id(void)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/soc/intel/braswell/scc.c b/src/soc/intel/braswell/scc.c
index 0b6385f..6f23fda 100644
--- a/src/soc/intel/braswell/scc.c
+++ b/src/soc/intel/braswell/scc.c
@@ -12,7 +12,7 @@
void scc_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
{
struct resource *bar;
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
printk(BIOS_SPEW, "%s/%s (%s, 0x%08x, 0x%08x)\n",
__FILE__, __func__, dev_name(dev), iosf_reg, nvs_index);
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index 614f56d..28765d0 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -19,7 +19,7 @@
#include <smmstore.h>
/* GNVS needs to be set by coreboot initiating a software SMI. */
-static global_nvs_t *gnvs;
+static struct global_nvs *gnvs;
static int smm_initialized;
int southbridge_io_trap_handler(int smif)
@@ -45,7 +45,7 @@
enable_smi(EOS);
}
-global_nvs_t *smm_get_gnvs(void)
+struct global_nvs *smm_get_gnvs(void)
{
return gnvs;
}
@@ -307,7 +307,7 @@
state = smi_apmc_find_state_save(reg8);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (global_nvs_t *)((uint32_t)state->rbx);
+ gnvs = (struct global_nvs *)((uint32_t)state->rbx);
smm_initialized = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index 43ff8eb..306d72f 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <arch/smp/mpspec.h>
#include <cbmem.h>
@@ -148,7 +149,7 @@
return cores;
}
-void acpi_init_gnvs(global_nvs_t *gnvs)
+void acpi_init_gnvs(struct global_nvs *gnvs)
{
/* Set unknown wake source */
gnvs->pm1i = -1;
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c
index 897f9c4..15858e1 100644
--- a/src/soc/intel/broadwell/adsp.c
+++ b/src/soc/intel/broadwell/adsp.c
@@ -80,7 +80,7 @@
if (config->sio_acpi_mode) {
/* Configure for ACPI mode */
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n");
diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h
index 46cc42a..0bf63a4 100644
--- a/src/soc/intel/broadwell/include/soc/acpi.h
+++ b/src/soc/intel/broadwell/include/soc/acpi.h
@@ -13,7 +13,6 @@
#define PSS_LATENCY_BUSMASTER 10
unsigned long acpi_madt_irq_overrides(unsigned long current);
-void acpi_init_gnvs(global_nvs_t *gnvs);
unsigned long northbridge_write_acpi_tables(const struct device *dev,
unsigned long current, struct acpi_rsdp *rsdp);
#endif
diff --git a/src/soc/intel/broadwell/include/soc/nvs.h b/src/soc/intel/broadwell/include/soc/nvs.h
index 8772a02..afeed6f 100644
--- a/src/soc/intel/broadwell/include/soc/nvs.h
+++ b/src/soc/intel/broadwell/include/soc/nvs.h
@@ -7,7 +7,7 @@
#include <soc/device_nvs.h>
#include <vendorcode/google/chromeos/gnvs.h>
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -45,12 +45,8 @@
/* Device specific (0x1000) */
device_nvs_t dev;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
-void acpi_create_gnvs(global_nvs_t *gnvs);
-
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 1e96286..58cd35d 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -11,6 +11,7 @@
#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h>
#include <cbmem.h>
#include <reg_script.h>
@@ -553,7 +554,7 @@
static void pch_lpc_read_resources(struct device *dev)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
@@ -565,14 +566,14 @@
pch_lpc_add_io_resources(dev);
/* Allocate ACPI NVS in CBMEM */
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (!acpi_is_wakeup_s3() && gnvs)
- memset(gnvs, 0, sizeof(global_nvs_t));
+ memset(gnvs, 0, sizeof(struct global_nvs));
}
static void southcluster_inject_dsdt(const struct device *device)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c
index 39550b7..c414d62 100644
--- a/src/soc/intel/broadwell/ramstage.c
+++ b/src/soc/intel/broadwell/ramstage.c
@@ -32,14 +32,14 @@
static void s3_resume_prepare(void)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (gnvs == NULL)
return;
if (!acpi_is_wakeup_s3())
- memset(gnvs, 0, sizeof(global_nvs_t));
+ memset(gnvs, 0, sizeof(struct global_nvs));
}
void broadwell_init_pre_device(void *chip_info)
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index 4da3979..dbe194a 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -233,7 +233,7 @@
}
if (config->sio_acpi_mode) {
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/broadwell/smihandler.c b/src/soc/intel/broadwell/smihandler.c
index 85d6ae0..c7cefdc 100644
--- a/src/soc/intel/broadwell/smihandler.c
+++ b/src/soc/intel/broadwell/smihandler.c
@@ -29,8 +29,8 @@
* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
* by coreboot.
*/
-static global_nvs_t *gnvs;
-global_nvs_t *smm_get_gnvs(void)
+static struct global_nvs *gnvs;
+struct global_nvs *smm_get_gnvs(void)
{
return gnvs;
}
@@ -350,7 +350,7 @@
state = smi_apmc_find_state_save(reg8);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (global_nvs_t *)((u32)state->rbx);
+ gnvs = (struct global_nvs *)((u32)state->rbx);
smm_initialized = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index c041eb0..1f3fbec 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <arch/smp/mpspec.h>
#include <cbmem.h>
@@ -182,7 +183,7 @@
return read32((void *)pmc_bar + IRQ_REG);
}
-void acpi_create_gnvs(struct global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
const struct soc_intel_cannonlake_config *config;
config = config_of_soc();
diff --git a/src/soc/intel/common/acpi_wake_source.c b/src/soc/intel/common/acpi_wake_source.c
index 1342c80..f30ef9f 100644
--- a/src/soc/intel/common/acpi_wake_source.c
+++ b/src/soc/intel/common/acpi_wake_source.c
@@ -16,7 +16,7 @@
/* Save wake source data for ACPI _SWS methods in NVS */
static void acpi_save_wake_source(void *unused)
{
- global_nvs_t *gnvs = acpi_get_gnvs();
+ struct global_nvs *gnvs = acpi_get_gnvs();
uint32_t pm1, *gpe0;
int gpe_reg, gpe_reg_count;
int reg_size = sizeof(uint32_t) * 8;
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index 3265131..5e4c6e8 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -222,13 +222,13 @@
}
#endif
-__weak void acpi_create_gnvs(struct global_nvs_t *gnvs)
+__weak void acpi_create_gnvs(struct global_nvs *gnvs)
{
}
void southbridge_inject_dsdt(const struct device *device)
{
- struct global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
@@ -457,7 +457,7 @@
/* Save wake source data for ACPI _SWS methods in NVS */
static void acpi_save_wake_source(void *unused)
{
- global_nvs_t *gnvs = acpi_get_gnvs();
+ struct global_nvs *gnvs = acpi_get_gnvs();
uint32_t pm1, *gpe0;
int gpe_reg, gpe_reg_count;
int reg_size = sizeof(uint32_t) * 8;
diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h
index 19dd68a..21664c8 100644
--- a/src/soc/intel/common/block/include/intelblocks/acpi.h
+++ b/src/soc/intel/common/block/include/intelblocks/acpi.h
@@ -12,7 +12,7 @@
struct chipset_power_state;
/* Forward declare the global nvs structure here */
-struct global_nvs_t;
+struct global_nvs;
/* Return ACPI name for this device */
const char *soc_acpi_name(const struct device *dev);
@@ -32,19 +32,6 @@
struct acpi_rsdp *rsdp);
/*
- * Creates acpi gnvs and adds it to the DSDT table.
- * GNVS creation is chipset specific and is done in soc specific acpi.c file.
- */
-void southbridge_inject_dsdt(const struct device *device);
-
-/*
- * This function populates the gnvs structure in acpi table.
- * Defined as weak in common acpi as gnvs structure definition is
- * chipset specific.
- */
-void acpi_create_gnvs(struct global_nvs_t *gnvs);
-
-/*
* get_cstate_map returns a table of processor specific acpi_cstate_t entries
* and number of entries in the table
*/
diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h
index e1040ea..cc240c5 100644
--- a/src/soc/intel/common/block/include/intelblocks/nvs.h
+++ b/src/soc/intel/common/block/include/intelblocks/nvs.h
@@ -6,7 +6,7 @@
#include <commonlib/helpers.h>
#include <vendorcode/google/chromeos/gnvs.h>
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - 0x01 Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -31,7 +31,8 @@
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
+
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif
diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h
index e6c9905..56e4a16 100644
--- a/src/soc/intel/common/block/include/intelblocks/sgx.h
+++ b/src/soc/intel/common/block/include/intelblocks/sgx.h
@@ -18,6 +18,6 @@
void sgx_configure(void *unused);
/* Fill GNVS data with SGX status, EPC base and length */
-void sgx_fill_gnvs(global_nvs_t *gnvs);
+void sgx_fill_gnvs(struct global_nvs *gnvs);
#endif /* SOC_INTEL_COMMON_BLOCK_SGX_H */
diff --git a/src/soc/intel/common/block/include/intelblocks/smihandler.h b/src/soc/intel/common/block/include/intelblocks/smihandler.h
index 428a9f3..7cea1dd 100644
--- a/src/soc/intel/common/block/include/intelblocks/smihandler.h
+++ b/src/soc/intel/common/block/include/intelblocks/smihandler.h
@@ -7,7 +7,7 @@
#include <stdint.h>
struct gpi_status;
-struct global_nvs_t;
+struct global_nvs;
/*
* The register value is used with get_reg and set_reg
@@ -127,11 +127,6 @@
void smihandler_southbridge_espi(
const struct smm_save_state_ops *save_state_ops);
-/*
- * Returns gnvs pointer within SMM context
- */
-struct global_nvs_t *smm_get_gnvs(void);
-
/* SoC overrides. */
/* Specific SOC SMI handler during ramstage finalize phase */
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
index ae72116..cf56138 100644
--- a/src/soc/intel/common/block/include/intelblocks/systemagent.h
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -71,7 +71,7 @@
/* API to get TSEG size */
size_t sa_get_tseg_size(void);
/* Fill MMIO resource above 4GB into GNVS */
-void sa_fill_gnvs(global_nvs_t *gnvs);
+void sa_fill_gnvs(struct global_nvs *gnvs);
/*
* SoC overrides
*
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c
index 9fe48d1f..ea85911 100644
--- a/src/soc/intel/common/block/lpc/lpc.c
+++ b/src/soc/intel/common/block/lpc/lpc.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <acpi/acpi_gnvs.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c
index 56648c8..8679f1f 100644
--- a/src/soc/intel/common/block/sgx/sgx.c
+++ b/src/soc/intel/common/block/sgx/sgx.c
@@ -235,7 +235,7 @@
activate_sgx();
}
-void sgx_fill_gnvs(global_nvs_t *gnvs)
+void sgx_fill_gnvs(struct global_nvs *gnvs)
{
struct cpuid_result cpuid_regs;
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index ab5e9c2..73dfda5 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -27,7 +27,7 @@
#include <stdint.h>
/* GNVS needs to be set by coreboot initiating a software SMI. */
-static struct global_nvs_t *gnvs;
+static struct global_nvs *gnvs;
/* SoC overrides. */
@@ -125,7 +125,7 @@
pmc_enable_smi(EOS);
}
-struct global_nvs_t *smm_get_gnvs(void)
+struct global_nvs *smm_get_gnvs(void)
{
return gnvs;
}
@@ -380,7 +380,7 @@
if (state) {
/* EBX in the state save contains the GNVS pointer */
uint32_t reg_ebx = save_state_ops->get_reg(state, RBX);
- gnvs = (struct global_nvs_t *)(uintptr_t)reg_ebx;
+ gnvs = (struct global_nvs *)(uintptr_t)reg_ebx;
smm_initialized = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c
index 1e9f4d9..1d6fb81 100644
--- a/src/soc/intel/common/block/smm/smitraphandler.c
+++ b/src/soc/intel/common/block/smm/smitraphandler.c
@@ -24,7 +24,7 @@
/* Inherited from cpu/x86/smm.h resulting in a different signature */
int southbridge_io_trap_handler(int smif)
{
- global_nvs_t *gnvs = smm_get_gnvs();
+ struct global_nvs *gnvs = smm_get_gnvs();
switch (smif) {
case 0x32:
printk(BIOS_DEBUG, "OS Init\n");
@@ -61,7 +61,7 @@
u32 data, mask = 0;
u8 trap_sts;
int i;
- global_nvs_t *gnvs = smm_get_gnvs();
+ struct global_nvs *gnvs = smm_get_gnvs();
/* TRSR - Trap Status Register */
trap_sts = pcr_read8(PID_PSTH, PCR_PSTH_TRPST);
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c
index d25e1aa..e6bbfc7 100644
--- a/src/soc/intel/common/block/systemagent/systemagent.c
+++ b/src/soc/intel/common/block/systemagent/systemagent.c
@@ -103,7 +103,7 @@
}
/* Fill MMIO resource above 4GB into GNVS */
-void sa_fill_gnvs(global_nvs_t *gnvs)
+void sa_fill_gnvs(struct global_nvs *gnvs)
{
struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 0c641f3..fac0577 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -167,7 +167,7 @@
*/
static bool pch_uart_init_debug_controller_on_resume(void)
{
- global_nvs_t *gnvs = acpi_get_gnvs();
+ struct global_nvs *gnvs = acpi_get_gnvs();
if (gnvs)
return !!gnvs->uior;
diff --git a/src/soc/intel/common/nhlt.c b/src/soc/intel/common/nhlt.c
index 099be5d..39baf01 100644
--- a/src/soc/intel/common/nhlt.c
+++ b/src/soc/intel/common/nhlt.c
@@ -13,7 +13,7 @@
uintptr_t acpi_addr, const char *oem_id, const char *oem_table_id,
uint32_t oem_revision)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = acpi_get_gnvs();
diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c
index 3f416b6..92a9c2a 100644
--- a/src/soc/intel/denverton_ns/acpi.c
+++ b/src/soc/intel/denverton_ns/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <arch/smp/mpspec.h>
#include <cpu/x86/smm.h>
@@ -57,7 +58,7 @@
}
};
-void acpi_init_gnvs(global_nvs_t *gnvs)
+void acpi_init_gnvs(struct global_nvs *gnvs)
{
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
@@ -280,7 +281,7 @@
void southcluster_inject_dsdt(const struct device *device)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/soc/intel/denverton_ns/include/soc/acpi.h b/src/soc/intel/denverton_ns/include/soc/acpi.h
index 00700a6..9bc5ed0 100644
--- a/src/soc/intel/denverton_ns/include/soc/acpi.h
+++ b/src/soc/intel/denverton_ns/include/soc/acpi.h
@@ -8,7 +8,6 @@
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
unsigned long acpi_madt_irq_overrides(unsigned long current);
-void acpi_init_gnvs(global_nvs_t *gnvs);
unsigned long southcluster_write_acpi_tables(const struct device *device,
unsigned long current,
struct acpi_rsdp *rsdp);
diff --git a/src/soc/intel/denverton_ns/include/soc/nvs.h b/src/soc/intel/denverton_ns/include/soc/nvs.h
index 0195643..4aaabc9 100644
--- a/src/soc/intel/denverton_ns/include/soc/nvs.h
+++ b/src/soc/intel/denverton_ns/include/soc/nvs.h
@@ -3,7 +3,7 @@
#ifndef _DENVERTON_NS_NVS_H_
#define _DENVERTON_NS_NVS_H_
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -47,9 +47,6 @@
u32 tsegl; /* 0x58 - TSEG Length/Size */
u8 rsvd3[164];
-} __packed global_nvs_t;
-
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
+};
#endif /* _DENVERTON_NS_NVS_H_ */
diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c
index b81eb11..aa87630 100644
--- a/src/soc/intel/denverton_ns/smihandler.c
+++ b/src/soc/intel/denverton_ns/smihandler.c
@@ -17,7 +17,7 @@
#include <soc/nvs.h>
/* GNVS needs to be set by coreboot initiating a software SMI. */
-static global_nvs_t *gnvs;
+static struct global_nvs *gnvs;
static int smm_initialized;
int southbridge_io_trap_handler(int smif)
@@ -39,7 +39,7 @@
void southbridge_smi_set_eos(void) { enable_smi(EOS); }
-global_nvs_t *smm_get_gnvs(void) { return gnvs; }
+struct global_nvs *smm_get_gnvs(void) { return gnvs; }
static void busmaster_disable_on_bus(int bus)
{
@@ -241,7 +241,7 @@
state = smi_apmc_find_state_save(reg8);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (global_nvs_t *)((uint32_t)state->rbx);
+ gnvs = (struct global_nvs *)((uint32_t)state->rbx);
smm_initialized = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
diff --git a/src/soc/intel/icelake/acpi.c b/src/soc/intel/icelake/acpi.c
index 796e770..ece28cc 100644
--- a/src/soc/intel/icelake/acpi.c
+++ b/src/soc/intel/icelake/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <device/mmio.h>
#include <arch/smp/mpspec.h>
@@ -178,7 +179,7 @@
return read32((void *)pmc_bar + IRQ_REG);
}
-void acpi_create_gnvs(struct global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
config_t *config = config_of_soc();
diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c
index 88ec5fe..9d5080b 100644
--- a/src/soc/intel/jasperlake/acpi.c
+++ b/src/soc/intel/jasperlake/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <device/mmio.h>
#include <arch/smp/mpspec.h>
@@ -272,7 +273,7 @@
return current;
}
-void acpi_create_gnvs(struct global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
config_t *config = config_of_soc();
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 6fde1e2..6da43e9 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <arch/cpu.h>
#include <arch/ioapic.h>
@@ -155,7 +156,7 @@
return cores;
}
-static void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
const struct soc_intel_skylake_config *config = config_of_soc();
@@ -643,7 +644,7 @@
void southbridge_inject_dsdt(const struct device *device)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/soc/intel/skylake/include/soc/acpi.h b/src/soc/intel/skylake/include/soc/acpi.h
index 3422ece..bf81afb 100644
--- a/src/soc/intel/skylake/include/soc/acpi.h
+++ b/src/soc/intel/skylake/include/soc/acpi.h
@@ -13,7 +13,6 @@
#define PSS_LATENCY_BUSMASTER 10
unsigned long acpi_madt_irq_overrides(unsigned long current);
-void southbridge_inject_dsdt(const struct device *device);
unsigned long southbridge_write_acpi_tables(const struct device *device,
unsigned long current, struct acpi_rsdp *rsdp);
unsigned long northbridge_write_acpi_tables(const struct device *,
diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h
index 4973597..87f16fb 100644
--- a/src/soc/intel/skylake/include/soc/nvs.h
+++ b/src/soc/intel/skylake/include/soc/nvs.h
@@ -6,7 +6,7 @@
#include <commonlib/helpers.h>
#include <vendorcode/google/chromeos/gnvs.h>
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -51,7 +51,8 @@
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
+
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
#endif
diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c
index 0991134..4b31c6d 100644
--- a/src/soc/intel/tigerlake/acpi.c
+++ b/src/soc/intel/tigerlake/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <device/mmio.h>
#include <arch/smp/mpspec.h>
@@ -272,7 +273,7 @@
return current;
}
-void acpi_create_gnvs(struct global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
config_t *config = config_of_soc();
diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c
index e52d75d..c554977 100644
--- a/src/soc/intel/xeon_sp/cpx/acpi.c
+++ b/src/soc/intel/xeon_sp/cpx/acpi.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <arch/ioapic.h>
#include <arch/smp/mpspec.h>
@@ -108,7 +109,7 @@
void southbridge_inject_dsdt(const struct device *device)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
@@ -133,7 +134,7 @@
uncore_inject_dsdt();
}
-void acpi_create_gnvs(struct global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h b/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h
index 08ad0f7..becdd76 100644
--- a/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h
+++ b/src/soc/intel/xeon_sp/cpx/include/soc/nvs.h
@@ -8,10 +8,10 @@
/* TODO - this requires xeon sp, server board support */
/* NOTE: We do not use intelblocks/nvs.h since it includes
mostly client specific attributes */
-typedef struct global_nvs_t {
+struct __packed global_nvs {
uint8_t pcnt; /* 0x00 - Processor Count */
uint32_t cbmc; /* 0x01 - coreboot memconsole */
uint8_t rsvd3[251];
-} __packed global_nvs_t;
+};
#endif /* _SOC_NVS_H_ */
diff --git a/src/soc/intel/xeon_sp/skx/acpi.c b/src/soc/intel/xeon_sp/skx/acpi.c
index 606bfed..903fc73 100644
--- a/src/soc/intel/xeon_sp/skx/acpi.c
+++ b/src/soc/intel/xeon_sp/skx/acpi.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <assert.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <arch/smp/mpspec.h>
#include <intelblocks/acpi.h>
@@ -47,7 +48,7 @@
return sci_irq;
}
-void acpi_init_gnvs(global_nvs_t *gnvs)
+void acpi_init_gnvs(struct global_nvs *gnvs)
{
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
@@ -956,7 +957,7 @@
void southbridge_inject_dsdt(const struct device *device)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h
index c1d61c9..0e00c2b 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/acpi.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/acpi.h
@@ -14,7 +14,6 @@
void acpi_create_serialio_ssdt(acpi_header_t *ssdt);
unsigned long acpi_madt_irq_overrides(unsigned long current);
-void acpi_init_gnvs(global_nvs_t *gnvs);
unsigned long northbridge_write_acpi_tables(const struct device *device,
unsigned long current, struct acpi_rsdp *rsdp);
void uncore_inject_dsdt(void);
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/nvs.h b/src/soc/intel/xeon_sp/skx/include/soc/nvs.h
index 08ad0f7..becdd76 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/nvs.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/nvs.h
@@ -8,10 +8,10 @@
/* TODO - this requires xeon sp, server board support */
/* NOTE: We do not use intelblocks/nvs.h since it includes
mostly client specific attributes */
-typedef struct global_nvs_t {
+struct __packed global_nvs {
uint8_t pcnt; /* 0x00 - Processor Count */
uint32_t cbmc; /* 0x01 - coreboot memconsole */
uint8_t rsvd3[251];
-} __packed global_nvs_t;
+};
#endif /* _SOC_NVS_H_ */
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index e41bca2..80d3a46 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -12,6 +12,7 @@
#include <arch/io.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <acpi/acpigen.h>
#include <cpu/x86/smm.h>
#include <cbmem.h>
@@ -647,9 +648,9 @@
pch_enable(dev);
}
-static void southbridge_inject_dsdt(const struct device *dev)
+void southbridge_inject_dsdt(const struct device *dev)
{
- global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
+ struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs) {
memset(gnvs, 0, sizeof(*gnvs));
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h
index 075eae0..ae3304e 100644
--- a/src/southbridge/intel/bd82x6x/nvs.h
+++ b/src/southbridge/intel/bd82x6x/nvs.h
@@ -4,7 +4,7 @@
#include <stdint.h>
#include "vendorcode/google/chromeos/gnvs.h"
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -102,9 +102,6 @@
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
-void acpi_create_gnvs(global_nvs_t *gnvs);
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index 83799bee..b257fb6 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -17,8 +17,8 @@
#include "pch.h"
#include "nvs.h"
-static global_nvs_t *gnvs;
-global_nvs_t *smm_get_gnvs(void)
+static struct global_nvs *gnvs;
+struct global_nvs *smm_get_gnvs(void)
{
return gnvs;
}
@@ -196,7 +196,7 @@
smi_apmc_find_state_save(apm_cnt);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (global_nvs_t *)((u32)state->rbx);
+ gnvs = (struct global_nvs *)((u32)state->rbx);
*smm_done = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
diff --git a/src/southbridge/intel/i82801dx/nvs.h b/src/southbridge/intel/i82801dx/nvs.h
index 9bd1678..3cd0afb 100644
--- a/src/southbridge/intel/i82801dx/nvs.h
+++ b/src/southbridge/intel/i82801dx/nvs.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-typedef struct {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -95,4 +95,4 @@
u8 dock; /* 0xf0 - Docking Status */
u8 bten;
u8 rsvd13[14];
-} __packed global_nvs_t;
+};
diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c
index b526a1a..7cd5c70 100644
--- a/src/southbridge/intel/i82801dx/smihandler.c
+++ b/src/southbridge/intel/i82801dx/smihandler.c
@@ -33,7 +33,7 @@
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
* by coreboot.
*/
-global_nvs_t *gnvs = (global_nvs_t *)0x0;
+struct global_nvs *gnvs = (struct global_nvs *)0x0;
void *tcg = (void *)0x0;
void *smi1 = (void *)0x0;
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 3b204d4..9b32f6c 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -12,6 +12,7 @@
#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h>
#include <acpi/acpigen.h>
#include <arch/smp/mpspec.h>
@@ -490,9 +491,9 @@
outb(POST_OS_BOOT, 0x80);
}
-static void southbridge_inject_dsdt(const struct device *dev)
+void southbridge_inject_dsdt(const struct device *dev)
{
- global_nvs_t *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
+ struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs) {
memset(gnvs, 0, sizeof(*gnvs));
diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h
index 3f44330..d2efc5c 100644
--- a/src/southbridge/intel/i82801gx/nvs.h
+++ b/src/southbridge/intel/i82801gx/nvs.h
@@ -2,9 +2,10 @@
#ifndef SOUTHBRIDGE_INTEL_I82801GX_NVS_H
#define SOUTHBRIDGE_INTEL_I82801GX_NVS_H
+
#include <stdint.h>
-typedef struct {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -96,8 +97,6 @@
u8 dock; /* 0xf0 - Docking Status */
u8 bten;
u8 rsvd13[14];
-} __packed global_nvs_t;
-
-void acpi_create_gnvs(global_nvs_t *gnvs);
+};
#endif /* SOUTHBRIDGE_INTEL_I82801GX_NVS_H */
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index ad0d358..1757872 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -22,11 +22,11 @@
u8 smm_initialized = 0;
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located by coreboot. */
-global_nvs_t *gnvs = (global_nvs_t *)0x0;
+struct global_nvs *gnvs = (struct global_nvs *)0x0;
void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)
{
- gnvs = *(global_nvs_t **)0x500;
+ gnvs = *(struct global_nvs **)0x500;
*smm_done = 1;
}
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 7ddd883..883c964 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -12,6 +12,7 @@
#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h>
#include <acpi/acpigen.h>
#include <cbmem.h>
@@ -456,9 +457,9 @@
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
-static void southbridge_inject_dsdt(const struct device *dev)
+void southbridge_inject_dsdt(const struct device *dev)
{
- global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
+ struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs) {
memset(gnvs, 0, sizeof(*gnvs));
diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h
index 3cd4c58..e0e6bbd 100644
--- a/src/southbridge/intel/i82801ix/nvs.h
+++ b/src/southbridge/intel/i82801ix/nvs.h
@@ -2,9 +2,10 @@
#ifndef SOUTHBRIDGE_INTEL_I82801IX_NVS_H
#define SOUTHBRIDGE_INTEL_I82801IX_NVS_H
+
#include <stdint.h>
-typedef struct {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -96,8 +97,6 @@
u8 dock; /* 0xf0 - Docking Status */
u8 bten;
u8 rsvd13[14];
-} __packed global_nvs_t;
-
-void acpi_create_gnvs(global_nvs_t *gnvs);
+};
#endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */
diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c
index df3026e..070b7a6 100644
--- a/src/southbridge/intel/i82801ix/smihandler.c
+++ b/src/southbridge/intel/i82801ix/smihandler.c
@@ -12,7 +12,7 @@
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
* by coreboot.
*/
-global_nvs_t *gnvs = (global_nvs_t *)0x0;
+struct global_nvs *gnvs = (struct global_nvs *)0x0;
void *tcg = (void *)0x0;
void *smi1 = (void *)0x0;
@@ -35,7 +35,7 @@
void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)
{
- gnvs = *(global_nvs_t **)0x500;
+ gnvs = *(struct global_nvs **)0x500;
tcg = *(void **)0x504;
smi1 = *(void **)0x508;
*smm_done = 1;
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index c36009e..2533d8c 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -12,6 +12,7 @@
#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h>
#include <acpi/acpigen.h>
#include <arch/smp/mpspec.h>
@@ -497,9 +498,9 @@
}
}
-static void southbridge_inject_dsdt(const struct device *dev)
+void southbridge_inject_dsdt(const struct device *dev)
{
- global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
+ struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs) {
memset(gnvs, 0, sizeof(*gnvs));
diff --git a/src/southbridge/intel/i82801jx/nvs.h b/src/southbridge/intel/i82801jx/nvs.h
index c487918..48a7d87 100644
--- a/src/southbridge/intel/i82801jx/nvs.h
+++ b/src/southbridge/intel/i82801jx/nvs.h
@@ -4,7 +4,7 @@
#define SOUTHBRIDGE_INTEL_I82801JX_NVS_H
#include <stdint.h>
-typedef struct {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -96,8 +96,6 @@
u8 dock; /* 0xf0 - Docking Status */
u8 bten;
u8 rsvd13[14];
-} __packed global_nvs_t;
-
-void acpi_create_gnvs(global_nvs_t *gnvs);
+};
#endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */
diff --git a/src/southbridge/intel/i82801jx/smihandler.c b/src/southbridge/intel/i82801jx/smihandler.c
index 00b3ffa..af242aa 100644
--- a/src/southbridge/intel/i82801jx/smihandler.c
+++ b/src/southbridge/intel/i82801jx/smihandler.c
@@ -18,7 +18,7 @@
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
* by coreboot.
*/
-global_nvs_t *gnvs = (global_nvs_t *)0x0;
+struct global_nvs *gnvs = (struct global_nvs *)0x0;
void *tcg = (void *)0x0;
void *smi1 = (void *)0x0;
@@ -41,7 +41,7 @@
void southbridge_update_gnvs(u8 apm_cnt, int *smm_done)
{
- gnvs = *(global_nvs_t **)0x500;
+ gnvs = *(struct global_nvs **)0x500;
tcg = *(void **)0x504;
smi1 = *(void **)0x508;
*smm_done = 1;
diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c
index 36d46f2..2c29046 100644
--- a/src/southbridge/intel/ibexpeak/lpc.c
+++ b/src/southbridge/intel/ibexpeak/lpc.c
@@ -13,6 +13,7 @@
#include <device/pci_ops.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <elog.h>
#include <acpi/acpigen.h>
#include <cbmem.h>
@@ -552,9 +553,9 @@
pch_enable(dev);
}
-static void southbridge_inject_dsdt(const struct device *dev)
+void southbridge_inject_dsdt(const struct device *dev)
{
- global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
+ struct global_nvs *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs) {
memset(gnvs, 0, sizeof(*gnvs));
diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h
index 6b82de3..834b3af 100644
--- a/src/southbridge/intel/ibexpeak/nvs.h
+++ b/src/southbridge/intel/ibexpeak/nvs.h
@@ -3,7 +3,7 @@
#include <commonlib/helpers.h>
#include "vendorcode/google/chromeos/gnvs.h"
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -99,10 +99,6 @@
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
-
-void acpi_create_gnvs(global_nvs_t *gnvs);
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c
index a881f33..2679351 100644
--- a/src/southbridge/intel/ibexpeak/smihandler.c
+++ b/src/southbridge/intel/ibexpeak/smihandler.c
@@ -26,8 +26,8 @@
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
* by coreboot.
*/
-static global_nvs_t *gnvs;
-global_nvs_t *smm_get_gnvs(void)
+static struct global_nvs *gnvs;
+struct global_nvs *smm_get_gnvs(void)
{
return gnvs;
}
@@ -160,7 +160,7 @@
smi_apmc_find_state_save(apm_cnt);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (global_nvs_t *)((u32)state->rbx);
+ gnvs = (struct global_nvs *)((u32)state->rbx);
*smm_done = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
diff --git a/src/southbridge/intel/lynxpoint/acpi.c b/src/southbridge/intel/lynxpoint/acpi.c
index c4ea418..cfdcee6 100644
--- a/src/southbridge/intel/lynxpoint/acpi.c
+++ b/src/southbridge/intel/lynxpoint/acpi.c
@@ -41,7 +41,7 @@
acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
}
-static void acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs)
+static void acpi_create_serialio_ssdt_entry(int id, struct global_nvs *gnvs)
{
char sio_name[5] = {};
snprintf(sio_name, sizeof(sio_name), "S%1uEN", id);
@@ -51,7 +51,7 @@
void acpi_create_serialio_ssdt(acpi_header_t *ssdt)
{
unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t);
- global_nvs_t *gnvs = acpi_get_gnvs();
+ struct global_nvs *gnvs = acpi_get_gnvs();
int id;
if (!gnvs)
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 78536f6..f486434 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -11,6 +11,7 @@
#include <arch/io.h>
#include <arch/ioapic.h>
#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
#include <cpu/x86/smm.h>
#include <cbmem.h>
#include <string.h>
@@ -669,7 +670,7 @@
static void pch_lpc_read_resources(struct device *dev)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
@@ -681,9 +682,9 @@
pch_lpc_add_io_resources(dev);
/* Allocate ACPI NVS in CBMEM */
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs));
if (!acpi_is_wakeup_s3() && gnvs)
- memset(gnvs, 0, sizeof(global_nvs_t));
+ memset(gnvs, 0, sizeof(struct global_nvs));
}
static void pch_lpc_enable(struct device *dev)
@@ -695,9 +696,9 @@
pch_enable(dev);
}
-static void southbridge_inject_dsdt(const struct device *dev)
+void southbridge_inject_dsdt(const struct device *dev)
{
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) {
diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h
index b5b6e9f..4abe026 100644
--- a/src/southbridge/intel/lynxpoint/nvs.h
+++ b/src/southbridge/intel/lynxpoint/nvs.h
@@ -4,7 +4,7 @@
#include <stdint.h>
#include "vendorcode/google/chromeos/gnvs.h"
-typedef struct global_nvs_t {
+struct __packed global_nvs {
/* Miscellaneous */
u16 osys; /* 0x00 - Operating System */
u8 smif; /* 0x02 - SMI function call ("TRAP") */
@@ -76,10 +76,6 @@
/* ChromeOS specific (starts at 0x100)*/
chromeos_acpi_t chromeos;
-} __packed global_nvs_t;
-check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+};
-/* Used in SMM to find the ACPI GNVS address */
-global_nvs_t *smm_get_gnvs(void);
-
-void acpi_create_gnvs(global_nvs_t * gnvs);
+check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c
index 3973a8d..77da535 100644
--- a/src/southbridge/intel/lynxpoint/serialio.c
+++ b/src/southbridge/intel/lynxpoint/serialio.c
@@ -205,7 +205,7 @@
}
if (config->sio_acpi_mode) {
- global_nvs_t *gnvs;
+ struct global_nvs *gnvs;
/* Find ACPI NVS to update BARs */
gnvs = acpi_get_gnvs();
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index be842c5..0bc1e2a 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -24,8 +24,8 @@
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
* by coreboot.
*/
-static global_nvs_t *gnvs;
-global_nvs_t *smm_get_gnvs(void)
+static struct global_nvs *gnvs;
+struct global_nvs *smm_get_gnvs(void)
{
return gnvs;
}
@@ -325,7 +325,7 @@
state = smi_apmc_find_state_save(reg8);
if (state) {
/* EBX in the state save contains the GNVS pointer */
- gnvs = (global_nvs_t *)((u32)state->rbx);
+ gnvs = (struct global_nvs *)((u32)state->rbx);
smm_initialized = 1;
printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
}
diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h
index 99b76e7..74324a0 100644
--- a/src/vendorcode/google/chromeos/gnvs.h
+++ b/src/vendorcode/google/chromeos/gnvs.h
@@ -10,10 +10,10 @@
/*
* chromeos_acpi_t portion of ACPI GNVS is assumed to live at
- * 0x100 - 0x1000. When defining global_nvs_t, use check_member
+ * 0x100 - 0x1000. When defining global_nvs, use check_member
* to ensure that it is properly aligned:
*
- * check_member(global_nvs_t, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
+ * check_member(global_nvs, chromeos, GNVS_CHROMEOS_ACPI_OFFSET);
*/
#define GNVS_CHROMEOS_ACPI_OFFSET 0x100
diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go
index 7bbb2d2..1440abc2 100644
--- a/util/autoport/bd82x6x.go
+++ b/util/autoport/bd82x6x.go
@@ -362,7 +362,7 @@
gnvs.WriteString(`#include <southbridge/intel/bd82x6x/nvs.h>
/* FIXME: check this function. */
-void acpi_create_gnvs(global_nvs_t *gnvs)
+void acpi_create_gnvs(struct global_nvs *gnvs)
{
/* Disable USB ports in S3 by default */
gnvs->s3u0 = 0;