wtm2: Convert to use soc/intel/broadwell
Convert wtm2 board to use the broadwell soc chipset.
BUG=chrome-os-partner:28234
TEST=Build and boot on wtm2 with haswell and broadwell
CQ-DEPEND=CL:201067
CQ-DEPEND=CL:*164226
Original-Change-Id: Ifb0db15cc23a3b66430b32b2ad3f8ab2fb03c4c3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201070
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit e1073c6e34ab2d436faf46dde5f6b3bf99692866)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I925b91a8de980b1768f03eaee915a7fd91fbdbda
Reviewed-on: http://review.coreboot.org/8001
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c
index 20814ab6..b6c0f9a 100644
--- a/src/mainboard/intel/wtm2/acpi_tables.c
+++ b/src/mainboard/intel/wtm2/acpi_tables.c
@@ -29,67 +29,26 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
-#include <cpu/x86/msr.h>
-#include <vendorcode/google/chromeos/gnvs.h>
-
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
+#include <broadwell/acpi.h>
+#include <broadwell/nvs.h>
#include "thermal.h"
-static void acpi_update_thermal_table(global_nvs_t *gnvs)
-{
- gnvs->f4of = FAN4_THRESHOLD_OFF;
- gnvs->f4on = FAN4_THRESHOLD_ON;
- gnvs->f4pw = FAN4_PWM;
-
- gnvs->f3of = FAN3_THRESHOLD_OFF;
- gnvs->f3on = FAN3_THRESHOLD_ON;
- gnvs->f3pw = FAN3_PWM;
-
- gnvs->f2of = FAN2_THRESHOLD_OFF;
- gnvs->f2on = FAN2_THRESHOLD_ON;
- gnvs->f2pw = FAN2_PWM;
-
- gnvs->f1of = FAN1_THRESHOLD_OFF;
- gnvs->f1on = FAN1_THRESHOLD_ON;
- gnvs->f1pw = FAN1_PWM;
-
- gnvs->f0of = FAN0_THRESHOLD_OFF;
- gnvs->f0on = FAN0_THRESHOLD_ON;
- gnvs->f0pw = FAN0_PWM;
-
- gnvs->tcrt = CRITICAL_TEMPERATURE;
- gnvs->tpsv = PASSIVE_TEMPERATURE;
- gnvs->tmax = MAX_TEMPERATURE;
-}
-
void acpi_create_gnvs(global_nvs_t *gnvs)
{
+ acpi_init_gnvs(gnvs);
+
/* Enable USB ports in S3 */
gnvs->s3u0 = 1;
- gnvs->s3u1 = 1;
/* Disable USB ports in S5 */
gnvs->s5u0 = 0;
- gnvs->s5u1 = 0;
/* TPM Present */
gnvs->tpmp = 1;
- /* IGD Displays */
- gnvs->ndid = 3;
- gnvs->did[0] = 0x80000100;
- gnvs->did[1] = 0x80000240;
- gnvs->did[2] = 0x80000410;
- gnvs->did[3] = 0x80000410;
- gnvs->did[4] = 0x00000005;
-
-#if CONFIG_CHROMEOS
- /* Emerald Lake has no EC (?) */
- gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
-#endif
-
- acpi_update_thermal_table(gnvs);
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+ gnvs->tmax = MAX_TEMPERATURE;
}
unsigned long acpi_fill_madt(unsigned long current)
@@ -101,23 +60,5 @@
current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
2, IO_APIC_ADDR, 0);
- /* INT_SRC_OVR */
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 0);
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
- current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
- return current;
-}
-
-unsigned long acpi_fill_slit(unsigned long current)
-{
- // Not implemented
- return current;
-}
-
-unsigned long acpi_fill_srat(unsigned long current)
-{
- /* No NUMA, no SRAT */
- return current;
+ return acpi_madt_irq_overrides(current);
}