diff --git a/src/mainboard/google/falco/acpi/haswell_pci_irqs.asl b/src/mainboard/google/falco/acpi/haswell_pci_irqs.asl
index 82a2eba..aa4a862 100644
--- a/src/mainboard/google/falco/acpi/haswell_pci_irqs.asl
+++ b/src/mainboard/google/falco/acpi/haswell_pci_irqs.asl
@@ -26,6 +26,8 @@
 		Return (Package() {
 			// Onboard graphics (IGD)	0:2.0
 			Package() { 0x0002ffff, 0, 0, 16 },
+			// Mini-HD Audio		0:3.0
+			Package() { 0x0003ffff, 0, 0, 16 },
 			// High Definition Audio	0:1b.0
 			Package() { 0x001bffff, 0, 0, 22 },
 			// PCIe Root Ports		0:1c.x
@@ -54,6 +56,8 @@
 		Return (Package() {
 			// Onboard graphics (IGD)	0:2.0
 			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// Mini-HD Audio		0:3.0
+			Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
 			// High Definition Audio	0:1b.0
 			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
 			// PCIe Root Ports		0:1c.x
diff --git a/src/mainboard/google/falco/devicetree.cb b/src/mainboard/google/falco/devicetree.cb
index 21858e7..cdd5a2e 100644
--- a/src/mainboard/google/falco/devicetree.cb
+++ b/src/mainboard/google/falco/devicetree.cb
@@ -42,6 +42,7 @@
 	device domain 0 on
 		device pci 00.0 on end # host bridge
 		device pci 02.0 on end # vga controller
+		device pci 03.0 on end # mini-hd audio
 
 		chip southbridge/intel/lynxpoint
 			register "pirqa_routing" = "0x8b"
diff --git a/src/mainboard/google/peppy/acpi/haswell_pci_irqs.asl b/src/mainboard/google/peppy/acpi/haswell_pci_irqs.asl
index 82a2eba..aa4a862 100644
--- a/src/mainboard/google/peppy/acpi/haswell_pci_irqs.asl
+++ b/src/mainboard/google/peppy/acpi/haswell_pci_irqs.asl
@@ -26,6 +26,8 @@
 		Return (Package() {
 			// Onboard graphics (IGD)	0:2.0
 			Package() { 0x0002ffff, 0, 0, 16 },
+			// Mini-HD Audio		0:3.0
+			Package() { 0x0003ffff, 0, 0, 16 },
 			// High Definition Audio	0:1b.0
 			Package() { 0x001bffff, 0, 0, 22 },
 			// PCIe Root Ports		0:1c.x
@@ -54,6 +56,8 @@
 		Return (Package() {
 			// Onboard graphics (IGD)	0:2.0
 			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// Mini-HD Audio		0:3.0
+			Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
 			// High Definition Audio	0:1b.0
 			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
 			// PCIe Root Ports		0:1c.x
diff --git a/src/mainboard/google/peppy/devicetree.cb b/src/mainboard/google/peppy/devicetree.cb
index b9bc47f..909a347 100644
--- a/src/mainboard/google/peppy/devicetree.cb
+++ b/src/mainboard/google/peppy/devicetree.cb
@@ -42,6 +42,7 @@
 	device domain 0 on
 		device pci 00.0 on end # host bridge
 		device pci 02.0 on end # vga controller
+		device pci 03.0 on end # mini-hd audio
 
 		chip southbridge/intel/lynxpoint
 			register "pirqa_routing" = "0x8b"
diff --git a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl b/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl
index 82a2eba..aa4a862 100644
--- a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl
+++ b/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl
@@ -26,6 +26,8 @@
 		Return (Package() {
 			// Onboard graphics (IGD)	0:2.0
 			Package() { 0x0002ffff, 0, 0, 16 },
+			// Mini-HD Audio		0:3.0
+			Package() { 0x0003ffff, 0, 0, 16 },
 			// High Definition Audio	0:1b.0
 			Package() { 0x001bffff, 0, 0, 22 },
 			// PCIe Root Ports		0:1c.x
@@ -54,6 +56,8 @@
 		Return (Package() {
 			// Onboard graphics (IGD)	0:2.0
 			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// Mini-HD Audio		0:3.0
+			Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
 			// High Definition Audio	0:1b.0
 			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
 			// PCIe Root Ports		0:1c.x
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb
index b9bc47f..909a347 100644
--- a/src/mainboard/google/slippy/devicetree.cb
+++ b/src/mainboard/google/slippy/devicetree.cb
@@ -42,6 +42,7 @@
 	device domain 0 on
 		device pci 00.0 on end # host bridge
 		device pci 02.0 on end # vga controller
+		device pci 03.0 on end # mini-hd audio
 
 		chip southbridge/intel/lynxpoint
 			register "pirqa_routing" = "0x8b"
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index b2ac85e..04b0d2f 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -22,6 +22,7 @@
 
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
 ramstage-y += mrccache.c
+ramstage-y += minihd.c
 
 romstage-y += raminit.c
 romstage-y += mrccache.c
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 5b36418..7f9f187 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -103,8 +103,9 @@
 	/* Setup all BARs required for early PCIe and raminit */
 	haswell_setup_bars();
 
-	/* Device Enable */
-	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, DEVEN_HOST | DEVEN_IGD);
+	/* Device Enable: IGD and Mini-HD Audio */
+	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN,
+			   DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
 
 	haswell_setup_graphics();
 }
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index c9e10ed..bcd22d1 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -50,12 +50,14 @@
 #define GGC		0x50			/* GMCH Graphics Control */
 
 #define DEVEN		0x54			/* Device Enable */
-#define  DEVEN_PEG60	(1 << 13)
-#define  DEVEN_IGD	(1 << 4)
-#define  DEVEN_PEG10	(1 << 3)
-#define  DEVEN_PEG11	(1 << 2)
-#define  DEVEN_PEG12	(1 << 1)
-#define  DEVEN_HOST	(1 << 0)
+#define  DEVEN_D7EN	(1 << 14)
+#define  DEVEN_D4EN	(1 << 7)
+#define  DEVEN_D3EN	(1 << 5)
+#define  DEVEN_D2EN	(1 << 4)
+#define  DEVEN_D1F0EN	(1 << 3)
+#define  DEVEN_D1F1EN	(1 << 2)
+#define  DEVEN_D1F2EN	(1 << 1)
+#define  DEVEN_D0EN	(1 << 0)
 
 #define PAM0		0x80
 #define PAM1		0x81
diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c
new file mode 100644
index 0000000..cef6126
--- /dev/null
+++ b/src/northbridge/intel/haswell/minihd.c
@@ -0,0 +1,140 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <delay.h>
+#include <stdlib.h>
+#include <southbridge/intel/lynxpoint/hda_verb.h>
+
+static const u32 minihd_verb_table[] = {
+	/* coreboot specific header */
+	0x80862807,	// Codec Vendor / Device ID: Intel Haswell Mini-HD
+	0x00000000,	// Subsystem ID
+	0x00000004,	// Number of jacks
+
+	/* Enable 3rd Pin and Converter Widget */
+	0x00878101,
+
+	/* Pin Widget 5 - PORT B */
+	0x00571C10,
+	0x00571D00,
+	0x00571E56,
+	0x00571F18,
+
+	/* Pin Widget 6 - PORT C */
+	0x00671C20,
+	0x00671D00,
+	0x00671E56,
+	0x00671F18,
+
+	/* Pin Widget 7 - PORT D */
+	0x00771C30,
+	0x00771D00,
+	0x00771E56,
+	0x00771F18,
+
+	/* Disable 3rd Pin and Converter Widget */
+	0x00878100,
+
+	/* Dummy entries to fill out the table */
+	0x00878100,
+	0x00878100,
+};
+
+static void minihd_init(struct device *dev)
+{
+	struct resource *res;
+	u32 base, reg32;
+	int codec_mask, i;
+
+	/* Find base address */
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	if (!res)
+		return;
+
+	base = (u32)res->base;
+	printk(BIOS_DEBUG, "Mini-HD: base = %08x\n", (u32)base);
+
+	/* Set Bus Master */
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+
+	/* Mini-HD configuration */
+	reg32 = read32(base + 0x100c);
+	reg32 &= 0xfffc0000;
+	reg32 |= 0x4;
+	write32(base + 0x100c, reg32);
+
+	reg32 = read32(base + 0x1010);
+	reg32 &= 0xfffc0000;
+	reg32 |= 0x4b;
+	write32(base + 0x1010, reg32);
+
+	/* Init the codec and write the verb table */
+	codec_mask = hda_codec_detect(base);
+
+	if (codec_mask) {
+		for (i = 3; i >= 0; i--) {
+			if (codec_mask & (1 << i))
+				hda_codec_init(base, i,
+					       sizeof(minihd_verb_table),
+					       minihd_verb_table);
+		}
+	}
+}
+
+static void minihd_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations minihd_pci_ops = {
+	.set_subsystem    = minihd_set_subsystem,
+};
+
+static struct device_operations minihd_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= minihd_init,
+	.scan_bus		= 0,
+	.ops_pci		= &minihd_pci_ops,
+};
+
+static const unsigned short pci_device_ids[] = { 0x0a0c, 0 };
+
+static const struct pci_driver haswell_minihd __pci_driver = {
+	.ops	 = &minihd_ops,
+	.vendor	 = PCI_VENDOR_ID_INTEL,
+	.devices = pci_device_ids,
+};
+
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 90419d6..92e1c00 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -33,6 +33,7 @@
 ramstage-y += usb_xhci.c
 ramstage-y += me_9.x.c
 ramstage-y += smbus.c
+ramstage-y += hda_verb.c
 ramstage-$(CONFIG_INTEL_LYNXPOINT_LP) += serialio.c
 
 ramstage-y += rcba.c
diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c
index ee12042..b63672d 100644
--- a/src/southbridge/intel/lynxpoint/azalia.c
+++ b/src/southbridge/intel/lynxpoint/azalia.c
@@ -27,240 +27,47 @@
 #include <arch/io.h>
 #include <delay.h>
 #include "pch.h"
-
-#define HDA_ICII_REG 0x68
-#define HDA_ICII_BUSY (1 << 0)
-#define HDA_ICII_VALID (1 << 1)
-
-typedef struct southbridge_intel_bd82x6x_config config_t;
-
-static int set_bits(u32 port, u32 mask, u32 val)
-{
-	u32 reg32;
-	int count;
-
-	/* Write (val & mask) to port */
-	val &= mask;
-	reg32 = read32(port);
-	reg32 &= ~mask;
-	reg32 |= val;
-	write32(port, reg32);
-
-	/* Wait for readback of register to
-	 * match what was just written to it
-	 */
-	count = 50;
-	do {
-		/* Wait 1ms based on BKDG wait time */
-		mdelay(1);
-		reg32 = read32(port);
-		reg32 &= mask;
-	} while ((reg32 != val) && --count);
-
-	/* Timeout occurred */
-	if (!count)
-		return -1;
-	return 0;
-}
-
-static int codec_detect(u32 base)
-{
-	u8 reg8;
-
-	/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
-	if (set_bits(base + 0x08, 1, 1) == -1)
-		goto no_codec;
-
-	/* Write back the value once reset bit is set. */
-	write16(base + 0x0, read16(base + 0x0));
-
-	/* Read in Codec location (BAR + 0xe)[2..0]*/
-	reg8 = read8(base + 0xe);
-	reg8 &= 0x0f;
-	if (!reg8)
-		goto no_codec;
-
-	return reg8;
-
-no_codec:
-	/* Codec Not found */
-	/* Put HDA back in reset (BAR + 0x8) [0] */
-	set_bits(base + 0x08, 1, 0);
-	printk(BIOS_DEBUG, "Azalia: No codec!\n");
-	return 0;
-}
+#include "hda_verb.h"
 
 const u32 * cim_verb_data = NULL;
 u32 cim_verb_data_size = 0;
 const u32 * pc_beep_verbs = NULL;
 u32 pc_beep_verbs_size = 0;
 
-static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
-{
-	int idx=0;
-
-	while (idx < (cim_verb_data_size / sizeof(u32))) {
-		u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
-		if (cim_verb_data[idx] != viddid) {
-			idx += verb_size + 3; // skip verb + header
-			continue;
-		}
-		*verb = &cim_verb_data[idx+3];
-		return verb_size;
-	}
-
-	/* Not all codecs need to load another verb */
-	return 0;
-}
-
-/**
- *  Wait 50usec for the codec to indicate it is ready
- *  no response would imply that the codec is non-operative
- */
-
-static int wait_for_ready(u32 base)
-{
-	/* Use a 50 usec timeout - the Linux kernel uses the
-	 * same duration */
-
-	int timeout = 50;
-
-	while(timeout--) {
-		u32 reg32 = read32(base +  HDA_ICII_REG);
-		if (!(reg32 & HDA_ICII_BUSY))
-			return 0;
-		udelay(1);
-	}
-
-	return -1;
-}
-
-/**
- *  Wait 50usec for the codec to indicate that it accepted
- *  the previous command.  No response would imply that the code
- *  is non-operative
- */
-
-static int wait_for_valid(u32 base)
-{
-	u32 reg32;
-
-	/* Send the verb to the codec */
-	reg32 = read32(base + HDA_ICII_REG);
-	reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
-	write32(base + HDA_ICII_REG, reg32);
-
-	/* Use a 50 usec timeout - the Linux kernel uses the
-	 * same duration */
-
-	int timeout = 50;
-	while(timeout--) {
-		reg32 = read32(base + HDA_ICII_REG);
-		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
-			HDA_ICII_VALID)
-			return 0;
-		udelay(1);
-	}
-
-	return -1;
-}
-
-static void codec_init(struct device *dev, u32 base, int addr)
-{
-	u32 reg32;
-	const u32 *verb;
-	u32 verb_size;
-	int i;
-
-	printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr);
-
-	/* 1 */
-	if (wait_for_ready(base) == -1) {
-		printk(BIOS_DEBUG, "  codec not ready.\n");
-		return;
-	}
-
-	reg32 = (addr << 28) | 0x000f0000;
-	write32(base + 0x60, reg32);
-
-	if (wait_for_valid(base) == -1) {
-		printk(BIOS_DEBUG, "  codec not valid.\n");
-		return;
-	}
-
-	reg32 = read32(base + 0x64);
-
-	/* 2 */
-	printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
-	verb_size = find_verb(dev, reg32, &verb);
-
-	if (!verb_size) {
-		printk(BIOS_DEBUG, "Azalia: No verb!\n");
-		return;
-	}
-	printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size);
-
-	/* 3 */
-	for (i = 0; i < verb_size; i++) {
-		if (wait_for_ready(base) == -1)
-			return;
-
-		write32(base + 0x60, verb[i]);
-
-		if (wait_for_valid(base) == -1)
-			return;
-	}
-	printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
-}
-
-static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+static void codecs_init(u32 base, u32 codec_mask)
 {
 	int i;
+
+	/* Can support up to 4 codecs */
 	for (i = 3; i >= 0; i--) {
 		if (codec_mask & (1 << i))
-			codec_init(dev, base, i);
+			hda_codec_init(base, i,
+				       cim_verb_data_size,
+				       cim_verb_data);
 	}
 
-	for (i = 0; i < pc_beep_verbs_size; i++) {
-		if (wait_for_ready(base) == -1)
-			return;
-
-		write32(base + 0x60, pc_beep_verbs[i]);
-
-		if (wait_for_valid(base) == -1)
-			return;
-	}
+	if (pc_beep_verbs_size && pc_beep_verbs)
+		hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs);
 }
 
-static void azalia_init(struct device *dev)
+static void azalia_pch_init(struct device *dev, u32 base)
 {
-	u32 base;
-	struct resource *res;
-	u32 codec_mask;
 	u8 reg8;
 	u16 reg16;
 	u32 reg32;
 
-	/* Find base address */
-	res = find_resource(dev, PCI_BASE_ADDRESS_0);
-	if (!res)
-		return;
-
-	// NOTE this will break as soon as the Azalia get's a bar above
-	// 4G. Is there anything we can do about it?
-	base = (u32)res->base;
-	printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
-
 	if (RCBA32(0x2030) & (1 << 31)) {
 		reg32 = pci_read_config32(dev, 0x120);
 		reg32 &= 0xf8ffff01;
-		reg32 |= (1 << 24); // 25 for server
+		reg32 |= (1 << 25);
 		reg32 |= RCBA32(0x2030) & 0xfe;
 		pci_write_config32(dev, 0x120, reg32);
 
-		reg16 = pci_read_config16(dev, 0x78);
-		reg16 &= ~(1 << 11);
-		pci_write_config16(dev, 0x78, reg16);
+		if (!pch_is_lp()) {
+			reg16 = pci_read_config16(dev, 0x78);
+			reg16 &= ~(1 << 11);
+			pci_write_config16(dev, 0x78, reg16);
+		}
 	} else
 		printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n");
 
@@ -272,73 +79,87 @@
 	if (pci_read_config32(dev, 0x120) & ((1 << 24) |
 						(1 << 25) | (1 << 26))) {
 		reg32 = pci_read_config32(dev, 0x120);
-		reg32 |= (1 << 31);
+		if (pch_is_lp())
+			reg32 &= ~(1 << 31);
+		else
+			reg32 |= (1 << 31);
 		pci_write_config32(dev, 0x120, reg32);
 	}
 
-	// Enable HDMI codec:
-	reg32 = pci_read_config32(dev, 0xc4);
-	reg32 |= (1 << 1);
-	pci_write_config32(dev, 0xc4, reg32);
-
 	reg8 = pci_read_config8(dev, 0x43);
-	reg8 |= (1 << 5) | (1 << 6) | (1 << 2) | (1 << 1) | (1 << 0);
+	if (pch_is_lp())
+		reg8 &= ~(1 << 6);
+	else
+		reg8 |= (1 << 4);
 	pci_write_config8(dev, 0x43, reg8);
 
-	/* Additional programming steps */
-	reg32 = pci_read_config32(dev, 0xc4);
-	reg32 |= (1 << 13) | (1 << 10);
-	pci_write_config32(dev, 0xc4, reg32);
-
-	reg32 = pci_read_config32(dev, 0xd0);
-	reg32 &= ~(1 << 31);
-	pci_write_config32(dev, 0xd0, reg32);
+	if (!pch_is_lp()) {
+		reg32 = pci_read_config32(dev, 0xc0);
+		reg32 |= (1 << 17);
+		pci_write_config32(dev, 0xc0, reg32);
+	}
 
 	/* Additional programming steps */
 	reg32 = pci_read_config32(dev, 0xc4);
-	reg32 |= (1 << 13);
+	if (pch_is_lp())
+		reg32 |= (1 << 24);
+	else
+		reg32 |= (1 << 14);
 	pci_write_config32(dev, 0xc4, reg32);
 
-	reg32 = pci_read_config32(dev, 0xc4);
-	reg32 |= (1 << 10);
-	pci_write_config32(dev, 0xc4, reg32);
+	if (!pch_is_lp()) {
+		reg32 = pci_read_config32(dev, 0xd0);
+		reg32 &= ~(1 << 31);
+		pci_write_config32(dev, 0xd0, reg32);
+	}
 
-	reg32 = pci_read_config32(dev, 0xd0);
-	reg32 &= ~(1 << 31);
-	pci_write_config32(dev, 0xd0, reg32);
-
-	/* Set Bus Master */
-	reg32 = pci_read_config32(dev, PCI_COMMAND);
-	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
-
-	pci_write_config8(dev, 0x3c, 0x0a); // unused?
-
-	/* Codec Initialization Programming Sequence */
-	reg32 = read32(base + 0x08);
-	reg32 |= (1 << 0);
-	write32(base + 0x08, reg32);
-
-	//
 	reg8 = pci_read_config8(dev, 0x40); // Audio Control
-	reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
+	reg8 |= 1; // Select Azalia mode
 	pci_write_config8(dev, 0x40, reg8);
 
 	reg8 = pci_read_config8(dev, 0x4d); // Docking Status
 	reg8 &= ~(1 << 7); // Docking not supported
 	pci_write_config8(dev, 0x4d, reg8);
 
-	codec_mask = codec_detect(base);
+	if (pch_is_lp()) {
+		reg16 = read32(base + 0x0012);
+		reg16 |= (1 << 0);
+		write32(base + 0x0012, reg16);
+
+		/* disable Auto Voltage Detector */
+		reg8 = pci_read_config8(dev, 0x42);
+		reg8 |= (1 << 2);
+		pci_write_config8(dev, 0x42, reg8);
+	}
+}
+
+static void azalia_init(struct device *dev)
+{
+	u32 base;
+	struct resource *res;
+	u32 codec_mask;
+	u32 reg32;
+
+	/* Find base address */
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	if (!res)
+		return;
+
+	base = (u32)res->base;
+	printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+
+	/* Set Bus Master */
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+
+	azalia_pch_init(dev, base);
+
+	codec_mask = hda_codec_detect(base);
 
 	if (codec_mask) {
 		printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
-		codecs_init(dev, base, codec_mask);
+		codecs_init(base, codec_mask);
 	}
-
-	/* Enable dynamic clock gating */
-	reg8 = pci_read_config8(dev, 0x43);
-	reg8 &= ~0x7;
-	reg8 |= (1 << 2) | (1 << 0);
-	pci_write_config8(dev, 0x43, reg8);
 }
 
 static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c
new file mode 100644
index 0000000..234a1ab
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/hda_verb.c
@@ -0,0 +1,254 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "pch.h"
+#include "hda_verb.h"
+
+/**
+ * Set bits in a register and wait for status
+ */
+static int set_bits(u32 port, u32 mask, u32 val)
+{
+	u32 reg32;
+	int count;
+
+	/* Write (val & mask) to port */
+	val &= mask;
+	reg32 = read32(port);
+	reg32 &= ~mask;
+	reg32 |= val;
+	write32(port, reg32);
+
+	/* Wait for readback of register to
+	 * match what was just written to it
+	 */
+	count = 50;
+	do {
+		/* Wait 1ms based on BKDG wait time */
+		mdelay(1);
+		reg32 = read32(port);
+		reg32 &= mask;
+	} while ((reg32 != val) && --count);
+
+	/* Timeout occurred */
+	if (!count)
+		return -1;
+	return 0;
+}
+
+/**
+ * Probe for supported codecs
+ */
+int hda_codec_detect(u32 base)
+{
+	u8 reg8;
+
+	/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
+	if (set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, HDA_GCTL_CRST) < 0)
+		goto no_codec;
+
+	/* Write back the value once reset bit is set. */
+	write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
+
+	/* Read in Codec location (BAR + 0xe)[2..0]*/
+	reg8 = read8(base + HDA_STATESTS_REG);
+	reg8 &= 0x0f;
+	if (!reg8)
+		goto no_codec;
+
+	return reg8;
+
+no_codec:
+	/* Codec Not found */
+	/* Put HDA back in reset (BAR + 0x8) [0] */
+	set_bits(base + HDA_GCTL_REG, HDA_GCTL_CRST, 0);
+	printk(BIOS_DEBUG, "HDA: No codec!\n");
+	return 0;
+}
+
+/**
+ * Wait 50usec for the codec to indicate it is ready
+ * no response would imply that the codec is non-operative
+ */
+static int hda_wait_for_ready(u32 base)
+{
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+
+	while(timeout--) {
+		u32 reg32 = read32(base +  HDA_ICII_REG);
+		if (!(reg32 & HDA_ICII_BUSY))
+			return 0;
+		udelay(1);
+	}
+
+	return -1;
+}
+
+/**
+ * Wait 50usec for the codec to indicate that it accepted
+ * the previous command.  No response would imply that the code
+ * is non-operative
+ */
+static int hda_wait_for_valid(u32 base)
+{
+	u32 reg32;
+
+	/* Send the verb to the codec */
+	reg32 = read32(base + HDA_ICII_REG);
+	reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
+	write32(base + HDA_ICII_REG, reg32);
+
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+	while(timeout--) {
+		reg32 = read32(base + HDA_ICII_REG);
+		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
+			HDA_ICII_VALID)
+			return 0;
+		udelay(1);
+	}
+
+	return -1;
+}
+
+/**
+ * Find a specific entry within a verb table
+ *
+ * @verb_table_bytes:	verb table size in bytes
+ * @verb_table_data:	verb table data
+ * @viddid:		vendor/device to search for
+ * @verb_out:		pointer to entry within table
+ *
+ * Returns size of the entry within the verb table,
+ * Returns 0 if the entry is not found
+ *
+ * The HDA verb table is composed of dwords. A set of 4 dwords is
+ * grouped together to form a "jack" descriptor.
+ *   Bits 31:28 - Codec Address
+ *   Bits 27:20 - NID
+ *   Bits 19:8  - Verb ID
+ *   Bits 7:0   - Payload
+ *
+ * coreboot groups different codec verb tables into a single table
+ * and prefixes each with a specific header consisting of 3
+ * dword entries:
+ *   1 - Codec Vendor/Device ID
+ *   2 - Subsystem ID
+ *   3 - Number of jacks (groups of 4 dwords) for this codec
+ */
+static u32 hda_find_verb(u32 verb_table_bytes,
+			 const u32 *verb_table_data,
+			 u32 viddid, const u32 ** verb)
+{
+	int idx=0;
+
+	while (idx < (verb_table_bytes / sizeof(u32))) {
+		u32 verb_size = 4 * verb_table_data[idx+2]; // in u32
+		if (verb_table_data[idx] != viddid) {
+			idx += verb_size + 3; // skip verb + header
+			continue;
+		}
+		*verb = &verb_table_data[idx+3];
+		return verb_size;
+	}
+
+	/* Not all codecs need to load another verb */
+	return 0;
+}
+
+/**
+ * Write a supplied verb table
+ */
+int hda_codec_write(u32 base, u32 size, const u32 *data)
+{
+	int i;
+
+	for (i = 0; i < size; i++) {
+		if (hda_wait_for_ready(base) < 0)
+			return -1;
+
+		write32(base + HDA_IC_REG, data[i]);
+
+		if (hda_wait_for_valid(base) < 0)
+			return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * Initialize codec, then find the verb table and write it
+ */
+int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data)
+{
+	const u32 *verb;
+	u32 reg32, size;
+	int rc;
+
+	printk(BIOS_DEBUG, "HDA: Initializing codec #%d\n", addr);
+
+	if (!verb_size || !verb_data) {
+		printk(BIOS_DEBUG, "HDA: No verb list!\n");
+		return -1;
+	}
+
+	/* 1 */
+	if (hda_wait_for_ready(base) < 0) {
+		printk(BIOS_DEBUG, "  codec not ready.\n");
+		return -1;
+	}
+
+	reg32 = (addr << 28) | 0x000f0000;
+	write32(base + HDA_IC_REG, reg32);
+
+	if (hda_wait_for_valid(base) < 0) {
+		printk(BIOS_DEBUG, "  codec not valid.\n");
+		return -1;
+	}
+
+	/* 2 */
+	reg32 = read32(base + HDA_IR_REG);
+	printk(BIOS_DEBUG, "HDA: codec viddid: %08x\n", reg32);
+
+	size = hda_find_verb(verb_size, verb_data, reg32, &verb);
+	if (!size) {
+		printk(BIOS_DEBUG, "HDA: No verb table entry found\n");
+		return -1;
+	}
+
+	/* 3 */
+	rc = hda_codec_write(base, size, verb);
+
+	if (rc < 0)
+		printk(BIOS_DEBUG, "HDA: verb not loaded\n");
+	else
+		printk(BIOS_DEBUG, "HDA: verb loaded.\n");
+
+	return rc;
+}
diff --git a/src/southbridge/intel/lynxpoint/hda_verb.h b/src/southbridge/intel/lynxpoint/hda_verb.h
new file mode 100644
index 0000000..8b3d27e
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/hda_verb.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef LYNXPOINT_HDA_VERB_H
+#define LYNXPOINT_HDA_VERB_H
+
+#define HDA_GCAP_REG		0x00
+#define HDA_GCTL_REG		0x08
+#define   HDA_GCTL_CRST		(1 << 0)
+#define HDA_STATESTS_REG	0x0e
+#define HDA_IC_REG		0x60
+#define HDA_IR_REG		0x64
+#define HDA_ICII_REG		0x68
+#define   HDA_ICII_BUSY		(1 << 0)
+#define   HDA_ICII_VALID	(1 << 1)
+
+int hda_codec_detect(u32 base);
+int hda_codec_write(u32 base, u32 size, const u32 *data);
+int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data);
+
+#endif