commit 0a760cd05b55755510a5672af3a1712a34a7e3aa
author Angel Pons <th3fanbus@gmail.com> Wed Jul 22 11:43:10 2020 +0200
committer Patrick Georgi <pgeorgi@google.com> Mon Aug 03 05:27:28 2020 +0000
tree fe4c1f04cf8e0044dcd10331f10ae83c8bf315b9
parent 0ddc2459bcbea812227b3b8b4fa5019e9a27da11

nb/intel/pineview/hostbridge_regs.h: Clean up registers

Sort them by ascending offsets.

Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.

Change-Id: I521aa3e49b17a9fb6b279ae758801356e510d054
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/northbridge/intel/pineview/hostbridge_regs.h

diff --git a/src/northbridge/intel/pineview/hostbridge_regs.h b/src/northbridge/intel/pineview/hostbridge_regs.h
index b320b9e..506efcf 100644
--- a/src/northbridge/intel/pineview/hostbridge_regs.h
+++ b/src/northbridge/intel/pineview/hostbridge_regs.h
@@ -5,9 +5,6 @@
 
 #define EPBAR		0x40
 #define MCHBAR		0x48
-#define PCIEXBAR	0x60
-#define DMIBAR		0x68
-#define PMIOBAR		0x78
 
 #define GGC		0x52	/* GMCH Graphics Control */
 
@@ -21,6 +18,10 @@
 #define BOARD_DEVEN (DEVEN_D0F0 | DEVEN_D2F0 | DEVEN_D2F1)
 #endif /* BOARD_DEVEN */
 
+#define PCIEXBAR	0x60
+#define DMIBAR		0x68
+#define PMIOBAR		0x78
+
 #define PAM0		0x90
 #define PAM1		0x91
 #define PAM2		0x92