diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index d277389..0245086 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4496,6 +4496,9 @@
 #define PCI_DID_INTEL_MTL_CRASHLOG_SRAM			0x7d0d
 #define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM		0xa77d
 
+/* Intel Trace Hub */
+#define PCI_DID_INTEL_MTL_TRACEHUB			0x7e24
+
 /* Intel Ethernet Controller device Ids */
 #define PCI_DID_INTEL_EHL_GBE_HOST		0x4B32
 #define PCI_DID_INTEL_EHL_GBE_PSE_0		0x4BA0
diff --git a/src/soc/intel/common/block/tracehub/Kconfig b/src/soc/intel/common/block/tracehub/Kconfig
new file mode 100644
index 0000000..76a0186
--- /dev/null
+++ b/src/soc/intel/common/block/tracehub/Kconfig
@@ -0,0 +1,9 @@
+config SOC_INTEL_COMMON_BLOCK_TRACEHUB
+	bool
+	default n
+	help
+	 Enable Intel Trace Hub (TH) driver. Intel FSP reserves some portion of
+	 memory for TH to store traces. This memory region information is
+	 passed via FSP HOB to coreboot. This driver locates the HOB and marks
+	 that memory region as reserved so that Operating System does not use
+	 this memory.
diff --git a/src/soc/intel/common/block/tracehub/Makefile.inc b/src/soc/intel/common/block/tracehub/Makefile.inc
new file mode 100644
index 0000000..aabed87
--- /dev/null
+++ b/src/soc/intel/common/block/tracehub/Makefile.inc
@@ -0,0 +1,2 @@
+## SPDX-License-Identifier: GPL-2.0-only
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TRACEHUB) += tracehub.c
diff --git a/src/soc/intel/common/block/tracehub/tracehub.c b/src/soc/intel/common/block/tracehub/tracehub.c
new file mode 100644
index 0000000..dd065d5
--- /dev/null
+++ b/src/soc/intel/common/block/tracehub/tracehub.c
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <fsp/util.h>
+
+static const uint8_t fsp_tracehub_guid[16] = {
+	0x09, 0x59, 0xb3, 0x5f, 0x1c, 0x5a, 0x31, 0x4a,
+	0xad, 0xaf, 0x57, 0x7b, 0x54, 0x68, 0x26, 0x3f,
+};
+
+static void tracehub_read_resources(struct device *dev)
+{
+	const struct hob_resource *tracehub_info_hob;
+
+	/* Read standard PCI resources. */
+	pci_dev_read_resources(dev);
+
+	/*
+	 * Find the Trace Hub HOB generated by Intel FSP. If the Trace Hub
+	 * is configured to save data in DRAM, FSP will generate this HOB.
+	 * This HOB contains address and length of the memory region used
+	 * by Trace Hub to save traces. Mark this memory region as reserved.
+	 */
+	tracehub_info_hob = fsp_find_resource_hob_by_guid(fsp_tracehub_guid);
+	if (!tracehub_info_hob) {
+		printk(BIOS_INFO, "Trace Hub HOB not found\n");
+		return;
+	}
+	printk(BIOS_DEBUG, "Trace Hub HOB found: addr=0x%08llx length=0x%08llx\n",
+			tracehub_info_hob->addr, tracehub_info_hob->length);
+	reserved_ram_resource_kb(dev, 0, tracehub_info_hob->addr / KiB,
+			tracehub_info_hob->length / KiB);
+}
+
+static struct device_operations dev_ops = {
+	.read_resources		= tracehub_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.ops_pci		= &pci_dev_ops_pci,
+};
+
+static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_TRACEHUB,
+	0
+};
+
+static const struct pci_driver tracehub_driver __pci_driver = {
+	.ops		= &dev_ops,
+	.vendor		= PCI_VID_INTEL,
+	.devices	= pci_device_ids,
+};