tree 30f980d1280790b74d31e571a534d96929857d1e
parent 193ee64d52a707809982231cd857329fe17f9f99
author Bernardo Perez Priego <bernardo.perez.priego@intel.com> 1621388359 -0700
committer Tim Wawrzynczak <twawrzynczak@chromium.org> 1624052555 +0000

soc/intel/alderlake: Add TBT PCIe root ports enablement

Ports are enabled according to devicetree.

BUG=none
TEST=Boot device, TBT should be functional

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I57e8eb13484014c17d24ad564643f0d03d11bc58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>