tree d11e8cab7262203fdd4c08f203fb50a9720aea0e
parent fda7d07b7bdb044b127ae0199af3e4c5c9401ad1
author Rizwan Qureshi <rizwan.qureshi@intel.com> 1667807710 +0530
committer Felix Held <felix-coreboot@felixheld.de> 1668691283 +0000

soc/intel/alderlake: Update ME HFSTS register definition

Update Alder Lake CSME HFSTS registers definitions as per Intel
doc #627331 revision 1.0.0, section 3.4.8.

Follow up CLs will use the bit definitions for performing
various checks.

TEST=build and boot nivviks platform

Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69286
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>