diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 613593e..4cd2133 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -92,15 +92,6 @@
 
 endif # HAVE_MRC
 
-config CAR_TILE_SIZE
-	hex
-	default 0x8000
-	help
-	 The tile size is the limit that can be assigned to cache-as-ram
-	 region as well as the amount of code cache used during cache-as-ram.
-	 Also note that (DCACHE_RAM_BASE ^ MRC_BIN_ADDRESS) & CAR_TILE_SIZE ==
-	 CAR_TILE_SIZE.
-
 # Cache As RAM region layout:
 #
 # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE
@@ -123,11 +114,11 @@
 
 config DCACHE_RAM_BASE
 	hex
-	default 0xff7f8000
+	default 0xff800000
 
 config DCACHE_RAM_SIZE
 	hex
-	default 0x1000
+	default 0x8000
 	help
 	  The size of the cache-as-ram region required during bootblock
 	  and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
@@ -135,7 +126,7 @@
 
 config DCACHE_RAM_MRC_VAR_SIZE
 	hex
-	default 0x7000
+	default 0x8000
 	help
 	  The amount of cache-as-ram region required by the reference code.