soc/intel/*: Use SSDT to pass A4GB and A4GS
GNVS is more fragile as you need to keep struct elements in sync with
ASL code.
Change-Id: I2cd5e6b56e4a0dbbb11f4a0ac97e8f84d53b90ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 0e60771..e0e6163 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -86,9 +86,6 @@
gnvs->scdp = gpio_get_pad_portid(cfg->sdcard_cd_gpio);
gnvs->scdo = gpio_acpi_pin(cfg->sdcard_cd_gpio);
}
-
- /* Fill in Above 4GB MMIO resource */
- sa_fill_gnvs(gnvs);
}
int soc_madt_sci_irq_polarity(int sci)
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index 41f2409..a56d2e1 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -23,6 +23,4 @@
SCDP, 8, // 0x29 - SD_CD GPIO portid
SCDO, 8, // 0x2A - GPIO pad offset relative to the community
UIOR, 8, // 0x2B - UART debug controller init on S3 resume
- A4GB, 64, // 0x2C - 0x33 Base of above 4GB MMIO Resource
- A4GS, 64, // 0x34 - 0x3B Length of above 4GB MMIO Resource
}
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl
index b05dc56..f8023be 100644
--- a/src/soc/intel/apollolake/acpi/northbridge.asl
+++ b/src/soc/intel/apollolake/acpi/northbridge.asl
@@ -22,6 +22,9 @@
}
}
+External (A4GS, IntObj)
+External (A4GB, IntObj)
+
/* Current Resource Settings */
Method (_CRS, 0, Serialized)
{
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index c98d1c4..0228cd2 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -22,6 +22,7 @@
#include <intelblocks/gpio.h>
#include <intelblocks/itss.h>
#include <intelblocks/pmclib.h>
+#include <intelblocks/systemagent.h>
#include <option.h>
#include <soc/cpu.h>
#include <soc/heci.h>
@@ -202,6 +203,7 @@
.set_resources = pci_domain_set_resources,
.scan_bus = pci_domain_scan_bus,
.acpi_name = &soc_acpi_name,
+ .acpi_fill_ssdt = ssdt_set_above_4g_pci,
};
static struct device_operations cpu_bus_ops = {
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index a9e0230..95d9ab4 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -28,8 +28,6 @@
uint8_t scdo; /* 0x2A - GPIO pad offset relative to the community */
uint8_t uior; /* 0x2B - UART debug controller init on S3
resume */
- uint64_t a4gb; /* 0x2C - 0x33 Base of above 4GB MMIO Resource */
- uint64_t a4gs; /* 0x34 - 0x3B Length of above 4GB MMIO Resource */
};
#endif /* _SOC_APOLLOLAKE_NVS_H_ */