intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOP
Change-Id: I02881ce465cb3835a6fa7c06b718aa42d0d327ec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15227
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index 36f5495..4b64210 100644
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -28,6 +28,7 @@
#include <superio/intel/i3100/i3100.h>
#include "lib/debug.c" // XXX
#include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
#include <spd.h>
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)
@@ -42,8 +43,7 @@
#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1)
-#include <cpu/intel/romstage.h>
-void main(unsigned long bist)
+void mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller mch[] = {
{