soc/intel/denverton_ns: Remove SOC specific FSP location overrides
1) FSP-S should not run XIP
2) Overriding the FSP-T location conflicts with the location set in
drivers/intel/fsp2_0
This fixes a regression caused by commit
0f068a600e (drivers/intel/fsp2_0: Fix the FSP-T position)
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/G6WRFITANOS2JEYG3GKB2ZNVCLUZ6W7P/
Change-Id: I381781c1de7c6dad32d66b295c927419dea7d8be
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig
index f6bafae..ee8e9eb 100644
--- a/src/soc/intel/denverton_ns/Kconfig
+++ b/src/soc/intel/denverton_ns/Kconfig
@@ -41,31 +41,12 @@
select CPU_INTEL_COMMON
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select SUPPORT_CPU_UCODE_IN_CBFS
+ select FSP_T_XIP if FSP_CAR
+ select FSP_M_XIP
config MMCONF_BASE_ADDRESS
default 0xe0000000
-config FSP_T_ADDR
- hex "Intel FSP-T (temp RAM init) binary location"
- depends on ADD_FSP_BINARIES && FSP_CAR
- default 0xfff30000
- help
- The memory location of the Intel FSP-T binary for this platform.
-
-config FSP_M_ADDR
- hex "Intel FSP-M (memory init) binary location"
- depends on ADD_FSP_BINARIES
- default 0xfff32000
- help
- The memory location of the Intel FSP-M binary for this platform.
-
-config FSP_S_ADDR
- hex "Intel FSP-S (silicon init) binary location"
- depends on ADD_FSP_BINARIES
- default 0xfffc3000
- help
- The memory location of the Intel FSP-S binary for this platform.
-
config FSP_HEADER_PATH
default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/"