google/poppy: Add new board
Add poppy board files using kabylake and FSP 2.0.
BUG=chrome-os-partner:60713
BRANCH=None
TEST=Compiles successfully
Change-Id: Ic9aa5093b319690ae893a21cab98d9b843000e6c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17866
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb
new file mode 100644
index 0000000..4283a34
--- /dev/null
+++ b/src/mainboard/google/poppy/devicetree.cb
@@ -0,0 +1,246 @@
+chip soc/intel/skylake
+
+ # Enable deep Sx states
+ register "deep_s3_enable" = "1"
+ register "deep_s5_enable" = "1"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
+ # FSP Configuration
+ register "ProbelessTrace" = "0"
+ register "EnableLan" = "0"
+ register "EnableSata" = "0"
+ register "SataSalpSupport" = "0"
+ register "SataMode" = "0"
+ register "SataPortsEnable[0]" = "0"
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "3"
+ register "EnableTraceHub" = "0"
+ register "XdciEnable" = "0"
+ register "SsicPortEnable" = "0"
+ register "SmbusEnable" = "1"
+ register "Cio2Enable" = "0"
+ register "ScsEmmcEnabled" = "1"
+ register "ScsEmmcHs400Enabled" = "1"
+ register "ScsSdCardEnabled" = "0"
+ register "IshEnable" = "0"
+ register "PttSwitch" = "0"
+ register "InternalGfx" = "1"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
+ register "FspSkipMpInit" = "1"
+ register "SaGv" = "3"
+ register "SerialIrqConfigSirqEnable" = "1"
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "1" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+ register "PmTimerDisabled" = "1"
+ register "SendVrMbxCmd" = "1" # IMVP8 workaround
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # VR Settings Configuration for 5 Domains
+ #+----------------+-------+-------+-------------+-------------+-------+
+ #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
+ #+----------------+-------+-------+-------------+-------------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-------+-------+-------------+-------------+-------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(4),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(7),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(34),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_RING]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(34),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1,
+ .psi1threshold = VR_CFG_AMP(20),
+ .psi2threshold = VR_CFG_AMP(5),
+ .psi3threshold = VR_CFG_AMP(1),
+ .psi3enable = 1,
+ .psi4enable = 1,
+ .imon_slope = 0x0,
+ .imon_offset = 0x0,
+ .icc_max = VR_CFG_AMP(35),
+ .voltage_limit = 1520,
+ }"
+
+ # Enable Root port 1.
+ register "PcieRpEnable[0]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[0]" = "1"
+ # RP 1 uses SRCCLKREQ1#
+ register "PcieRpClkReqNumber[0]" = "1"
+
+ register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
+ register "usb2_ports[4]" = "USB2_PORT_LONG(OC1)" # Type-C Port 2
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-C Port 1
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-C Port 2
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port
+ register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
+
+ register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" # Touchscreen
+ register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" # NFC
+ register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" # Camera
+ register "i2c_voltage[3]" = "I2C_VOLTAGE_1V8" # Pen
+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # Camera
+ register "i2c_voltage[5]" = "I2C_VOLTAGE_1V8" # Audio
+
+ # Must leave UART0 enabled or SD/eMMC will not work as PCI
+ register "SerialIoDevMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoPci,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ [PchSerialIoIndexSpi0] = PchSerialIoPci,
+ [PchSerialIoIndexSpi1] = PchSerialIoPci,
+ [PchSerialIoIndexUart0] = PchSerialIoPci,
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit,
+ }"
+
+ register "speed_shift_enable" = "1"
+ register "tdp_pl2_override" = "7"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 15.0 on end # I2C #0
+ device pci 15.1 on end # I2C #1
+ device pci 15.2 on end # I2C #2
+ device pci 15.3 on end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 off end # SATA
+ device pci 19.0 on end # UART #2
+ device pci 19.1 on end # I2C #5
+ device pci 19.2 on end # I2C #4
+ device pci 1c.0 on
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_PCI_EXP"
+ device pci 00.0 on end
+ end
+ end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 off end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1e.0 on end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 on end # GSPI #0
+ device pci 1e.3 on end # GSPI #1
+ device pci 1e.4 on end # eMMC
+ device pci 1e.5 off end # SDIO
+ device pci 1e.6 off end # SDCard
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # LPC Interface
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end