commit 0679392177b25a418f8d601b049f841c9d79ba55
author Chris Wang <chris.wang@amd.corp-partner.google.com> Thu Apr 29 00:11:01 2021 +0800
committer Felix Held <felix-coreboot@felixheld.de> Fri Apr 30 16:19:05 2021 +0000
tree f7b534dbbef134c617f68284474c677a6653746f
parent ca084b8db29ebf0eed63e5204213a15a6c8b3f53

amd/cezanne: Add telemetry setting to UPD

Add telemetry setting to UPD, the value comes from the SDLE testing.

BUG=b:182754399
TEST=Build & Boot guybrush

Cq-Depend: chrome-internal:3787638
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I9dd3643e9c582a41192130901935eef321b2c67e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52733
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/cezanne/chip.h

diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h
index 6b6a28f..244f2ba3 100644
--- a/src/soc/amd/cezanne/chip.h
+++ b/src/soc/amd/cezanne/chip.h
@@ -68,6 +68,13 @@
 	uint8_t cppc_epp_max_range;
 	uint8_t cppc_epp_min_range;
 	uint8_t cppc_preferred_cores;
+
+	/* telemetry settings */
+	uint32_t telemetry_vddcrvddfull_scale_current_mA;
+	uint32_t telemetry_vddcrvddoffset;
+	uint32_t telemetry_vddcrsocfull_scale_current_mA;
+	uint32_t telemetry_vddcrsocoffset;
+
 };
 
 #endif /* CEZANNE_CHIP_H */

src/soc/amd/cezanne/fsp_m_params.c

diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
index 2528086..8da38ff 100644
--- a/src/soc/amd/cezanne/fsp_m_params.c
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -118,5 +118,15 @@
 	/* S0i3 enable */
 	mcfg->s0i3_enable = config->s0ix_enable;
 
+	/* voltage regulator telemetry settings */
+	mcfg->telemetry_vddcrvddfull_scale_current =
+		config->telemetry_vddcrvddfull_scale_current_mA;
+	mcfg->telemetry_vddcrvddoffset =
+		config->telemetry_vddcrvddoffset;
+	mcfg->telemetry_vddcrsocfull_scale_current =
+		config->telemetry_vddcrsocfull_scale_current_mA;
+	mcfg->telemetry_vddcrsocOffset =
+		config->telemetry_vddcrsocoffset;
+
 	fsp_fill_pcie_ddi_descriptors(mcfg);
 }

src/vendorcode/amd/fsp/cezanne/FspmUpd.h

diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
index 6e9a1f0..f01af85 100644
--- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
+++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
@@ -102,8 +102,12 @@
 	/** Offset 0x04A4**/	uint8_t                     fch_ioapic_id;
 	/** Offset 0x04A5**/	uint8_t                     sata_enable;
 	/** Offset 0x04A6**/	uint8_t                     fch_reserved[32];
-	/** Offset 0x04A7**/	uint8_t                     s0i3_enable;
-	/** Offset 0x04C6**/	uint8_t                     UnusedUpdSpace0[57];
+	/** Offset 0x04C6**/	uint8_t                     s0i3_enable;
+	/** Offset 0x04C7**/	uint32_t                    telemetry_vddcrvddfull_scale_current;
+	/** Offset 0x04CB**/	uint32_t                    telemetry_vddcrvddoffset;
+	/** Offset 0x04CF**/	uint32_t                    telemetry_vddcrsocfull_scale_current;
+	/** Offset 0x04D3**/	uint32_t                    telemetry_vddcrsocOffset;
+	/** Offset 0x04D7**/	uint8_t                     UnusedUpdSpace0[41];
 	/** Offset 0x0500**/	uint16_t                    UpdTerminator;
 } FSP_M_CONFIG;