mb/google/deltaur: Update onboard memory config
Update dq, dqs map based on deltan schematics.
Configure memory to read SPD.
BUG=b:151702387
Signed-off-by: Varun Joshi <varun.joshi@intel.corp-partner.google.com>
Change-Id: I29059f09dd08c81b5ca5fe1215f33871835703fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/mainboard/google/deltaur/Makefile.inc b/src/mainboard/google/deltaur/Makefile.inc
index a913c75..5d758aa 100644
--- a/src/mainboard/google/deltaur/Makefile.inc
+++ b/src/mainboard/google/deltaur/Makefile.inc
@@ -8,6 +8,7 @@
bootblock-$(CONFIG_CHROMEOS) += chromeos.c
bootblock-y += ec.c
+romstage-y += romstage.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-y += ec.c
diff --git a/src/mainboard/google/deltaur/romstage.c b/src/mainboard/google/deltaur/romstage.c
new file mode 100644
index 0000000..2d73629
--- /dev/null
+++ b/src/mainboard/google/deltaur/romstage.c
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+ variant_memory_init(mem_cfg);
+}
diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h
index e6092b6..e6b23e6 100644
--- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/gpio.h
@@ -27,6 +27,8 @@
#define GPIO_MEM_CONFIG_3 GPP_F14
#define GPIO_MEM_CONFIG_4 GPP_F15
+/* DQ Memory Interleaved */
+#define MEMORY_INTERLEAVED GPP_E3
const struct pad_config *override_gpio_table(size_t *num);
const struct pad_config *override_early_gpio_table(size_t *num);
diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h
index 1d8a934..a1f1b22 100644
--- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h
@@ -8,6 +8,7 @@
#define __BASEBOARD_VARIANTS_H__
#include <soc/gpio.h>
+#include <soc/meminit.h>
#include <stddef.h>
#include <vendorcode/google/chromeos/chromeos.h>
@@ -21,4 +22,7 @@
const struct cros_gpio *variant_cros_gpios(size_t *num);
+const struct lpddr4x_cfg *variant_memory_params(void);
+void variant_memory_init(FSP_M_CONFIG *mem_cfg);
+
#endif /* __BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/deltaur/variants/deltan/Makefile.inc b/src/mainboard/google/deltaur/variants/deltan/Makefile.inc
index ea0d5f0..bad6b24 100644
--- a/src/mainboard/google/deltaur/variants/deltan/Makefile.inc
+++ b/src/mainboard/google/deltaur/variants/deltan/Makefile.inc
@@ -7,3 +7,4 @@
bootblock-y += gpio.c
ramstage-y += gpio.c
+romstage-y += memory.c
diff --git a/src/mainboard/google/deltaur/variants/deltan/memory.c b/src/mainboard/google/deltaur/variants/deltan/memory.c
new file mode 100644
index 0000000..90fa642
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/deltan/memory.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_ddr4_cfg baseboard_memcfg = {
+ /* DQ byte map */
+ .dq_map = {
+ [0] = {
+ { 10, 15, 11, 14, 13, 8, 12, 9, }, /* Byte 0 */
+ { 3, 5, 1, 0, 4, 7, 2, 6, }, /* Byte 1 */
+ { 15, 8, 11, 13, 10, 12, 14, 9, }, /* Byte 2 */
+ { 1, 6, 2, 4, 7, 5, 3, 0, }, /* Byte 3 */
+ { 7, 2, 6, 3, 4, 0, 5, 1, }, /* Byte 4 */
+ { 14, 10, 15, 11, 9, 13, 8, 12, }, /* Byte 5 */
+ { 8, 10, 14, 12, 9, 13, 11, 15, }, /* Byte 6 */
+ { 2, 7, 4, 5, 1, 3, 0, 6 }, /* Byte 7 */
+ },
+
+ [1] = {
+ { 12, 14, 10, 11, 15, 13, 9, 8, }, /* Byte 0 */
+ { 0, 6, 2, 7, 3, 5, 1, 4, }, /* Byte 1 */
+ { 10, 9, 14, 12, 11, 8, 15, 13, }, /* Byte 2 */
+ { 7, 3, 1, 4, 6, 2, 0, 5, }, /* Byte 3 */
+ { 10, 9, 13, 12, 8, 14, 11, 15, }, /* Byte 4 */
+ { 5, 4, 0, 2, 7, 3, 6, 1, }, /* Byte 5 */
+ { 15, 9, 11, 13, 10, 14, 8, 12, }, /* Byte 6 */
+ { 7, 3, 0, 4, 2, 5, 1, 6 }, /* Byte 7 */
+ },
+ },
+
+ /* DQS CPU<>DRAM map */
+ .dqs_map = {
+ { 1, 0, 1, 0, 0, 1, 1, 0 },
+ { 1, 0, 1, 0, 1, 0, 1, 0 }
+ },
+
+ .ect = 0, /* Disable Early Command Training */
+};
+
+void variant_memory_init(FSP_M_CONFIG *mem_cfg)
+{
+ const struct spd_info spd_info = {
+ .smbus_info[0] = {.addr_dimm0 = 0xa0,
+ .addr_dimm1 = 0 },
+ .smbus_info[1] = {.addr_dimm0 = 0xa4,
+ .addr_dimm1 = 0 },
+ };
+ const bool half_populated = false;
+ struct mb_ddr4_cfg new_board_cfg_ddr4;
+
+ memcpy(&new_board_cfg_ddr4, &baseboard_memcfg, sizeof(baseboard_memcfg));
+
+ new_board_cfg_ddr4.dq_pins_interleaved = gpio_get(MEMORY_INTERLEAVED);
+
+ meminit_ddr4(mem_cfg, &new_board_cfg_ddr4, &spd_info, half_populated);
+}
diff --git a/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc b/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc
index ea0d5f0..bad6b24 100644
--- a/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc
+++ b/src/mainboard/google/deltaur/variants/deltaur/Makefile.inc
@@ -7,3 +7,4 @@
bootblock-y += gpio.c
ramstage-y += gpio.c
+romstage-y += memory.c
diff --git a/src/mainboard/google/deltaur/variants/deltaur/memory.c b/src/mainboard/google/deltaur/variants/deltaur/memory.c
new file mode 100644
index 0000000..c2df467
--- /dev/null
+++ b/src/mainboard/google/deltaur/variants/deltaur/memory.c
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <variant/gpio.h>
+
+static const struct lpddr4x_cfg baseboard_memcfg = {
+ /* DQ byte map */
+ .dq_map = {
+ [0] = {
+ { 8, 9, 12, 11, 13, 15, 10, 14, }, /* DDR0_DQ0[7:0] */
+ { 4, 6, 0, 2, 5, 7, 1, 3, }, /* DDR0_DQ1[7:0] */
+ },
+ [1] = {
+ { 2, 3, 0, 6, 1, 7, 5, 4, }, /* DDR1_DQ0[7:0] */
+ { 15, 14, 13, 8, 12, 11, 9, 10, }, /* DDR1_DQ1[7:0] */
+ },
+ [2] = {
+ { 1, 0, 3, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */
+ { 14, 15, 12, 13, 8, 10, 9, 11, }, /* DDR2_DQ1[7:0] */
+ },
+ [3] = {
+ { 8, 10, 11, 9, 15, 12, 14, 13, }, /* DDR3_DQ0[7:0] */
+ { 4, 7, 6, 5, 2, 0, 1, 3, }, /* DDR3_DQ1[7:0] */
+ },
+ [4] = {
+ { 8, 9, 10, 11, 13, 12, 15, 14, }, /* DDR4_DQ0[7:0] */
+ { 7, 6, 4, 5, 0, 2, 1, 3, }, /* DDR4_DQ1[7:0] */
+ },
+ [5] = {
+ { 1, 3, 0, 2, 6, 4, 5, 7, }, /* DDR5_DQ0[7:0] */
+ { 14, 15, 10, 12, 8, 13, 11, 9, }, /* DDR5_DQ1[7:0] */
+ },
+ [6] = {
+ { 1, 0, 2, 4, 5, 3, 7, 6, }, /* DDR6_DQ0[7:0] */
+ { 12, 14, 15, 13, 9, 10, 8, 11, }, /* DDR6_DQ1[7:0] */
+ },
+ [7] = {
+ { 11, 9, 8, 13, 12, 14, 15, 10, }, /* DDR7_DQ0[7:0] */
+ { 4, 7, 5, 1, 2, 6, 3, 0, }, /* DDR7_DQ1[7:0] */
+ },
+ },
+
+ /* DQS CPU<>DRAM map */
+ .dqs_map = {
+ [0] = { 1, 0 }, /* DDR0_DQS[1:0] */
+ [1] = { 0, 1 }, /* DDR1_DQS[1:0] */
+ [2] = { 0, 1 }, /* DDR2_DQS[1:0] */
+ [3] = { 1, 0 }, /* DDR3_DQS[1:0] */
+ [4] = { 1, 0 }, /* DDR4_DQS[1:0] */
+ [5] = { 0, 1 }, /* DDR5_DQS[1:0] */
+ [6] = { 0, 1 }, /* DDR6_DQS[1:0] */
+ [7] = { 1, 0 }, /* DDR7_DQS[1:0] */
+ },
+
+ .ect = 0, /* Early Command Training */
+};
+
+const struct lpddr4x_cfg *variant_memory_params(void)
+{
+ return &baseboard_memcfg;
+}
+
+static int variant_memory_sku(void)
+{
+ gpio_t spd_gpios[] = {
+ GPIO_MEM_CONFIG_0,
+ GPIO_MEM_CONFIG_1,
+ GPIO_MEM_CONFIG_2,
+ GPIO_MEM_CONFIG_3,
+ GPIO_MEM_CONFIG_4,
+ };
+
+ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+
+void variant_memory_init(FSP_M_CONFIG *mem_cfg)
+{
+ const struct lpddr4x_cfg *board_cfg = variant_memory_params();
+ const struct spd_info spd_info = {
+ .md_spd_loc = SPD_CBFS,
+ .cbfs_index = variant_memory_sku(),
+ };
+ const bool half_populated = false;
+ meminit_lpddr4x(mem_cfg, board_cfg, &spd_info, half_populated);
+}