soc/intel/skylake: Align PMC offset 0x31C name with CNL
As per EDS PMC BASE Offset 0x31C is known as CPPMVRIC hence rename
CIR31C with CPPMVRIC.
Change-Id: Idaff62fb742e6c58b1d8e662b5e4087fa2da79a3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45795
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 98f12a5..0294a72 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -81,9 +81,9 @@
/* Disable XTAL shutdown qualification for low power idle. */
if (config->s0ix_enable) {
- reg32 = read32(pmcbase + CIR31C);
+ reg32 = read32(pmcbase + CPPMVRIC);
reg32 |= XTALSDQDIS;
- write32(pmcbase + CIR31C, reg32);
+ write32(pmcbase + CPPMVRIC, reg32);
}
/* we should disable Heci1 based on the devicetree policy */
diff --git a/src/soc/intel/skylake/include/soc/pmc.h b/src/soc/intel/skylake/include/soc/pmc.h
index f4995a2..68d9eb3 100644
--- a/src/soc/intel/skylake/include/soc/pmc.h
+++ b/src/soc/intel/skylake/include/soc/pmc.h
@@ -82,6 +82,6 @@
#define GPE0_DW_SHIFT(x) (4*(x))
#define GBLRST_CAUSE0 0x124
#define GBLRST_CAUSE1 0x128
-#define CIR31C 0x31c
+#define CPPMVRIC 0x31c
#define XTALSDQDIS (1 << 22)
#endif