diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index ca107c4..4e0f391 100644
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -22,6 +22,7 @@
 
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
 #include <cpu/x86/lapic_def.h>
 
@@ -188,7 +189,7 @@
 
 	/* Do not disable cache (so BSP can enable it). */
         movl	%cr0, %eax
-	andl	$(~((1 << 30) | (1 << 29))), %eax
+	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
 	movl	%eax, %cr0
 
 	post_code(0x28)
@@ -271,7 +272,7 @@
 
 	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
 	movl	%cr0, %eax
-	andl	$(~((1 << 30) | (1 << 29))), %eax
+	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
 	invd
 	movl	%eax, %cr0
 
@@ -284,7 +285,7 @@
 
 	/* Enable Cache-as-RAM mode by disabling cache. */
 	movl	%cr0, %eax
-	orl	$(1 << 30), %eax
+	orl	$CR0_CacheDisable, %eax
 	movl	%eax, %cr0
 
 	post_code(0x2d)
@@ -310,7 +311,7 @@
 
 	/* Enable cache. */
 	movl	%cr0, %eax
-	andl	$(~((1 << 30) | (1 << 29))), %eax
+	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
 	movl	%eax, %cr0
 
 	post_code(0x2e)
@@ -338,7 +339,7 @@
 
 	/* Disable cache. */
 	movl	%cr0, %eax
-	orl	$(1 << 30), %eax
+	orl	$CR0_CacheDisable, %eax
 	movl	%eax, %cr0
 
 	post_code(0x34)
@@ -357,14 +358,14 @@
 
 	/* Enable cache. */
 	movl	%cr0, %eax
-	andl	$~((1 << 30) | (1 << 29)), %eax
+	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
 	movl	%eax, %cr0
 
 	post_code(0x37)
 
 	/* Disable cache. */
 	movl	%cr0, %eax
-	orl	$(1 << 30), %eax
+	orl	$CR0_CacheDisable, %eax
 	movl	%eax, %cr0
 
 	post_code(0x38)
@@ -393,7 +394,7 @@
 
 	/* And enable cache again after setting MTRRs. */
 	movl	%cr0, %eax
-	andl	$~((1 << 30) | (1 << 29)), %eax
+	andl	$~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
 	movl	%eax, %cr0
 
 	post_code(0x3a)