| #define ASSEMBLY 1 |
| #define __ROMCC__ |
| |
| #define RAMINIT_SYSINFO 0 |
| |
| #if CONFIG_LOGICAL_CPUS==1 |
| #define SET_NB_CFG_54 1 |
| #endif |
| |
| //use by raminit |
| #define QRANK_DIMM_SUPPORT 1 |
| |
| //used by incoherent_ht |
| //#define K8_SCAN_PCI_BUS 1 |
| //#define K8_ALLOCATE_IO_RANGE 1 |
| |
| #include <stdint.h> |
| #include <device/pci_def.h> |
| #include <device/pci_ids.h> |
| #include <arch/io.h> |
| #include <device/pnp_def.h> |
| #include <arch/romcc_io.h> |
| #include <cpu/x86/lapic.h> |
| #include "option_table.h" |
| #include "pc80/mc146818rtc_early.c" |
| |
| #if USE_FAILOVER_IMAGE==0 |
| #include "pc80/serial.c" |
| #include "arch/i386/lib/console.c" |
| |
| #if 0 |
| static void post_code(uint8_t value) { |
| #if 1 |
| int i; |
| for(i=0;i<0x80000;i++) { |
| outb(value, 0x80); |
| } |
| #endif |
| } |
| #endif |
| |
| #include <cpu/amd/model_fxx_rev.h> |
| #include "southbridge/amd/amd8111/amd8111_early_smbus.c" |
| #include "northbridge/amd/amdk8/raminit.h" |
| #include "cpu/amd/model_fxx/apic_timer.c" |
| #include "lib/delay.c" |
| |
| #endif |
| |
| #include "cpu/x86/lapic/boot_cpu.c" |
| #include "northbridge/amd/amdk8/reset_test.c" |
| |
| #if USE_FAILOVER_IMAGE==0 |
| |
| #if CONFIG_USE_INIT == 0 |
| #include "lib/memcpy.c" |
| #if CONFIG_USE_PRINTK_IN_CAR == 1 |
| #include "lib/uart8250.c" |
| #include "console/vtxprintf.c" |
| #include "arch/i386/lib/printk_init.c" |
| #endif |
| #endif |
| |
| #include "northbridge/amd/amdk8/debug.c" |
| #include "superio/winbond/w83627hf/w83627hf_early_serial.c" |
| |
| #include "cpu/amd/mtrr/amd_earlymtrr.c" |
| #include "cpu/x86/bist.h" |
| |
| #include "northbridge/amd/amdk8/setup_resource_map.c" |
| #include "northbridge/amd/amdk8/incoherent_ht.c" |
| |
| #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
| |
| #include "southbridge/amd/amd8111/amd8111_early_ctrl.c" |
| |
| static void memreset_setup(void) |
| { |
| if (is_cpu_pre_c0()) { |
| outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 |
| } |
| else { |
| outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 |
| } |
| outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); |
| } |
| |
| static void memreset(int controllers, const struct mem_controller *ctrl) |
| { |
| if (is_cpu_pre_c0()) { |
| udelay(800); |
| outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 |
| udelay(90); |
| } |
| } |
| |
| static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| { |
| #define SMBUS_HUB 0x18 |
| int ret,i; |
| unsigned device=(ctrl->channel0[0])>>8; |
| /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ |
| i=2; |
| do { |
| ret = smbus_write_byte(SMBUS_HUB, 0x01, device); |
| } while ((ret!=0) && (i-->0)); |
| |
| smbus_write_byte(SMBUS_HUB, 0x03, 0); |
| } |
| #if 0 |
| static inline void change_i2c_mux(unsigned device) |
| { |
| #define SMBUS_HUB 0x18 |
| int ret, i; |
| print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\r\n"); |
| i=2; |
| do { |
| ret = smbus_write_byte(SMBUS_HUB, 0x01, device); |
| print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\r\n"); |
| } while ((ret!=0) && (i-->0)); |
| ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); |
| print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\r\n"); |
| } |
| #endif |
| |
| static inline int spd_read_byte(unsigned device, unsigned address) |
| { |
| return smbus_read_byte(device, address); |
| } |
| |
| |
| #include "northbridge/amd/amdk8/raminit.c" |
| #include "northbridge/amd/amdk8/coherent_ht.c" |
| #include "sdram/generic_sdram.c" |
| |
| /* tyan does not want the default */ |
| #include "resourcemap.c" |
| |
| #include "cpu/amd/dualcore/dualcore.c" |
| |
| #define RC0 ((1<<0)<<8) |
| #define RC1 ((1<<1)<<8) |
| |
| #define DIMM0 0x50 |
| #define DIMM1 0x51 |
| |
| #include "cpu/amd/car/copy_and_run.c" |
| #include "cpu/amd/car/post_cache_as_ram.c" |
| |
| #include "cpu/amd/model_fxx/init_cpus.c" |
| |
| #endif |
| |
| #if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1)) |
| |
| #include "southbridge/amd/amd8111/amd8111_enable_rom.c" |
| #include "northbridge/amd/amdk8/early_ht.c" |
| |
| void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) |
| { |
| unsigned last_boot_normal_x = last_boot_normal(); |
| |
| /* Is this a cpu only reset? or Is this a secondary cpu? */ |
| if ((cpu_init_detectedx) || (!boot_cpu())) { |
| if (last_boot_normal_x) { |
| goto normal_image; |
| } else { |
| goto fallback_image; |
| } |
| } |
| |
| /* Nothing special needs to be done to find bus 0 */ |
| /* Allow the HT devices to be found */ |
| |
| enumerate_ht_chain(); |
| |
| /* Setup the flash access */ |
| amd8111_enable_rom(); |
| |
| /* Is this a deliberate reset by the bios */ |
| // post_code(0x22); |
| if (bios_reset_detected() && last_boot_normal_x) { |
| goto normal_image; |
| } |
| /* This is the primary cpu how should I boot? */ |
| else if (do_normal_boot()) { |
| goto normal_image; |
| } |
| else { |
| goto fallback_image; |
| } |
| normal_image: |
| // post_code(0x23); |
| __asm__ volatile ("jmp __normal_image" |
| : /* outputs */ |
| : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ |
| ); |
| |
| fallback_image: |
| // post_code(0x25); |
| #if HAVE_FAILOVER_BOOT==1 |
| __asm__ volatile ("jmp __fallback_image" |
| : /* outputs */ |
| : "a" (bist), "b" (cpu_init_detectedx) /* inputs */ |
| ) |
| #endif |
| ; |
| } |
| #endif |
| void real_main(unsigned long bist, unsigned long cpu_init_detectedx); |
| |
| void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| { |
| #if HAVE_FAILOVER_BOOT==1 |
| #if USE_FAILOVER_IMAGE==1 |
| failover_process(bist, cpu_init_detectedx); |
| #else |
| real_main(bist, cpu_init_detectedx); |
| #endif |
| #else |
| #if USE_FALLBACK_IMAGE == 1 |
| failover_process(bist, cpu_init_detectedx); |
| #endif |
| real_main(bist, cpu_init_detectedx); |
| #endif |
| } |
| |
| #if USE_FAILOVER_IMAGE==0 |
| |
| void real_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| { |
| static const uint16_t spd_addr [] = { |
| RC0|DIMM0, 0, 0, 0, |
| RC0|DIMM1, 0, 0, 0, |
| #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
| RC1|DIMM0, 0 , 0, 0, |
| RC1|DIMM1, 0 , 0, 0, |
| #endif |
| }; |
| |
| int needs_reset; |
| unsigned bsp_apicid = 0; |
| |
| struct mem_controller ctrl[8]; |
| unsigned nodes; |
| |
| if (bist == 0) { |
| bsp_apicid = init_cpus(cpu_init_detectedx); |
| } |
| |
| // post_code(0x32); |
| |
| w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); |
| uart_init(); |
| console_init(); |
| |
| // dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); |
| |
| /* Halt if there was a built in self test failure */ |
| report_bist_failure(bist); |
| |
| print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); |
| |
| setup_serengeti_leopard_resource_map(); |
| #if 0 |
| dump_pci_device(PCI_DEV(0, 0x18, 0)); |
| dump_pci_device(PCI_DEV(0, 0x19, 0)); |
| #endif |
| |
| needs_reset = setup_coherent_ht_domain(); |
| |
| wait_all_core0_started(); |
| #if CONFIG_LOGICAL_CPUS==1 |
| // It is said that we should start core1 after all core0 launched |
| /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
| * So here need to make sure last core0 is started, esp for two way system, |
| * (there may be apic id conflicts in that case) |
| */ |
| start_other_cores(); |
| wait_all_other_cores_started(bsp_apicid); |
| #endif |
| |
| needs_reset |= ht_setup_chains_x(); |
| |
| if (needs_reset) { |
| print_info("ht reset -\r\n"); |
| soft_reset(); |
| } |
| |
| allow_all_aps_stop(bsp_apicid); |
| |
| nodes = get_nodes(); |
| //It's the time to set ctrl now; |
| fill_mem_ctrl(nodes, ctrl, spd_addr); |
| |
| enable_smbus(); |
| #if 0 |
| dump_spd_registers(&cpu[0]); |
| #endif |
| #if 0 |
| dump_smbus_registers(); |
| #endif |
| |
| memreset_setup(); |
| |
| // init_timer(); // Need to use TMICT to synconize FID/VID |
| |
| sdram_initialize(nodes, ctrl); |
| |
| #if 0 |
| print_pci_devices(); |
| #endif |
| |
| #if 0 |
| dump_pci_devices(); |
| #endif |
| |
| post_cache_as_ram(); |
| |
| } |
| |
| #endif |