x86: Add pre-memory stages CBFS cache scratchpad support
Having a CBFS cache scratchpad offers a generic way to decompress CBFS
files through the cbfs_map() function without having to reserve a
per-file specific memory region.
This commit introduces the x86 `PRERAM_CBFS_CACHE_SIZE' Kconfig to set
the pre-memory stages CBFS cache size. A cache size of zero disables
the CBFS cache feature. The default value is 16 KB which seems a
reasonable minimal value enough to satisfy basic needs such as the
decompression of a small configuration file. This setting can be
adjusted depending on the platform needs and capabilities.
We have set this size to zero for all the platforms without enough
space in Cache-As-RAM to accommodate the default size.
TEST=Decompression of vbt.bin in romstage on rex using cbfs_map()
Change-Id: Iee493f9947fddcc57576f04c3d6a2d58c7368e09
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index c97fecb..b0e479b 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -153,6 +153,13 @@
Increase this value if you see CBFS mcache overflow warnings. Do NOT
change this value for vboot RW updates!
+config PRERAM_CBFS_CACHE_SIZE
+ hex
+ default 0x4000
+ help
+ Define the size of the Pre-RAM stages CBFS cache. A size of
+ zero disables the CBFS cache feature in pre-memory stages.
+
config PC80_SYSTEM
bool
default y if ARCH_X86
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld
index 14fdba6..2ad1ca2 100644
--- a/src/arch/x86/car.ld
+++ b/src/arch/x86/car.ld
@@ -51,6 +51,9 @@
FMAP_CACHE(., FMAP_SIZE)
#endif
+ . = ALIGN(CONFIG_CBFS_CACHE_ALIGN);
+ CBFS_CACHE(., CONFIG_PRERAM_CBFS_CACHE_SIZE)
+
/* Reserve sizeof(struct ehci_dbg_info). */
REGION(car_ehci_dbg_info, ., 80, 1)
diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig
index 4ba8747..fffca39 100644
--- a/src/cpu/intel/slot_1/Kconfig
+++ b/src/cpu/intel/slot_1/Kconfig
@@ -24,6 +24,9 @@
hex
default 0x02000
+config PRERAM_CBFS_CACHE_SIZE
+ default 0x0
+
config DCACHE_BSP_STACK_SIZE
hex
default 0x1000
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig
index 1a549ac..381b72b 100644
--- a/src/cpu/intel/socket_441/Kconfig
+++ b/src/cpu/intel/socket_441/Kconfig
@@ -13,6 +13,9 @@
hex
default 0x8000
+config PRERAM_CBFS_CACHE_SIZE
+ default 0x0
+
config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig
index 7c42722..9197faa 100644
--- a/src/cpu/intel/socket_BGA956/Kconfig
+++ b/src/cpu/intel/socket_BGA956/Kconfig
@@ -12,6 +12,9 @@
hex
default 0x10000
+config PRERAM_CBFS_CACHE_SIZE
+ default 0x0
+
config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig
index 223f80d..95099c5 100644
--- a/src/cpu/intel/socket_FCBGA559/Kconfig
+++ b/src/cpu/intel/socket_FCBGA559/Kconfig
@@ -15,6 +15,9 @@
hex
default 0x8000
+config PRERAM_CBFS_CACHE_SIZE
+ default 0x0
+
config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig
index 63d6250..870fd78 100644
--- a/src/cpu/intel/socket_LGA775/Kconfig
+++ b/src/cpu/intel/socket_LGA775/Kconfig
@@ -12,6 +12,9 @@
hex
default 0x8000 # 32 kB
+config PRERAM_CBFS_CACHE_SIZE
+ default 0x0
+
config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig
index 2e653e9..2e6d432 100644
--- a/src/cpu/intel/socket_m/Kconfig
+++ b/src/cpu/intel/socket_m/Kconfig
@@ -13,6 +13,9 @@
hex
default 0x8000
+config PRERAM_CBFS_CACHE_SIZE
+ default 0x0
+
config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig
index 8f28670..92a0b43 100644
--- a/src/cpu/intel/socket_mPGA604/Kconfig
+++ b/src/cpu/intel/socket_mPGA604/Kconfig
@@ -17,6 +17,9 @@
hex
default 0x4000
+config PRERAM_CBFS_CACHE_SIZE
+ default 0x0
+
config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index b7738a2..34a0939 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -172,4 +172,7 @@
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
+config PRERAM_CBFS_CACHE_SIZE
+ default 0x0
+
endif
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 6ff135e..bd55b71 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -103,6 +103,9 @@
hex
default 0x10000
+config PRERAM_CBFS_CACHE_SIZE
+ default 0x0
+
config DCACHE_BSP_STACK_SIZE
hex
default 0x4000
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 13fd201..dbadbf1 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -110,6 +110,9 @@
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.
+config PRERAM_CBFS_CACHE_SIZE
+ default 0x0
+
config DCACHE_RAM_MRC_VAR_SIZE
hex
default 0x8000
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index ba6450b..5aeb9e5 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -97,6 +97,9 @@
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.
+config PRERAM_CBFS_CACHE_SIZE
+ default 0x0
+
config ENABLE_BUILTIN_COM1
bool "Enable builtin COM1 Serial Port"
default n