soc|vc/amd/phoenix: Prepare for PSP verstage
Update all the required sources to lay the ground work to enable PSP
verstage.
BUG=b:284984667
TEST=Build Myst BIOS image with PSP verstage enabled.
Change-Id: I6fbb1f835ac2ad6ff47f843321e1bd380af7ce33
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75584
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
diff --git a/src/soc/amd/phoenix/include/soc/psp_verstage_addr.h b/src/soc/amd/phoenix/include/soc/psp_verstage_addr.h
index ee9deda..30f65f6 100644
--- a/src/soc/amd/phoenix/include/soc/psp_verstage_addr.h
+++ b/src/soc/amd/phoenix/include/soc/psp_verstage_addr.h
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* TODO: Update for Phoenix */
-
#ifndef AMD_PHOENIX_PSP_VERSTAGE_ADDR_H
#define AMD_PHOENIX_PSP_VERSTAGE_ADDR_H
diff --git a/src/soc/amd/phoenix/psp_verstage/Makefile.inc b/src/soc/amd/phoenix/psp_verstage/Makefile.inc
index 6ff447c..6a2eace 100644
--- a/src/soc/amd/phoenix/psp_verstage/Makefile.inc
+++ b/src/soc/amd/phoenix/psp_verstage/Makefile.inc
@@ -1,10 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
-ifeq $($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
+subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage
-subdirs-y += ../../common/psp_verstage
-
-verstage-generic-ccopts += -I$(src)/soc/amd/phoenix/psp_verstage/include
verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include
verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/phoenix/include
verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/common/include
@@ -15,5 +12,3 @@
verstage-y +=$(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_startup.S
verstage-y += $(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S
-
-endif
diff --git a/src/soc/amd/phoenix/psp_verstage/chipset.c b/src/soc/amd/phoenix/psp_verstage/chipset.c
index 3f3a7cf..acbd559 100644
--- a/src/soc/amd/phoenix/psp_verstage/chipset.c
+++ b/src/soc/amd/phoenix/psp_verstage/chipset.c
@@ -1,11 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* TODO: Update for Phoenix */
-
+#include "2api.h"
+#include <arch/hlt.h>
+#include <bl_uapp/bl_errorcodes_public.h>
#include <bl_uapp/bl_syscall_public.h>
+#include <boot_device.h>
#include <cbfs.h>
#include <console/console.h>
#include <psp_verstage.h>
+#include <security/vboot/misc.h>
+#include <security/vboot/vbnv.h>
/*
* We can't pass pointer to hash table in the SPI.
@@ -20,7 +24,8 @@
void update_psp_fw_hash_table(const char *fname)
{
- uint8_t *spi_ptr = (uint8_t *)cbfs_map(fname, NULL);
+ void *hash_file = cbfs_map(fname, NULL);
+ uint8_t *spi_ptr = (uint8_t *)hash_file;
uint32_t len;
if (!spi_ptr) {
@@ -39,6 +44,8 @@
printk(BIOS_ERR, "Too many entries in AMD Firmware hash table"
" (SHA256:%d, SHA384:%d)\n",
hash_table.no_of_entries_256, hash_table.no_of_entries_384);
+ cbfs_unmap(hash_file);
+ rdev_munmap(boot_device_ro(), hash_file);
return;
}
@@ -47,6 +54,8 @@
printk(BIOS_ERR, "No entries in AMD Firmware hash table"
" (SHA256:%d, SHA384:%d)\n",
hash_table.no_of_entries_256, hash_table.no_of_entries_384);
+ cbfs_unmap(hash_file);
+ rdev_munmap(boot_device_ro(), hash_file);
return;
}
@@ -62,6 +71,8 @@
memcpy(hash_384, spi_ptr, len);
svc_set_fw_hash_table(&hash_table);
+ cbfs_unmap(hash_file);
+ rdev_munmap(boot_device_ro(), hash_file);
}
uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset)
@@ -94,16 +105,6 @@
return 0;
}
-
-/* Functions below are stub functions for not-yet-implemented PSP features.
- * These functions should be replaced with proper implementations later.
- */
-
-uint32_t svc_write_postcode(uint32_t postcode)
-{
- return 0;
-}
-
void platform_report_mode(int developer_mode_enabled)
{
printk(BIOS_INFO, "Reporting %s mode\n",
@@ -113,3 +114,36 @@
else
svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_NORMAL);
}
+
+void report_prev_boot_status_to_vboot(void)
+{
+ uint32_t boot_status = 0;
+ int ret;
+ struct vb2_context *ctx = vboot_get_context();
+
+ /* Already in recovery mode. No need to report previous boot status. */
+ if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE)
+ return;
+
+ ret = svc_get_prev_boot_status(&boot_status);
+ if (ret != BL_OK || boot_status) {
+ printk(BIOS_ERR, "PSPFW failure in previous boot: %d:%#8x\n", ret, boot_status);
+ vbnv_init();
+ vb2api_previous_boot_fail(ctx, VB2_RECOVERY_FW_VENDOR_BLOB,
+ boot_status ? (int)boot_status : ret);
+ }
+}
+
+void report_hsp_secure_state(void)
+{
+ uint32_t hsp_secure_state;
+ int ret;
+
+ ret = svc_get_hsp_secure_state(&hsp_secure_state);
+ if (ret != BL_OK) {
+ printk(BIOS_ERR, "Error reading HSP Secure state: %d\n", ret);
+ hlt();
+ }
+
+ printk(BIOS_INFO, "HSP Secure state: %#8x\n", hsp_secure_state);
+}
diff --git a/src/soc/amd/phoenix/psp_verstage/svc.c b/src/soc/amd/phoenix/psp_verstage/svc.c
index becfcb0..c88f759 100644
--- a/src/soc/amd/phoenix/psp_verstage/svc.c
+++ b/src/soc/amd/phoenix/psp_verstage/svc.c
@@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-/* TODO: Update for Phoenix */
-
#include "svc.h"
#include <assert.h>
@@ -217,3 +215,32 @@
SVC_CALL2(SVC_VERSTAGE_CMD, CMD_SET_FW_HASH_TABLE, (void *)¶m, retval);
return retval;
}
+
+uint32_t svc_get_prev_boot_status(uint32_t *boot_status)
+{
+ uint32_t retval = 0;
+ struct cmd_param_get_prev_boot_status param = {
+ .ptr_boot_status = boot_status,
+ };
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_GET_PREV_BOOT_STATUS, (void *)¶m, retval);
+ return retval;
+}
+
+uint32_t svc_get_hsp_secure_state(uint32_t *hsp_secure_state)
+{
+ uint32_t retval = 0;
+ struct cmd_param_get_hsp_secure_state param;
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_GET_HSP_SECURE_STATE, (void *)¶m, retval);
+ *hsp_secure_state = param.hsp_secure_state;
+ return retval;
+}
+
+uint32_t svc_write_postcode(uint32_t postcode)
+{
+ uint32_t retval = 0;
+ struct cmd_param_postcode param = {
+ .postcode = postcode,
+ };
+ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_WRITE_POSTCODE, (void *)¶m, retval);
+ return retval;
+}
diff --git a/src/soc/amd/phoenix/psp_verstage/svc.h b/src/soc/amd/phoenix/psp_verstage/svc.h
index 3c59a1c..c3e6475 100644
--- a/src/soc/amd/phoenix/psp_verstage/svc.h
+++ b/src/soc/amd/phoenix/psp_verstage/svc.h
@@ -95,4 +95,16 @@
struct psp_fw_hash_table *ptr_psp_fw_hash_table;
};
+struct cmd_param_get_prev_boot_status {
+ unsigned int *ptr_boot_status;
+};
+
+struct cmd_param_get_hsp_secure_state {
+ unsigned int hsp_secure_state;
+};
+
+struct cmd_param_postcode {
+ uint32_t postcode;
+};
+
#endif /* PSP_VERSTAGE_SVC_H */
diff --git a/src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h
index 30ea49f..623762a 100644
--- a/src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h
+++ b/src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h
@@ -57,6 +57,9 @@
CMD_CCP_DMA,
CMD_SET_PLATFORM_BOOT_MODE,
CMD_SET_FW_HASH_TABLE,
+ CMD_GET_PREV_BOOT_STATUS,
+ CMD_GET_HSP_SECURE_STATE,
+ CMD_WRITE_POSTCODE,
};
struct mod_exp_params {
@@ -94,6 +97,7 @@
FCH_IO_DEVICE_MISC,
FCH_IO_DEVICE_AOAC,
FCH_IO_DEVICE_IOPORT,
+ FCH_IO_DEVICE_UART,
FCH_IO_DEVICE_END,
};
@@ -105,6 +109,12 @@
FCH_I2C_CONTROLLER_ID_MAX,
};
+enum fch_uart_id {
+ FCH_UART_ID_0 = 0,
+ FCH_UART_ID_1 = 1,
+ FCH_UART_ID_MAX,
+};
+
struct spirom_info {
void *SpiBiosSysHubBase;
void *SpiBiosSmnBase;
@@ -371,6 +381,24 @@
*/
uint32_t svc_set_fw_hash_table(struct psp_fw_hash_table *hash_table);
+/* Get the previous boot status.
+ *
+ * Parameters:
+ * - boot_status - Address where the boot status is read into
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_get_prev_boot_status(uint32_t *boot_status);
+
+/* Get HSP Secure state
+ *
+ * Parameters:
+ * - hsp_secure_state - Address where the state info is read into
+ *
+ * Return value: BL_OK or error code
+ */
+uint32_t svc_get_hsp_secure_state(uint32_t *hsp_secure_state);
+
/* C entry point for the Bootloader Userspace Application */
void Main(void);