sb,soc/intel: Set IOAPIC redirection entry count
The number of redirection table entries (aka interrupt vectors) inside
an I/O APIC may depend of the SKU, with the related register being of
type read/write-once. Provide support utilities to either lock or set
this registers value.
Change-Id: I8da869ba390dd821b43032e4ccbc9291c39e6bab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c
index 41da81e..40cc61e 100644
--- a/src/soc/intel/broadwell/pch/lpc.c
+++ b/src/soc/intel/broadwell/pch/lpc.c
@@ -25,8 +25,6 @@
static void pch_enable_ioapic(struct device *dev)
{
- u32 reg32;
-
/* Assign unique bus/dev/fn for I/O APIC */
pci_write_config16(dev, LPC_IBDF,
PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
@@ -34,13 +32,8 @@
set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
- reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
-
- /* PCH-LP has 39 redirection entries */
- reg32 &= ~0x00ff0000;
- reg32 |= 0x00270000;
-
- io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
+ /* PCH-LP has 40 redirection entries */
+ ioapic_set_max_vectors(VIO_APIC_VADDR, 40);
}
static void enable_hpet(struct device *dev)
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 0268245..c2278df 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -274,22 +274,16 @@
pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN);
}
+/* PCH I/O APIC redirection entries */
+#define PCH_REDIR_ETR 120
+
/* Enable PCH IOAPIC */
void pch_enable_ioapic(void)
{
- uint32_t reg32;
- /* PCH-LP has 120 redirection entries */
- const int redir_entries = 120;
-
set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
- reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
-
- reg32 &= ~0x00ff0000;
- reg32 |= (redir_entries - 1) << 16;
-
- io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
+ ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR);
}
static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = {
diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c
index a099c31..7f47e5e 100644
--- a/src/soc/intel/denverton_ns/lpc.c
+++ b/src/soc/intel/denverton_ns/lpc.c
@@ -21,8 +21,8 @@
#include "chip.h"
-/* PCH-LP redirection entries */
-#define PCH_LP_REDIR_ETR 120
+/* PCH I/O APIC redirection entries */
+#define PCH_REDIR_ETR 120
/**
* Set miscellaneous static southbridge features.
@@ -31,17 +31,10 @@
*/
static void pch_enable_ioapic(struct device *dev)
{
- u32 reg32;
-
set_ioapic_id((void *)IO_APIC_ADDR, IO_APIC0);
/* affirm full set of redirection table entries ("write once") */
- reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
-
- reg32 &= ~0x00ff0000;
- reg32 |= (PCH_LP_REDIR_ETR - 1) << 16;
-
- io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
+ ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR);
}
/* interrupt router lookup for internal devices */