Inteltool: Add i830/Tolapai/Ich4 support
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/util/inteltool/powermgt.c b/util/inteltool/powermgt.c
index d479bfd..fbf9e3a 100644
--- a/util/inteltool/powermgt.c
+++ b/util/inteltool/powermgt.c
@@ -1,7 +1,7 @@
/*
* inteltool - dump all registers on an Intel CPU + chipset based system.
*
- * Copyright (C) 2008 by coresystems GmbH
+ * Copyright (C) 2008-2010 by coresystems GmbH
* written by Stefan Reinauer <stepan@coresystems.de>
*
* This program is free software; you can redistribute it and/or modify
@@ -145,6 +145,68 @@
{ 0x7c, 4, "RESERVED" },
};
+static const io_register_t ich4_pm_registers[] = {
+ { 0x00, 2, "PM1_STS" },
+ { 0x02, 2, "PM1_EN" },
+ { 0x04, 4, "PM1_CNT" },
+ { 0x08, 4, "PM1_TMR" },
+ { 0x0c, 4, "RESERVED" },
+ { 0x10, 4, "PROC_CNT" },
+#if DANGEROUS_REGISTERS
+ /* These registers return 0 on read, but reading them may cause
+ * the system to enter C2/C3/C4 state, which might hang the system.
+ */
+ { 0x14, 1, "LV2 (Mobile)" },
+ { 0x15, 1, "LV3 (Mobile)" },
+ { 0x16, 1, "LV4 (Mobile)" },
+#endif
+ { 0x17, 1, "RESERVED" },
+ { 0x18, 4, "RESERVED" },
+ { 0x1c, 4, "RESERVED" },
+ { 0x20, 1, "PM2_CNT (Mobile)" },
+ { 0x21, 1, "RESERVED" },
+ { 0x22, 2, "RESERVED" },
+ { 0x24, 4, "RESERVED" },
+ { 0x28, 4, "GPE0_STS" },
+ { 0x2C, 4, "GPE0_EN" },
+ { 0x30, 4, "SMI_EN" },
+ { 0x34, 4, "SMI_STS" },
+ { 0x38, 2, "ALT_GP_SMI_EN" },
+ { 0x3a, 2, "ALT_GP_SMI_STS" },
+ { 0x3c, 4, "RESERVED" },
+ { 0x40, 2, "MON_SMI" },
+ { 0x42, 2, "RESERVED" },
+ { 0x44, 2, "DEVACT_STS" },
+ { 0x46, 2, "RESERVED" },
+ { 0x48, 4, "DEVTRAP_EN" },
+ { 0x4c, 2, "BUS_ADDR_TRACK" },
+ { 0x4e, 2, "BUS_CYC_TRACK" },
+ { 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" },
+ { 0x51, 1, "RESERVED" },
+ { 0x52, 2, "RESERVED" },
+ { 0x54, 4, "RESERVED" },
+ { 0x58, 4, "RESERVED" },
+ { 0x5c, 4, "RESERVED" },
+ /* Here start the TCO registers */
+ { 0x60, 1, "TCO_RLD" },
+ { 0x61, 1, "TCO_TMR" },
+ { 0x62, 1, "TCO_DAT_IN" },
+ { 0x63, 1, "TCO_DAT_OUT" },
+ { 0x64, 2, "TCO1_STS" },
+ { 0x66, 2, "TCO2_STS" },
+ { 0x68, 2, "TCO1_CNT" },
+ { 0x6a, 2, "TCO2_CNT" },
+ { 0x6c, 2, "TCO_MESSAGE" },
+ { 0x6e, 1, "TCO_WDSTATUS" },
+ { 0x6f, 1, "RESERVED" },
+ { 0x70, 1, "SW_IRQ_GEN" },
+ { 0x71, 1, "RESERVED" },
+ { 0x72, 2, "RESERVED" },
+ { 0x74, 4, "RESERVED" },
+ { 0x78, 4, "RESERVED" },
+ { 0x7c, 4, "RESERVED" },
+};
+
static const io_register_t ich0_pm_registers[] = {
{ 0x00, 2, "PM1_STS" },
{ 0x02, 2, "PM1_EN" },
@@ -269,6 +331,11 @@
pm_registers = ich8_pm_registers;
size = ARRAY_SIZE(ich8_pm_registers);
break;
+ case PCI_DEVICE_ID_INTEL_ICH4:
+ pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+ pm_registers = ich4_pm_registers;
+ size = ARRAY_SIZE(ich4_pm_registers);
+ break;
case PCI_DEVICE_ID_INTEL_ICH0:
pmbase = pci_read_word(sb, 0x40) & 0xfffc;
pm_registers = ich0_pm_registers;