tree bea7178ed0bc40dd3a24ede70235024462210d7b
parent f5a48989b4d005158917b9890340f416dad506f1
author Mario Scheithauer <mario.scheithauer@siemens.com> 1683721829 +0200
committer Felix Held <felix-coreboot@felixheld.de> 1684927550 +0000

mb/siemens/mc_ehl4: Double payload size to 256 bytes for PCIe RP #2, #3

To improve the rate of data transfer for PCIe root port #2 (00:1c.1) and
root port #3 (00:1c.2) set the max payload size to 256 bytes for both
root ports.

Change-Id: I553f6cf090d799fbbaafb925646c6566d6951a86
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75127
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>