diff --git a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
index e471b4f..cb6cc2c 100644
--- a/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
+++ b/src/soc/mediatek/mt8173/dramc_pi_basic_api.c
@@ -381,15 +381,15 @@
 	}
 
 	/* mempll new power-on */
-	write32(&mt8173_spm->poweron_config_set, 0x1 << 0 |
+	write32(&mtk_spm->poweron_config_set, 0x1 << 0 |
 						 SPM_PROJECT_CODE << 16);
 	/* request mempll reset/pdn mode */
-	setbits_le32(&mt8173_spm->power_on_val0, 0x1 << 27);
+	setbits_le32(&mtk_spm->power_on_val0, 0x1 << 27);
 
 	udelay(2);
 
 	/* unrequest mempll reset/pdn mode and wait settle */
-	clrbits_le32(&mt8173_spm->power_on_val0, 0x1 << 27);
+	clrbits_le32(&mtk_spm->power_on_val0, 0x1 << 27);
 
 	udelay(31);  /* PLL ready */
 
diff --git a/src/soc/mediatek/mt8173/include/soc/mtcmos.h b/src/soc/mediatek/mt8173/include/soc/mtcmos.h
index a2b4f65..5460e1f 100644
--- a/src/soc/mediatek/mt8173/include/soc/mtcmos.h
+++ b/src/soc/mediatek/mt8173/include/soc/mtcmos.h
@@ -13,9 +13,10 @@
  * GNU General Public License for more details.
  */
 
-#ifndef __SOC_MEDIATEK_MT8173_MTCMOS_H__
-#define __SOC_MEDIATEK_MT8173_MTCMOS_H__
+#ifndef __SOC_MEDIATEK_COMMON_MTCMOS_H__
+#define __SOC_MEDIATEK_COMMON_MTCMOS_H__
 
 void mtcmos_audio_power_on(void);
 void mtcmos_display_power_on(void);
-#endif /* __SOC_MEDIATEK_MT8173_MTCMOS_H__ */
+
+#endif /* __SOC_MEDIATEK_COMMON_MTCMOS_H__ */
diff --git a/src/soc/mediatek/mt8173/include/soc/spm.h b/src/soc/mediatek/mt8173/include/soc/spm.h
index 77516fc..133c8a3 100644
--- a/src/soc/mediatek/mt8173/include/soc/spm.h
+++ b/src/soc/mediatek/mt8173/include/soc/spm.h
@@ -23,7 +23,14 @@
 	SPM_PROJECT_CODE = 0xb16
 };
 
-struct mt8173_spm_regs {
+enum {
+	DISP_SRAM_PDN_MASK	= 0xf << 8,
+	DISP_SRAM_ACK_MASK	= 0x1 << 12,
+	AUDIO_SRAM_PDN_MASK	= 0xf << 8,
+	AUDIO_SRAM_ACK_MASK	= 0xf << 12,
+};
+
+struct mtk_spm_regs {
 	u32 poweron_config_set;
 	u32 reserved1[3];
 	u32 power_on_val0;		/* 0x010 */
@@ -152,8 +159,8 @@
 	u32 sleep_ca15_wfi_en[4];
 };
 
-check_member(mt8173_spm_regs, sleep_ca15_wfi_en[3], 0xf1c);
+check_member(mtk_spm_regs, sleep_ca15_wfi_en[3], 0xf1c);
 
-static struct mt8173_spm_regs *const mt8173_spm = (void *)SPM_BASE;
+static struct mtk_spm_regs *const mtk_spm = (void *)SPM_BASE;
 
 #endif  /* __SOC_MEDIATEK_MT8173_SPM_H__ */
diff --git a/src/soc/mediatek/mt8173/mtcmos.c b/src/soc/mediatek/mt8173/mtcmos.c
index cdd31f4..00e37ed 100644
--- a/src/soc/mediatek/mt8173/mtcmos.c
+++ b/src/soc/mediatek/mt8173/mtcmos.c
@@ -13,10 +13,19 @@
  * GNU General Public License for more details.
  */
 
+#include <stddef.h>
+
 #include <arch/io.h>
 #include <soc/mtcmos.h>
 #include <soc/spm.h>
 
+struct power_domain_data {
+	void *pwr_con;
+	u32 pwr_sta_mask;
+	u32 sram_pdn_mask;
+	u32 sram_ack_mask;
+};
+
 enum {
 	SRAM_ISOINT_B	= 1U << 6,
 	SRAM_CKISO	= 1U << 5,
@@ -28,44 +37,51 @@
 };
 
 enum {
-	SRAM_PDN           = 0xf << 8,
-	DIS_SRAM_ACK       = 0x1 << 12,
-	AUD_SRAM_ACK       = 0xf << 12,
+	DISP_PWR_STA_MASK	= 0x1 << 3,
+	AUDIO_PWR_STA_MASK	= 0x1 << 24,
 };
 
-enum {
-	DIS_PWR_STA_MASK   = 0x1 << 3,
-	AUD_PWR_STA_MASK   = 0x1 << 24,
-};
-
-static void mtcmos_power_on(u32 *pwr_con, u32 pwr_sta_mask)
+static void mtcmos_power_on(const struct power_domain_data *pd)
 {
-	write32(&mt8173_spm->poweron_config_set,
+	write32(&mtk_spm->poweron_config_set,
 		(SPM_PROJECT_CODE << 16) | (1U << 0));
 
-	setbits_le32(pwr_con, PWR_ON);
-	setbits_le32(pwr_con, PWR_ON_2ND);
+	setbits_le32(pd->pwr_con, PWR_ON);
+	setbits_le32(pd->pwr_con, PWR_ON_2ND);
 
-	while (!(read32(&mt8173_spm->pwr_status) & pwr_sta_mask) ||
-	       !(read32(&mt8173_spm->pwr_status_2nd) & pwr_sta_mask))
+	while (!(read32(&mtk_spm->pwr_status) & pd->pwr_sta_mask) ||
+	       !(read32(&mtk_spm->pwr_status_2nd) & pd->pwr_sta_mask))
 		continue;
 
-	clrbits_le32(pwr_con, PWR_CLK_DIS);
-	clrbits_le32(pwr_con, PWR_ISO);
-	setbits_le32(pwr_con, PWR_RST_B);
-	clrbits_le32(pwr_con, SRAM_PDN);
-}
+	clrbits_le32(pd->pwr_con, PWR_CLK_DIS);
+	clrbits_le32(pd->pwr_con, PWR_ISO);
+	setbits_le32(pd->pwr_con, PWR_RST_B);
+	clrbits_le32(pd->pwr_con, pd->sram_pdn_mask);
 
-void mtcmos_audio_power_on(void)
-{
-	mtcmos_power_on(&mt8173_spm->audio_pwr_con, AUD_PWR_STA_MASK);
-	while (read32(&mt8173_spm->audio_pwr_con) & AUD_SRAM_ACK)
+	while (read32(pd->pwr_con) & pd->sram_ack_mask)
 		continue;
 }
 
 void mtcmos_display_power_on(void)
 {
-	mtcmos_power_on(&mt8173_spm->dis_pwr_con, DIS_PWR_STA_MASK);
-	while (read32(&mt8173_spm->dis_pwr_con) & DIS_SRAM_ACK)
-		continue;
+	static const struct power_domain_data disp = {
+		.pwr_con = &mtk_spm->dis_pwr_con,
+		.pwr_sta_mask = DISP_PWR_STA_MASK,
+		.sram_pdn_mask = DISP_SRAM_PDN_MASK,
+		.sram_ack_mask = DISP_SRAM_ACK_MASK,
+	};
+
+	mtcmos_power_on(&disp);
+}
+
+void mtcmos_audio_power_on(void)
+{
+	static const struct power_domain_data audio = {
+		.pwr_con = &mtk_spm->audio_pwr_con,
+		.pwr_sta_mask = AUDIO_PWR_STA_MASK,
+		.sram_pdn_mask = AUDIO_SRAM_PDN_MASK,
+		.sram_ack_mask = AUDIO_SRAM_ACK_MASK,
+	};
+
+	mtcmos_power_on(&audio);
 }