mb/intel/adlrvp: Add RTD3 support for PCIe slot1
Add RTD3 support for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec
BUG=none
BRANCH=firmware-brya-14505.B
TEST=Insert a SD card or NIC AIC on PCIe slot1 and run
'suspend_stress_test -c 1'. The RP8 should not cause suspend issue.
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Ieb7d207a7ec3763bad3e82522e86a825c1ed00b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70119
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb
index 2eea1e4..c78189f 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb
@@ -84,5 +84,24 @@
end
end
end
+ device ref pcie_rp8 on
+ # NOTE: requires GPP_A7 set to Native Function 1 for SRCCLK_OE7
+ register "pch_pcie_rp[PCH_RP(8)]" = "{
+ .clk_src = 7,
+ .clk_req = 7,
+ .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+ .PcieRpL1Substates = L1_SS_L1_2,
+ .pcie_rp_detect_timeout_ms = 50,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)"
+ register "enable_delay_ms" = "50"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)"
+ register "reset_off_delay_ms" = "20"
+ register "srcclk_pin" = "7"
+ device generic 0 on
+ end
+ end
+ end
end
end
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb
index 2eea1e4..c78189f 100644
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb
@@ -84,5 +84,24 @@
end
end
end
+ device ref pcie_rp8 on
+ # NOTE: requires GPP_A7 set to Native Function 1 for SRCCLK_OE7
+ register "pch_pcie_rp[PCH_RP(8)]" = "{
+ .clk_src = 7,
+ .clk_req = 7,
+ .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR,
+ .PcieRpL1Substates = L1_SS_L1_2,
+ .pcie_rp_detect_timeout_ms = 50,
+ }"
+ chip soc/intel/common/block/pcie/rtd3
+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H17)"
+ register "enable_delay_ms" = "50"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)"
+ register "reset_off_delay_ms" = "20"
+ register "srcclk_pin" = "7"
+ device generic 0 on
+ end
+ end
+ end
end
end