soc/intel/apollolake: Add the remaining CSE Firmware Status Registers
Add the Shadow Registers from 2 through 5 and print information
from them accordingly. All values were taken from Intel document
number 571993.
Tested on the StarLite Mk III and the correct values are
shown:
[DEBUG] CSE: IBB Verification Result: PASS
[DEBUG] CSE: IBB Verification Done : YES
[DEBUG] CSE: Actual IBB Size : 88
[DEBUG] CSE: Verified Boot Valid : FAIL
[DEBUG] CSE: Verified Boot Test : NO
[DEBUG] CSE: FPF status : FUSED
Please note, the values shown are in an error state.
This replaces the Fuse check that is done via Heci, as this will only
work whilst the CSE is in a normal state.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8a9e7b329010fae1a2ed9c3fefc9765e617cdfe4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c
index 8473d20..01c4c47 100644
--- a/src/soc/intel/apollolake/cse.c
+++ b/src/soc/intel/apollolake/cse.c
@@ -158,16 +158,21 @@
static void dump_cse_state(void)
{
union cse_fwsts1 fwsts1;
+ union cse_fwsts2 fwsts2;
+ union cse_fwsts3 fwsts3;
+ union cse_fwsts4 fwsts4;
+ union cse_fwsts5 fwsts5;
+ union cse_fwsts6 fwsts6;
if (!is_cse_enabled())
return;
fwsts1.data = dump_status(1, PCI_ME_HFSTS1);
- dump_status(2, PCI_ME_HFSTS2);
- dump_status(3, PCI_ME_HFSTS3);
- dump_status(4, PCI_ME_HFSTS4);
- dump_status(5, PCI_ME_HFSTS5);
- dump_status(6, PCI_ME_HFSTS6);
+ fwsts2.data = dump_status(2, PCI_ME_HFSTS2);
+ fwsts3.data = dump_status(3, PCI_ME_HFSTS3);
+ fwsts4.data = dump_status(4, PCI_ME_HFSTS4);
+ fwsts5.data = dump_status(5, PCI_ME_HFSTS5);
+ fwsts6.data = dump_status(6, PCI_ME_HFSTS6);
printk(BIOS_DEBUG, "CSE: Working State : %u\n",
fwsts1.fields.working_state);
@@ -181,20 +186,20 @@
fwsts1.fields.error_code);
printk(BIOS_DEBUG, "CSE: Operation Mode : %u\n",
fwsts1.fields.operation_mode);
-
- printk(BIOS_DEBUG, "CSE: FPF status : ");
- switch (g_fuse_state) {
- case FUSE_FLASH_UNFUSED:
- printk(BIOS_DEBUG, "unfused");
- break;
- case FUSE_FLASH_FUSED:
- printk(BIOS_DEBUG, "fused");
- break;
- default:
- case FUSE_FLASH_UNKNOWN:
- printk(BIOS_DEBUG, "unknown");
- }
- printk(BIOS_DEBUG, "\n");
+ printk(BIOS_DEBUG, "CSE: IBB Verification Result: %s\n",
+ fwsts3.fields.ibb_verif_result ? "PASS" : "FAIL");
+ printk(BIOS_DEBUG, "CSE: IBB Verification Done : %s\n",
+ fwsts3.fields.ibb_verif_done ? "YES" : "NO");
+ printk(BIOS_DEBUG, "CSE: Actual IBB Size : %u\n",
+ fwsts3.fields.ibb_size);
+ printk(BIOS_DEBUG, "CSE: Verified Boot Valid : %s\n",
+ fwsts4.fields.txe_veri_boot_valid ? "PASS" : "FAIL");
+ printk(BIOS_DEBUG, "CSE: Verified Boot Test : %s\n",
+ fwsts4.fields.txe_veri_boot_test ? "YES" : "NO");
+ printk(BIOS_DEBUG, "CSE: FPF status : %s\n",
+ fwsts6.fields.fpf_commited ? "FUSED" : "UNFUSED");
+ printk(BIOS_DEBUG, "CSE: Error Status Code : %u\n",
+ fwsts5.fields.error_status_code);
}
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
diff --git a/src/soc/intel/apollolake/include/soc/cse.h b/src/soc/intel/apollolake/include/soc/cse.h
index b3f5881..6fb70af 100644
--- a/src/soc/intel/apollolake/include/soc/cse.h
+++ b/src/soc/intel/apollolake/include/soc/cse.h
@@ -23,25 +23,10 @@
} __packed fields;
};
-
-/* Miscellaneous Shadow Register 1 */
+/* General Status Shadow Register 1 */
union cse_fwsts2 {
uint32_t data;
struct {
- uint32_t cse_uma_size: 6;
- uint32_t reserved1: 8;
- uint32_t reserved2: 2;
- uint32_t cse_uma_size_valid: 1;
- uint32_t reserved3: 8;
- uint32_t reserved4: 6;
- uint32_t misc_shadow_valid: 1;
- } __packed fields;
-};
-
-/* General Status Shadow Register */
-union cse_fwsts3 {
- uint32_t data;
- struct {
uint32_t bist_in_progress: 1;
uint32_t icc_prog_sts: 2;
uint32_t invoke_mebx: 1;
@@ -61,4 +46,71 @@
} __packed fields;
};
+/* General Status Shadow Register 2 */
+union cse_fwsts3 {
+ uint32_t data;
+ struct {
+ uint32_t chunk_0: 1;
+ uint32_t chunk_1: 1;
+ uint32_t chunk_2: 1;
+ uint32_t chunk_3: 1;
+ uint32_t reserved1: 5;
+ uint32_t ibb_verif_result: 1;
+ uint32_t ibb_verif_done: 1;
+ uint32_t reserved2: 3;
+ uint32_t ibb_size: 14;
+ uint32_t no_of_chunks: 2;
+ uint32_t reserved: 2;
+ } __packed fields;
+};
+
+/* General Status Shadow Register 3 */
+union cse_fwsts4 {
+ uint32_t data;
+ struct {
+ uint32_t reserved1: 10;
+ uint32_t reserved2: 1;
+ uint32_t reserved3: 1;
+ uint32_t tpm_disconnected: 1;
+ uint32_t reserved4: 1;
+ uint32_t txe_veri_boot_valid: 1;
+ uint32_t txe_veri_boot_test: 1;
+ uint32_t reserved5: 16;
+ } __packed fields;
+};
+
+/* General Status Shadow Register 4 */
+union cse_fwsts5 {
+ uint32_t data;
+ struct {
+ uint32_t reserved1: 3;
+ uint32_t error_status_code: 5;
+ uint32_t reserved2: 24;
+ } __packed fields;
+};
+
+/* General Status Shadow Register 5 */
+union cse_fwsts6 {
+ uint32_t data;
+ struct {
+ uint32_t reserved1: 30;
+ uint32_t fpf_commited: 1;
+ uint32_t reserved2: 1;
+ } __packed fields;
+};
+
+/* Miscellaneous Shadow Register 1 */
+union cse_fwsts7 {
+ uint32_t data;
+ struct {
+ uint32_t cse_uma_size: 6;
+ uint32_t reserved1: 8;
+ uint32_t reserved2: 2;
+ uint32_t cse_uma_size_valid: 1;
+ uint32_t reserved3: 8;
+ uint32_t reserved4: 6;
+ uint32_t misc_shadow_valid: 1;
+ } __packed fields;
+};
+
#endif /* _APOLLOLAKE_CSE_H_ */