diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index c3d9a10..8cf2e7c 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -19,7 +19,7 @@
 
 	enable_lapic();
 
-	wake_from_s3 = early_pch_init(params->gpio_map);
+	wake_from_s3 = early_pch_init();
 
 	/* Perform some early chipset initialization required
 	 * before RAM initialization can work