commit | bee4bb5f0d157bc360aaf5d70d7ac2b91b18af48 | [log] [tgz] |
---|---|---|
author | Subrata Banik <subrata.banik@intel.com> | Tue Sep 21 21:00:16 2021 +0530 |
committer | Subrata Banik <subrata.banik@intel.com> | Thu Sep 30 07:08:03 2021 +0000 |
tree | cda73ae240bef70ce992c619caccbae909dc1417 | |
parent | a834a6eede3065b954f8bebcc77bd2df557b4a18 [diff] |
soc/intel/common/cse: Late sending EOP msg if !HECI_DISABLE_USING_SMM Pushing EOP msg post FSP notify helps to save ~30ms+ boot time across various warm reboots. This patch ensures late sending EOP msg when function disabling of CSE is no longer a requirement. BUG=b:200644229 TEST=Able to save ~30ms+ of boot time Without this code change EOP sending timestamp as below: 943:after sending EOP to ME 1,248,328(61,954)) With this code change EOP sending timestamp as below: 943:after sending EOP to ME 1,231,660 (2,754) Change-Id: I2b78a1c07803aacfb34dce9e94b2a05a2491aabc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.