drivers/pc80/mc146818rtc: Assume we always have ALTCENTURY
This patch has a rather twisted history. It was originally split off
from a chromium patch, which moved ALTCENTURY to Kconfig. However,
since we have no user without ALTCENTURY, we've agreed that the best
way to proceed is to eliminate the non-ALTCENTURY case entirely.
The old commit message and identifiers are kept below for reference:
The availability of "ALTCENTURY" is now set through a kconfig
variable so it can be available to the RTC driver without having to have a
specialized interface.
BUG=None
TEST=Built and booted on Link with the event log code modified to use the RTC
interface. Verified that the event times were accurate.
BRANCH=nyan
Original-Change-Id: Ifa807898e583254e57167fd44932ea86627a02ee
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197795
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
This is the second half the following patch.
(cherry picked from commit 9e0fd75142d29afe34f6c6b9ce0099f478ca5a93)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8e871f31c3d4be7676abf9454ca90808d1ddca03
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7987
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
diff --git a/src/southbridge/amd/agesa/hudson/lpc.c b/src/southbridge/amd/agesa/hudson/lpc.c
index 836966e..b784fc4 100644
--- a/src/southbridge/amd/agesa/hudson/lpc.c
+++ b/src/southbridge/amd/agesa/hudson/lpc.c
@@ -71,7 +71,7 @@
byte |= 1 << 0 | 1 << 3;
pci_write_config8(dev, 0xBB, byte);
- cmos_check_update_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date();
/* Initialize the real time clock.
* The 0 argument tells cmos_init not to
diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c
index 9c70482..3fa6940 100644
--- a/src/southbridge/amd/cimx/sb700/late.c
+++ b/src/southbridge/amd/cimx/sb700/late.c
@@ -81,7 +81,7 @@
{
printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - Start.\n");
- cmos_check_update_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date();
/* Initialize the real time clock.
* The 0 argument tells cmos_init not to
diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c
index 9c4047f..d7f22d3 100644
--- a/src/southbridge/amd/cimx/sb800/late.c
+++ b/src/southbridge/amd/cimx/sb800/late.c
@@ -132,7 +132,7 @@
{
printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - Start.\n");
- cmos_check_update_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date();
/* Initialize the real time clock.
* The 0 argument tells cmos_init not to
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c
index 6f6a501..e9f5ad6 100644
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -103,7 +103,7 @@
printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n");
/* SB Configure HPET base and enable bit */
//- hpetInit(sb_config, &(sb_config->BuildParameters));
- cmos_check_update_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date();
/* Initialize the real time clock.
* The 0 argument tells cmos_init not to
diff --git a/src/southbridge/amd/pi/avalon/lpc.c b/src/southbridge/amd/pi/avalon/lpc.c
index 1f60bc4..7b54cc3 100644
--- a/src/southbridge/amd/pi/avalon/lpc.c
+++ b/src/southbridge/amd/pi/avalon/lpc.c
@@ -70,7 +70,7 @@
byte |= 1 << 0 | 1 << 3;
pci_write_config8(dev, 0xBB, byte);
- cmos_check_update_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date();
/* Initialize the real time clock.
* The 0 argument tells cmos_init not to
diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c
index acee69d..dc2f31b 100644
--- a/src/southbridge/amd/sb600/lpc.c
+++ b/src/southbridge/amd/sb600/lpc.c
@@ -63,7 +63,7 @@
byte &= ~(1 << 1);
pci_write_config8(dev, 0x78, byte);
- cmos_check_update_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date();
}
static void sb600_lpc_read_resources(device_t dev)
diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c
index 26478b7..8ebc765 100644
--- a/src/southbridge/amd/sb700/lpc.c
+++ b/src/southbridge/amd/sb700/lpc.c
@@ -90,7 +90,7 @@
}
#endif
- cmos_check_update_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date();
}
void backup_top_of_ram(uint64_t ramtop)
diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c
index f862a97..87c09a2 100644
--- a/src/southbridge/amd/sb800/lpc.c
+++ b/src/southbridge/amd/sb800/lpc.c
@@ -74,7 +74,7 @@
byte |= 1 << 0 | 1 << 3;
pci_write_config8(dev, 0xBB, byte);
- cmos_check_update_date(RTC_HAS_ALTCENTURY);
+ cmos_check_update_date();
}
static void sb800_lpc_read_resources(device_t dev)