soc/amd/picasso: factor out AOAC offset defines
Factoring out those defines allows using them easily in the ACPI code
without having to use preprocessor macros.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I99cb03de8782a0eeeb505f567b982099b0e8a18d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/soc/amd/picasso/aoac.c b/src/soc/amd/picasso/aoac.c
index aed6d74..13d6be4 100644
--- a/src/soc/amd/picasso/aoac.c
+++ b/src/soc/amd/picasso/aoac.c
@@ -3,6 +3,7 @@
#include <stdint.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/aoac.h>
+#include <soc/aoac_defs.h>
#include <soc/southbridge.h>
#include <delay.h>
diff --git a/src/soc/amd/picasso/include/soc/aoac_defs.h b/src/soc/amd/picasso/include/soc/aoac_defs.h
new file mode 100644
index 0000000..cc34403
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/aoac_defs.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_PICASSO_AOAC_DEFS_H
+#define AMD_PICASSO_AOAC_DEFS_H
+
+/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
+#define FCH_AOAC_DEV_CLK_GEN 0
+#define FCH_AOAC_DEV_I2C2 7
+#define FCH_AOAC_DEV_I2C3 8
+#define FCH_AOAC_DEV_I2C4 9
+#define FCH_AOAC_DEV_UART0 11
+#define FCH_AOAC_DEV_UART1 12
+#define FCH_AOAC_DEV_UART2 16
+#define FCH_AOAC_DEV_AMBA 17
+#define FCH_AOAC_DEV_UART3 26
+#define FCH_AOAC_DEV_ESPI 27
+#define FCH_AOAC_DEV_EMMC 28
+
+#endif /* AMD_PICASSO_AOAC_DEFS_H */
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index e9d891c..1a0456d 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -119,19 +119,6 @@
#define I2C_PAD_CTRL_SPARE0 BIT(17)
#define I2C_PAD_CTRL_SPARE1 BIT(18)
-/* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
-#define FCH_AOAC_DEV_CLK_GEN 0
-#define FCH_AOAC_DEV_I2C2 7
-#define FCH_AOAC_DEV_I2C3 8
-#define FCH_AOAC_DEV_I2C4 9
-#define FCH_AOAC_DEV_UART0 11
-#define FCH_AOAC_DEV_UART1 12
-#define FCH_AOAC_DEV_UART2 16
-#define FCH_AOAC_DEV_AMBA 17
-#define FCH_AOAC_DEV_UART3 26
-#define FCH_AOAC_DEV_ESPI 27
-#define FCH_AOAC_DEV_EMMC 28
-
#define FCH_LEGACY_UART_DECODE (ALINK_AHB_ADDRESS + 0x20) /* 0xfedc0020 */
/* SATA Controller D11F0 */
diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c
index 2767817..faaa3f3 100644
--- a/src/soc/amd/picasso/uart.c
+++ b/src/soc/amd/picasso/uart.c
@@ -7,6 +7,7 @@
#include <amdblocks/gpio_banks.h>
#include <amdblocks/aoac.h>
#include <amdblocks/uart.h>
+#include <soc/aoac_defs.h>
#include <soc/southbridge.h>
#include <soc/gpio.h>
#include <soc/uart.h>