mb/emulation/spike-riscv: Update UART address

I updated my spike patch[1] to cleanly apply to current spike master.
As a side effect, the UART is now at 0x02100000.

[1]: https://github.com/riscv/riscv-isa-sim/pull/53

Change-Id: I4cb09014619e230011486fa57636abe183baa4be
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/20126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
1 file changed