commit 033aa0dfc3e6c2478b6e21a75c751293ddeb6d35
author Furquan Shaikh <furquan@google.com> Sat May 09 14:26:37 2020 -0700
committer Furquan Shaikh <furquan@google.com> Tue May 12 20:04:24 2020 +0000
tree 1cb778caa063f7680cd081a065fd185108d78b6a
parent 08c524c0b7266fd9f51e0d412bdac2b4d14c09e0

soc/amd/picasso: Add support for using common SoC configuration

This change adds support for using common SoC configuration by adding
soc_amd_common_config to soc_amd_picasso_config and helper function to
return pointer to the structure to amd common block code.

Change-Id: I8bd4eac3b19c9ded2d9a3e95ac077f014730f9d1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/amd/picasso/Makefile.inc

diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc
index 0e54661..43bb32e 100644
--- a/src/soc/amd/picasso/Makefile.inc
+++ b/src/soc/amd/picasso/Makefile.inc
@@ -18,6 +18,7 @@
 bootblock-y += tsc_freq.c
 bootblock-y += gpio.c
 bootblock-y += smi_util.c
+bootblock-y += config.c
 
 romstage-y += i2c.c
 romstage-y += romstage.c
@@ -31,10 +32,12 @@
 romstage-y += soc_util.c
 romstage-y += psp.c
 romstage-y += mtrr.c
+romstage-y += config.c
 
 verstage-y += gpio.c
 verstage-y += i2c.c
 verstage-y += pmutil.c
+verstage-y += config.c
 verstage-$(CONFIG_PICASSO_UART) += uart.c
 verstage-y += tsc_freq.c
 
@@ -59,6 +62,7 @@
 ramstage-y += soc_util.c
 ramstage-y += psp.c
 ramstage-y += fsp_params.c
+ramstage-y += config.c
 
 all-y += reset.c
 
@@ -68,6 +72,7 @@
 smm-$(CONFIG_DEBUG_SMI) += uart.c
 smm-y += gpio.c
 smm-y += psp.c
+smm-y += config.c
 
 CPPFLAGS_common += -I$(src)/soc/amd/picasso
 CPPFLAGS_common += -I$(src)/soc/amd/picasso/include

src/soc/amd/picasso/chip.h

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 9b77e84..2b9ef3c 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -5,6 +5,7 @@
 
 #include <stddef.h>
 #include <stdint.h>
+#include <amdblocks/chip.h>
 #include <commonlib/helpers.h>
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <soc/i2c.h>
@@ -13,6 +14,7 @@
 #include <acpi/acpi_device.h>
 
 struct soc_amd_picasso_config {
+	struct soc_amd_common_config common_config;
 	/*
 	 * If sb_reset_i2c_slaves() is called, this devicetree register
 	 * defines which I2C SCL will be toggled 9 times at 100 KHz.

src/soc/amd/picasso/config.c

diff --git a/src/soc/amd/picasso/config.c b/src/soc/amd/picasso/config.c
new file mode 100644
index 0000000..5d52e7a
--- /dev/null
+++ b/src/soc/amd/picasso/config.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <amdblocks/chip.h>
+#include <device/device.h>
+#include "chip.h"
+
+const struct soc_amd_common_config *soc_get_common_config()
+{
+	const struct soc_amd_picasso_config *cfg = config_of_soc();
+	return &cfg->common_config;
+}