soc/intel/broadwell: Add missing resources in ASL
Taken from Haswell code. These resources also exist on Broadwell and
should be reported to the OS.
Change-Id: I45f2a6a9140d72c1cc2ee8b72621dc16c815b621
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/soc/intel/broadwell/acpi/hostbridge.asl b/src/soc/intel/broadwell/acpi/hostbridge.asl
index c0a3c7d..cf8a6ce 100644
--- a/src/soc/intel/broadwell/acpi/hostbridge.asl
+++ b/src/soc/intel/broadwell/acpi/hostbridge.asl
@@ -179,6 +179,9 @@
Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
+ Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT
+ Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM
+ Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
Memory32Fixed (ReadWrite, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE)
Memory32Fixed (ReadWrite, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE)
})