mb/msi/ms7d25: Add correct memory init configuration
Tested with 4x KINGSTON KF3600C17D4/8GX DIMMs.
TEST=Include the microcode from vendor firmware and FSP blob from
Intel R&DC. Boot the platform and see ramstage is executing.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I98b9c77d791d18640cb05c133cb0bf14ad22dcdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c
index 210af05..60f2371 100644
--- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c
+++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c
@@ -9,18 +9,13 @@
static const struct mb_cfg ddr4_mem_config = {
.type = MEM_TYPE_DDR4,
- .rcomp = {
- /* Baseboard uses only 100ohm Rcomp resistor FIXME */
- .resistor = 100,
-
- /* Baseboard Rcomp target values FIXME */
- .targets = { 50, 20, 25, 25, 25 },
- },
+ /* According to DOC #573387 rcomp values no longer have to be provided */
+ /* DDR DIMM configuration does not need to set DQ/DQS maps */
.UserBd = BOARD_TYPE_DESKTOP_2DPC, /* FIXME */
.ddr_config = {
- .dq_pins_interleaved = false, /* FIXME */
+ .dq_pins_interleaved = true,
},
};