amd/cezanne: Add slow_ppt_time & thermctl_limit to UPD
These values will be added in the upcoming STAPM configuration update.
BUG=b:185209734
TEST=Build & Boot guybrush
Cq-Depend: chrome-internal:3780259
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I2a6835c16badfe505e3c33b356ca671766cd6972
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h
index 7753ab8..4c5118e 100644
--- a/src/soc/amd/cezanne/chip.h
+++ b/src/soc/amd/cezanne/chip.h
@@ -55,6 +55,8 @@
uint32_t sustained_power_limit;
uint32_t fast_ppt_limit;
uint32_t slow_ppt_limit;
+ uint32_t slow_ppt_time_constant_s;
+ uint32_t thermctl_limit_degreeC;
uint8_t smartshift_enable;
diff --git a/src/soc/amd/cezanne/fsp_m_params.c b/src/soc/amd/cezanne/fsp_m_params.c
index a83b8b2..964ec18 100644
--- a/src/soc/amd/cezanne/fsp_m_params.c
+++ b/src/soc/amd/cezanne/fsp_m_params.c
@@ -98,6 +98,8 @@
mcfg->sustained_power_limit = config->sustained_power_limit;
mcfg->fast_ppt_limit = config->fast_ppt_limit;
mcfg->slow_ppt_limit = config->slow_ppt_limit;
+ mcfg->slow_ppt_time_constant = config->slow_ppt_time_constant_s;
+ mcfg->thermctl_limit = config->thermctl_limit_degreeC;
/* 0 is default */
mcfg->smartshift_enable = config->smartshift_enable;
diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
index dd59d52..6e9a1f0 100644
--- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
+++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h
@@ -65,7 +65,9 @@
/** Offset 0x0405**/ uint8_t cppc_preferred_cores;
/** Offset 0x0406**/ uint8_t stapm_boost;
/** Offset 0x0407**/ uint32_t stapm_time_constant;
- /** Offset 0x040B**/ uint8_t smu_soc_tuning_reserved[17];
+ /** Offset 0x040B**/ uint32_t slow_ppt_time_constant;
+ /** Offset 0x040F**/ uint32_t thermctl_limit;
+ /** Offset 0x0413**/ uint8_t smu_soc_tuning_reserved[9];
/** Offset 0x041C**/ uint8_t iommu_support;
/** Offset 0x041D**/ uint8_t pspp_policy;
/** Offset 0x041E**/ uint8_t enable_nb_azalia;