commit 027f86e6af023b338a0f1d8a999a8f33eeacb010
author Kyösti Mälkki <kyosti.malkki@gmail.com> Fri Dec 02 15:30:10 2022 +0200
committer Kyösti Mälkki <kyosti.malkki@gmail.com> Wed Aug 16 17:55:02 2023 +0000
tree 691450089ec0116cba1ec04b1b73ca3dea39aaf5
parent 4a9de553c5307595f396b47aaa108bf1dc34638d

ACPI: Add usb_charge_mode_from_gnvs()

Early Chromebook generations stored the information about
USB port power control for S3/S5 sleepstates in GNVS, although
the configuration is static.

Reduce code duplication and react to ACPI S4 as if it was ACPI
S5 request.

Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>

src/mainboard/google/auron/Kconfig

diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig
index f503d46..e7ba578 100644
--- a/src/mainboard/google/auron/Kconfig
+++ b/src/mainboard/google/auron/Kconfig
@@ -1,5 +1,6 @@
 config BOARD_GOOGLE_BASEBOARD_AURON
 	def_bool n
+	select ACPI_GNVS_USB_CHARGECTL
 	select BOARD_ROMSIZE_KB_8192
 	select BROADWELL_LPDDR3 if BOARD_GOOGLE_SAMUS
 	select EC_GOOGLE_CHROMEEC

src/mainboard/google/auron/acpi_tables.c

diff --git a/src/mainboard/google/auron/acpi_tables.c b/src/mainboard/google/auron/acpi_tables.c
index 501f54b..048de76 100644
--- a/src/mainboard/google/auron/acpi_tables.c
+++ b/src/mainboard/google/auron/acpi_tables.c
@@ -10,9 +10,7 @@
 {
 	/* Enable USB ports in S3 */
 	gnvs->s3u0 = 1;
-
-	/* Disable USB ports in S5 */
-	gnvs->s5u0 = 0;
+	gnvs->s3u1 = gnvs->s3u0;
 
 	gnvs->tmps = CTL_TDP_SENSOR_ID;
 	gnvs->tcrt = CRITICAL_TEMPERATURE;

src/mainboard/google/auron/smihandler.c

diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c
index 237a2b3..0fc3588 100644
--- a/src/mainboard/google/auron/smihandler.c
+++ b/src/mainboard/google/auron/smihandler.c
@@ -8,7 +8,6 @@
 #include <ec/google/chromeec/smm.h>
 #include <southbridge/intel/lynxpoint/lp_gpio.h>
 #include <soc/iomap.h>
-#include <soc/nvs.h>
 #include "ec.h"
 #include <variant/onboard.h>
 
@@ -36,28 +35,17 @@
 void mainboard_smi_sleep(u8 slp_typ)
 {
 	/* Disable USB charging if required */
+	/* NOTE: Setting of usb0 _may_ also control usb1 here. */
+	chromeec_set_usb_charge_mode(slp_typ);
+
 	switch (slp_typ) {
 	case ACPI_S3:
-		if (gnvs->s3u0 == 0) {
-			google_chromeec_set_usb_charge_mode(
-				0, USB_CHARGE_MODE_DISABLED);
-			google_chromeec_set_usb_charge_mode(
-				1, USB_CHARGE_MODE_DISABLED);
-		}
-
 		mainboard_disable_gpios();
 
 		/* Enable wake events */
 		google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
 		break;
 	case ACPI_S5:
-		if (gnvs->s5u0 == 0) {
-			google_chromeec_set_usb_charge_mode(
-				0, USB_CHARGE_MODE_DISABLED);
-			google_chromeec_set_usb_charge_mode(
-				1, USB_CHARGE_MODE_DISABLED);
-		}
-
 		mainboard_disable_gpios();
 
 		/* Enable wake events */