diff --git a/src/Kconfig b/src/Kconfig
index c282d21..91a3b29f 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -332,8 +332,31 @@
 
 source "src/acpi/Kconfig"
 
+menu "Mainboard"
+
 source "src/mainboard/Kconfig"
 
+config CBFS_SIZE
+	hex "Size of CBFS filesystem in ROM"
+	default 0x100000 if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE || \
+	  NORTHBRIDGE_INTEL_IVYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE || \
+	  NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || \
+	  NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_HASWELL || \
+	  NORTHBRIDGE_INTEL_NEHALEM || SOC_INTEL_BAYTRAIL || SOC_INTEL_BRASWELL || \
+	  SOC_INTEL_BROADWELL
+	default 0x200000 if SOC_INTEL_FSP_BAYTRAIL
+	default ROM_SIZE
+	help
+	  This is the part of the ROM actually managed by CBFS, located at the
+	  end of the ROM (passed through cbfstool -o) on x86 and at at the start
+	  of the ROM (passed through cbfstool -s) everywhere else. It defaults
+	  to span the whole ROM on all but Intel systems that use an Intel Firmware
+	  Descriptor.  It can be overridden to make coreboot live alongside other
+	  components like ChromeOS's vboot/FMAP or Intel's IFD / ME / TXE
+	  binaries.
+
+endmenu
+
 config SYSTEM_TYPE_LAPTOP
 	default n
 	bool
@@ -482,16 +505,6 @@
 	bool
 	default n
 
-config CBFS_SIZE
-	hex "Size of CBFS filesystem in ROM"
-	default ROM_SIZE
-	help
-	  This is the part of the ROM actually managed by CBFS, located at the
-	  end of the ROM (passed through cbfstool -o) on x86 and at at the start
-	  of the ROM (passed through cbfstool -s) everywhere else. Defaults to
-	  span the whole ROM but can be overwritten to make coreboot live
-	  alongside other components (like ChromeOS's vboot/FMAP).
-
 config CACHE_ROM_SIZE_OVERRIDE
 	hex
 	default 0
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index d7cdc3d..ab8ee26 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -1,5 +1,3 @@
-menu "Mainboard"
-
 choice
 	prompt "Mainboard vendor"
 	default VENDOR_EMULATION
@@ -147,5 +145,3 @@
 config ENABLE_POWER_BUTTON
 	def_bool y if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_ENABLE
 	def_bool n if !POWER_BUTTON_IS_OPTIONAL && POWER_BUTTON_FORCE_DISABLE
-
-endmenu
diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig
index 21d3f65..e1f2e88 100644
--- a/src/northbridge/intel/fsp_sandybridge/Kconfig
+++ b/src/northbridge/intel/fsp_sandybridge/Kconfig
@@ -40,17 +40,6 @@
 	  0x80860102, 0x8086010a, 0x80860112, 0x80860116
 	  0x80860122, 0x80860126, 0x80860166
 
-config CBFS_SIZE
-	hex "Size of CBFS filesystem in ROM"
-	default 0x100000
-	help
-	  On Sandybridge and Ivybridge systems the firmware image may
-	  have to store a lot more than just coreboot, including:
-	   - a firmware descriptor
-	   - Intel Management Engine firmware
-	  This option specifies the maximum size of the CBFS portion in the
-	  firmware image.
-
 # Ivybridge Specific FSP Kconfig
 source src/northbridge/intel/fsp_sandybridge/fsp/Kconfig
 
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 9564ea6..2374a1f 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -36,17 +36,6 @@
 	string
 	default "northbridge/intel/gm45/bootblock.c"
 
-config CBFS_SIZE
-	hex "Size of CBFS filesystem in ROM"
-	default 0x100000
-	help
-	  On GM45 systems the firmware image may
-	  store a lot more than just coreboot, including:
-	   - a firmware descriptor
-	   - Intel Management Engine firmware
-	  This option allows to limit the size of the CBFS portion in the
-	  firmware image.
-
 config VGA_BIOS_ID
 	string
 	default "8086,2a42"
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index e51ac3c..c5b8088 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -88,18 +88,6 @@
 	  The path and filename of the file to use as System Agent
 	  binary.
 
-config CBFS_SIZE
-	hex "Size of CBFS filesystem in ROM"
-	default 0x100000
-	help
-	  On Haswell systems the firmware image has to store a lot more
-	  than just coreboot, including:
-	   - a firmware descriptor
-	   - Intel Management Engine firmware
-	   - MRC cache information
-	  This option allows to limit the size of the CBFS portion in the
-	  firmware image.
-
 config PRE_GRAPHICS_DELAY
 	int "Graphics initialization delay in ms"
 	default 0
diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig
index 17c94b6..f115d97 100644
--- a/src/northbridge/intel/nehalem/Kconfig
+++ b/src/northbridge/intel/nehalem/Kconfig
@@ -49,15 +49,4 @@
 	hex
 	default 0x10000
 
-config CBFS_SIZE
-	hex "Size of CBFS filesystem in ROM"
-	default 0x100000
-	help
-	  On Nehalem systems the firmware image has to
-	  store a lot more than just coreboot, including:
-	   - a firmware descriptor
-	   - Intel Management Engine firmware
-	  This option allows to limit the size of the CBFS portion in the
-	  firmware image.
-
 endif
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 7eb6948..4dede09 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -110,16 +110,4 @@
 	  The path and filename of the file to use as System Agent
 	  binary.
 
-config CBFS_SIZE
-	hex "Size of CBFS filesystem in ROM"
-	default 0x100000
-	help
-	  On Sandybridge and Ivybridge systems the firmware image has to
-	  store a lot more than just coreboot, including:
-	   - a firmware descriptor
-	   - Intel Management Engine firmware
-	   - MRC cache information
-	  This option allows to limit the size of the CBFS portion in the
-	  firmware image.
-
 endif
diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig
index 5060e45..032a60e 100644
--- a/src/soc/intel/baytrail/Kconfig
+++ b/src/soc/intel/baytrail/Kconfig
@@ -146,18 +146,6 @@
 	  the system will reset otherwise the ramstage will be reloaded from
 	  cbfs.
 
-config CBFS_SIZE
-	hex "Size of CBFS filesystem in ROM"
-	default 0x100000
-	help
-	  On Bay Trail systems the firmware image has to store a lot more
-	  than just coreboot, including:
-	   - a firmware descriptor
-	   - Intel Management Engine firmware
-	   - MRC cache information
-	  This option allows to limit the size of the CBFS portion in the
-	  firmware image.
-
 config ENABLE_BUILTIN_COM1
 	bool "Enable builtin COM1 Serial Port"
 	default n
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index aa191b3..20abff5 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -147,18 +147,6 @@
 	  the system will reset otherwise the ramstage will be reloaded from
 	  cbfs.
 
-config CBFS_SIZE
-	hex "Size of CBFS filesystem in ROM"
-	default 0x100000
-	help
-	  On Bay Trail systems the firmware image has to store a lot more
-	  than just coreboot, including:
-	   - a firmware descriptor
-	   - Intel Management Engine firmware
-	   - MRC cache information
-	  This option allows to limit the size of the CBFS portion in the
-	  firmware image.
-
 config ENABLE_BUILTIN_COM1
 	bool "Enable builtin COM1 Serial Port"
 	default n
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index b584c0e..3c8b64b 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -140,17 +140,6 @@
 
 endif # HAVE_MRC
 
-config CBFS_SIZE
-	hex "Size of CBFS filesystem in ROM"
-	default 0x100000
-	help
-	  The firmware image has to store more than just coreboot, including:
-	   - a firmware descriptor
-	   - Intel Management Engine firmware
-	   - MRC cache information
-	  This option allows to limit the size of the CBFS portion in the
-	  firmware image.
-
 config PRE_GRAPHICS_DELAY
 	int "Graphics initialization delay in ms"
 	default 0
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index 371ad52..765c57f 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -95,17 +95,6 @@
 	hex
 	default 0xfff10040
 
-config CBFS_SIZE
-	hex
-	default 0x200000
-	help
-	  On Bay Trail systems the firmware image has to store a lot more
-	  than just coreboot, including:
-	   - a firmware descriptor
-	   - Intel Trusted Execution Engine firmware
-	  This option specifies the maximum size of the CBFS portion in the
-	  firmware image.
-
 config INCLUDE_ME
 	bool "Include the TXE"
 	default n
diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig
index f07d97b..7f8937c 100644
--- a/src/soc/qualcomm/ipq806x/Kconfig
+++ b/src/soc/qualcomm/ipq806x/Kconfig
@@ -13,14 +13,6 @@
 
 if SOC_QC_IPQ806X
 
-config CBFS_SIZE
-	hex "Size of CBFS filesystem in ROM"
-	default ROM_SIZE
-	help
-	  CBFS size needs to match the size of memory allocated to the
-	  coreboot blob elsewhere in the system. Make sure this config option
-	  is fine tuned in the board config file.
-
 config MBN_ENCAPSULATION
 	depends on USE_BLOBS
 	bool "bootblock encapsulation for ipq8064"