tree f6019ebb72abe3760d36dedefa801de55b23a0a7
parent 52ac424b9cd2fa7ea7c3e4de90c847b22c1aee4b
author Joey Peng <joey.peng@lcfc.corp-partner.google.com> 1642491032 +0800
committer Felix Held <felix-coreboot@felixheld.de> 1643133885 +0000

mb/google/brya/var/taniks: Run time probe for NVMe SSD and MMC

Taniks will use two PCIE port signals with one slot, one CLK and one
CLKREQ at next build. In order to accommodate this, probe statements
are added to the devicetree. This only affects NVME SSD and EMMC.

BUG=b:215040000
TEST=Build FSP with debug output enabled, and observe the correct root
ports being initialized depending on the FW_CONFIG values for BOOT_EMMC
and BOOT_NVME.

Cq-Depend:chromium:3397561
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I2ead505088f19fd3bf9768b541838395c82ef051
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>