ec/google/chromeec: clang-format ec_commands.h
This is a format-only change: Reformat ec_commands.h using clang-format
according to the EC repo's current formatting style.
The command is:
clang-format --style=file:$EC/.clang-format -i ec_commands.h
where $EC points to the chromeos EC repo.
The EC repo has recently adpoted the practice of formatting all files
through clang-format using its own style. So, run ec_commands.h through
the EC's clang-format so future updates don't get overwhelmed by
inconsequential style changes.
BUG=b:258110734
BRANCH=none
TEST=built coreboot for brya
Change-Id: Icbd6d00922dc5fd4c44ee109d54cea612e15db06
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
index 7b1eeb2..300ca13 100644
--- a/src/ec/google/chromeec/ec_commands.h
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -29,7 +29,7 @@
#ifndef BUILD_ASSERT
#define BUILD_ASSERT(_cond)
#endif /* !BUILD_ASSERT */
-#endif /* CHROMIUM_EC */
+#endif /* CHROMIUM_EC */
#ifdef __KERNEL__
#include <linux/limits.h>
@@ -42,11 +42,11 @@
*/
#ifndef BIT
-#define BIT(nr) (1UL << (nr))
+#define BIT(nr) (1UL << (nr))
#endif
#ifndef BIT_ULL
-#define BIT_ULL(nr) (1ULL << (nr))
+#define BIT_ULL(nr) (1ULL << (nr))
#endif
/*
@@ -64,7 +64,7 @@
#endif
#endif
-#endif /* __KERNEL__ */
+#endif /* __KERNEL__ */
#ifdef __cplusplus
extern "C" {
@@ -77,28 +77,29 @@
* determined in other ways. Remove this once the kernel code no longer
* depends on it.
*/
-#define EC_PROTO_VERSION 0x00000002
+#define EC_PROTO_VERSION 0x00000002
/* Command version mask */
#define EC_VER_MASK(version) BIT(version)
/* I/O addresses for ACPI commands */
-#define EC_LPC_ADDR_ACPI_DATA 0x62
-#define EC_LPC_ADDR_ACPI_CMD 0x66
+#define EC_LPC_ADDR_ACPI_DATA 0x62
+#define EC_LPC_ADDR_ACPI_CMD 0x66
/* I/O addresses for host command */
-#define EC_LPC_ADDR_HOST_DATA 0x200
-#define EC_LPC_ADDR_HOST_CMD 0x204
+#define EC_LPC_ADDR_HOST_DATA 0x200
+#define EC_LPC_ADDR_HOST_CMD 0x204
/* I/O addresses for host command args and params */
/* Protocol version 2 */
-#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */
-#define EC_LPC_ADDR_HOST_PARAM 0x804 /* For version 2 params; size is
- * EC_PROTO2_MAX_PARAM_SIZE
- */
+#define EC_LPC_ADDR_HOST_ARGS 0x800 /* And 0x801, 0x802, 0x803 */
+#define EC_LPC_ADDR_HOST_PARAM \
+ 0x804 /* For version 2 params; size is \
+ * EC_PROTO2_MAX_PARAM_SIZE \
+ */
/* Protocol version 3 */
-#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */
-#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */
+#define EC_LPC_ADDR_HOST_PACKET 0x800 /* Offset of version 3 packet */
+#define EC_LPC_HOST_PACKET_SIZE 0x100 /* Max size of version 3 packet */
/*
* The actual block is 0x800-0x8ff, but some BIOSes think it's 0x880-0x8ff
@@ -107,65 +108,65 @@
* Other BIOSes report only the I/O port region spanned by the Microchip
* MEC series EC; an attempt to address a larger region may fail.
*/
-#define EC_HOST_CMD_REGION0 0x800
-#define EC_HOST_CMD_REGION1 0x880
-#define EC_HOST_CMD_REGION_SIZE 0x80
+#define EC_HOST_CMD_REGION0 0x800
+#define EC_HOST_CMD_REGION1 0x880
+#define EC_HOST_CMD_REGION_SIZE 0x80
#define EC_HOST_CMD_MEC_REGION_SIZE 0x8
/* EC command register bit functions */
-#define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */
-#define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */
-#define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */
-#define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */
-#define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */
-#define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */
-#define EC_LPC_CMDR_SMI BIT(6) /* SMI event is pending */
+#define EC_LPC_CMDR_DATA BIT(0) /* Data ready for host to read */
+#define EC_LPC_CMDR_PENDING BIT(1) /* Write pending to EC */
+#define EC_LPC_CMDR_BUSY BIT(2) /* EC is busy processing a command */
+#define EC_LPC_CMDR_CMD BIT(3) /* Last host write was a command */
+#define EC_LPC_CMDR_ACPI_BRST BIT(4) /* Burst mode (not used) */
+#define EC_LPC_CMDR_SCI BIT(5) /* SCI event is pending */
+#define EC_LPC_CMDR_SMI BIT(6) /* SMI event is pending */
-#define EC_LPC_ADDR_MEMMAP 0x900
-#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */
-#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */
+#define EC_LPC_ADDR_MEMMAP 0x900
+#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */
+#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */
/* The offset address of each type of data in mapped memory. */
-#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */
-#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */
-#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */
-#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */
-#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */
-#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */
-#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */
+#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors 0x00 - 0x0f */
+#define EC_MEMMAP_FAN 0x10 /* Fan speeds 0x10 - 0x17 */
+#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* More temp sensors 0x18 - 0x1f */
+#define EC_MEMMAP_ID 0x20 /* 0x20 == 'E', 0x21 == 'C' */
+#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */
+#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */
+#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */
#define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */
-#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */
-#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */
+#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */
+#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host cmd interface flags (8 bits) */
/* Unused 0x28 - 0x2f */
-#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */
+#define EC_MEMMAP_SWITCHES 0x30 /* 8 bits */
/* Unused 0x31 - 0x33 */
-#define EC_MEMMAP_HOST_EVENTS 0x34 /* 64 bits */
+#define EC_MEMMAP_HOST_EVENTS 0x34 /* 64 bits */
/* Battery values are all 32 bits, unless otherwise noted. */
-#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */
-#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */
-#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */
-#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, see below (8-bit) */
-#define EC_MEMMAP_BATT_COUNT 0x4d /* Battery Count (8-bit) */
-#define EC_MEMMAP_BATT_INDEX 0x4e /* Current Battery Data Index (8-bit) */
+#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */
+#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */
+#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */
+#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, see below (8-bit) */
+#define EC_MEMMAP_BATT_COUNT 0x4d /* Battery Count (8-bit) */
+#define EC_MEMMAP_BATT_INDEX 0x4e /* Current Battery Data Index (8-bit) */
/* Unused 0x4f */
-#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */
-#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */
-#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */
-#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */
+#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */
+#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */
+#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */
+#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */
/* Strings are all 8 bytes (EC_MEMMAP_TEXT_MAX) */
-#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */
-#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */
-#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */
-#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */
-#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */
+#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */
+#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */
+#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */
+#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */
+#define EC_MEMMAP_ALS 0x80 /* ALS readings in lux (2 X 16 bits) */
/* Unused 0x84 - 0x8f */
-#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/
+#define EC_MEMMAP_ACC_STATUS 0x90 /* Accelerometer status (8 bits )*/
/* Unused 0x91 */
-#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometers data 0x92 - 0x9f */
+#define EC_MEMMAP_ACC_DATA 0x92 /* Accelerometers data 0x92 - 0x9f */
/* 0x92: Lid Angle if available, LID_ANGLE_UNRELIABLE otherwise */
/* 0x94 - 0x99: 1st Accelerometer */
/* 0x9a - 0x9f: 2nd Accelerometer */
-#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */
+#define EC_MEMMAP_GYRO_DATA 0xa0 /* Gyroscope data 0xa0 - 0xa5 */
/* Unused 0xa6 - 0xdf */
/*
@@ -176,82 +177,82 @@
#define EC_MEMMAP_NO_ACPI 0xe0
/* Define the format of the accelerometer mapped memory status byte. */
-#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f
-#define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4)
-#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7)
+#define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f
+#define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4)
+#define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7)
/* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */
-#define EC_TEMP_SENSOR_ENTRIES 16
+#define EC_TEMP_SENSOR_ENTRIES 16
/*
* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B.
*
* Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2.
*/
-#define EC_TEMP_SENSOR_B_ENTRIES 8
+#define EC_TEMP_SENSOR_B_ENTRIES 8
/* Max temp sensor entries for host commands */
-#define EC_MAX_TEMP_SENSOR_ENTRIES (EC_TEMP_SENSOR_ENTRIES + \
- EC_TEMP_SENSOR_B_ENTRIES)
+#define EC_MAX_TEMP_SENSOR_ENTRIES \
+ (EC_TEMP_SENSOR_ENTRIES + EC_TEMP_SENSOR_B_ENTRIES)
/* Special values for mapped temperature sensors */
-#define EC_TEMP_SENSOR_NOT_PRESENT 0xff
-#define EC_TEMP_SENSOR_ERROR 0xfe
-#define EC_TEMP_SENSOR_NOT_POWERED 0xfd
+#define EC_TEMP_SENSOR_NOT_PRESENT 0xff
+#define EC_TEMP_SENSOR_ERROR 0xfe
+#define EC_TEMP_SENSOR_NOT_POWERED 0xfd
#define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc
/*
* The offset of temperature value stored in mapped memory. This allows
* reporting a temperature range of 200K to 454K = -73C to 181C.
*/
-#define EC_TEMP_SENSOR_OFFSET 200
+#define EC_TEMP_SENSOR_OFFSET 200
/*
* Number of ALS readings at EC_MEMMAP_ALS
*/
-#define EC_ALS_ENTRIES 2
+#define EC_ALS_ENTRIES 2
/*
* The default value a temperature sensor will return when it is present but
* has not been read this boot. This is a reasonable number to avoid
* triggering alarms on the host.
*/
-#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET)
+#define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET)
-#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */
-#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */
-#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */
+#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */
+#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */
+#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */
/* Battery bit flags at EC_MEMMAP_BATT_FLAG. */
-#define EC_BATT_FLAG_AC_PRESENT 0x01
+#define EC_BATT_FLAG_AC_PRESENT 0x01
#define EC_BATT_FLAG_BATT_PRESENT 0x02
-#define EC_BATT_FLAG_DISCHARGING 0x04
-#define EC_BATT_FLAG_CHARGING 0x08
+#define EC_BATT_FLAG_DISCHARGING 0x04
+#define EC_BATT_FLAG_CHARGING 0x08
#define EC_BATT_FLAG_LEVEL_CRITICAL 0x10
/* Set if some of the static/dynamic data is invalid (or outdated). */
#define EC_BATT_FLAG_INVALID_DATA 0x20
/* Switch flags at EC_MEMMAP_SWITCHES */
-#define EC_SWITCH_LID_OPEN 0x01
-#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02
+#define EC_SWITCH_LID_OPEN 0x01
+#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02
#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04
/* Was recovery requested via keyboard; now unused. */
-#define EC_SWITCH_IGNORE1 0x08
+#define EC_SWITCH_IGNORE1 0x08
/* Recovery requested via dedicated signal (from servo board) */
-#define EC_SWITCH_DEDICATED_RECOVERY 0x10
+#define EC_SWITCH_DEDICATED_RECOVERY 0x10
/* Was fake developer mode switch; now unused. Remove in next refactor. */
-#define EC_SWITCH_IGNORE0 0x20
+#define EC_SWITCH_IGNORE0 0x20
/* Host command interface flags */
/* Host command interface supports LPC args (LPC interface only) */
-#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01
+#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01
/* Host command interface supports version 3 protocol */
-#define EC_HOST_CMD_FLAG_VERSION_3 0x02
+#define EC_HOST_CMD_FLAG_VERSION_3 0x02
/* Wireless switch flags */
-#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */
-#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */
-#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */
-#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */
-#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */
+#define EC_WIRELESS_SWITCH_ALL ~0x00 /* All flags */
+#define EC_WIRELESS_SWITCH_WLAN 0x01 /* WLAN radio */
+#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02 /* Bluetooth radio */
+#define EC_WIRELESS_SWITCH_WWAN 0x04 /* WWAN power */
+#define EC_WIRELESS_SWITCH_WLAN_POWER 0x08 /* WLAN power */
/*****************************************************************************/
/*
@@ -319,19 +320,19 @@
/* Valid addresses in ACPI memory space, for read/write commands */
/* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */
-#define EC_ACPI_MEM_VERSION 0x00
+#define EC_ACPI_MEM_VERSION 0x00
/*
* Test location; writing value here updates test compliment byte to (0xff -
* value).
*/
-#define EC_ACPI_MEM_TEST 0x01
+#define EC_ACPI_MEM_TEST 0x01
/* Test compliment; writes here are ignored. */
-#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02
+#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02
/* Keyboard backlight brightness percent (0 - 100) */
#define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03
/* DPTF Target Fan Duty (0-100, 0xff for auto/none) */
-#define EC_ACPI_MEM_FAN_DUTY 0x04
+#define EC_ACPI_MEM_FAN_DUTY 0x04
/*
* DPTF temp thresholds. Any of the EC's temp sensors can have up to two
@@ -348,9 +349,9 @@
* have tripped". Setting or enabling the thresholds for a sensor will clear
* the unread event count for that sensor.
*/
-#define EC_ACPI_MEM_TEMP_ID 0x05
-#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06
-#define EC_ACPI_MEM_TEMP_COMMIT 0x07
+#define EC_ACPI_MEM_TEMP_ID 0x05
+#define EC_ACPI_MEM_TEMP_THRESHOLD 0x06
+#define EC_ACPI_MEM_TEMP_COMMIT 0x07
/*
* Here are the bits for the COMMIT register:
* bit 0 selects the threshold index for the chosen sensor (0/1)
@@ -375,12 +376,12 @@
*/
/* DPTF battery charging current limit */
-#define EC_ACPI_MEM_CHARGING_LIMIT 0x08
+#define EC_ACPI_MEM_CHARGING_LIMIT 0x08
/* Charging limit is specified in 64 mA steps */
-#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64
+#define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64
/* Value to disable DPTF battery charging limit */
-#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff
+#define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff
/*
* Report device orientation
@@ -393,10 +394,10 @@
* 0 Tablet Mode Device Indicator (TBMD)
*/
#define EC_ACPI_MEM_DEVICE_ORIENTATION 0x09
-#define EC_ACPI_MEM_TBMD_SHIFT 0
-#define EC_ACPI_MEM_TBMD_MASK 0x1
-#define EC_ACPI_MEM_DDPN_SHIFT 1
-#define EC_ACPI_MEM_DDPN_MASK 0x7
+#define EC_ACPI_MEM_TBMD_SHIFT 0
+#define EC_ACPI_MEM_TBMD_MASK 0x1
+#define EC_ACPI_MEM_DDPN_SHIFT 1
+#define EC_ACPI_MEM_DDPN_MASK 0x7
/*
* Report device features. Uses the same format as the host command, except:
@@ -419,7 +420,7 @@
#define EC_ACPI_MEM_DEVICE_FEATURES6 0x10
#define EC_ACPI_MEM_DEVICE_FEATURES7 0x11
-#define EC_ACPI_MEM_BATTERY_INDEX 0x12
+#define EC_ACPI_MEM_BATTERY_INDEX 0x12
/*
* USB Port Power. Each bit indicates whether the corresponding USB ports' power
@@ -458,40 +459,38 @@
#define EC_ACPI_MEM_USB_RETIMER_FW_UPDATE 0x14
#define USB_RETIMER_FW_UPDATE_OP_SHIFT 4
-#define USB_RETIMER_FW_UPDATE_ERR 0xfe
+#define USB_RETIMER_FW_UPDATE_ERR 0xfe
#define USB_RETIMER_FW_UPDATE_INVALID_MUX 0xff
/* Mask to clear unused MUX bits in retimer firmware update */
-#define USB_RETIMER_FW_UPDATE_MUX_MASK (USB_PD_MUX_USB_ENABLED | \
- USB_PD_MUX_DP_ENABLED | \
- USB_PD_MUX_SAFE_MODE | \
- USB_PD_MUX_TBT_COMPAT_ENABLED | \
- USB_PD_MUX_USB4_ENABLED)
+#define USB_RETIMER_FW_UPDATE_MUX_MASK \
+ (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED | \
+ USB_PD_MUX_SAFE_MODE | USB_PD_MUX_TBT_COMPAT_ENABLED | \
+ USB_PD_MUX_USB4_ENABLED)
/* Retimer firmware update operations */
#define USB_RETIMER_FW_UPDATE_QUERY_PORT 0 /* Which ports has retimer */
#define USB_RETIMER_FW_UPDATE_SUSPEND_PD 1 /* Suspend PD port */
-#define USB_RETIMER_FW_UPDATE_RESUME_PD 2 /* Resume PD port */
-#define USB_RETIMER_FW_UPDATE_GET_MUX 3 /* Read current USB MUX */
-#define USB_RETIMER_FW_UPDATE_SET_USB 4 /* Set MUX to USB mode */
-#define USB_RETIMER_FW_UPDATE_SET_SAFE 5 /* Set MUX to Safe mode */
-#define USB_RETIMER_FW_UPDATE_SET_TBT 6 /* Set MUX to TBT mode */
+#define USB_RETIMER_FW_UPDATE_RESUME_PD 2 /* Resume PD port */
+#define USB_RETIMER_FW_UPDATE_GET_MUX 3 /* Read current USB MUX */
+#define USB_RETIMER_FW_UPDATE_SET_USB 4 /* Set MUX to USB mode */
+#define USB_RETIMER_FW_UPDATE_SET_SAFE 5 /* Set MUX to Safe mode */
+#define USB_RETIMER_FW_UPDATE_SET_TBT 6 /* Set MUX to TBT mode */
#define USB_RETIMER_FW_UPDATE_DISCONNECT 7 /* Set MUX to disconnect */
-#define EC_ACPI_MEM_USB_RETIMER_PORT(x) ((x) & 0x0f)
+#define EC_ACPI_MEM_USB_RETIMER_PORT(x) ((x)&0x0f)
#define EC_ACPI_MEM_USB_RETIMER_OP(x) \
- (((x) & 0xf0) >> USB_RETIMER_FW_UPDATE_OP_SHIFT)
+ (((x)&0xf0) >> USB_RETIMER_FW_UPDATE_OP_SHIFT)
/*
* ACPI addresses 0x20 - 0xff map to EC_MEMMAP offset 0x00 - 0xdf. This data
* is read-only from the AP. Added in EC_ACPI_MEM_VERSION 2.
*/
-#define EC_ACPI_MEM_MAPPED_BEGIN 0x20
-#define EC_ACPI_MEM_MAPPED_SIZE 0xe0
+#define EC_ACPI_MEM_MAPPED_BEGIN 0x20
+#define EC_ACPI_MEM_MAPPED_SIZE 0xe0
/* Current version of ACPI memory address space */
#define EC_ACPI_MEM_VERSION_CURRENT 2
-
/*
* This header file is used in coreboot both in C and ACPI code. The ACPI code
* is pre-processed to handle constants but the ASL compiler is unable to
@@ -511,7 +510,7 @@
#ifndef __aligned
#define __aligned(x) __attribute__((aligned(x)))
#endif
-#endif /* __KERNEL__ */
+#endif /* __KERNEL__ */
/*
* Attributes for EC request and response packets. Just defining __packed
@@ -578,7 +577,7 @@
#define __ec_todo_packed __packed
#define __ec_todo_unpacked
-#else /* !CONFIG_HOSTCMD_ALIGNED */
+#else /* !CONFIG_HOSTCMD_ALIGNED */
/*
* Packed structures make no assumption about alignment, so they do inefficient
@@ -593,25 +592,25 @@
#define __ec_todo_packed __packed
#define __ec_todo_unpacked
-#endif /* !CONFIG_HOSTCMD_ALIGNED */
+#endif /* !CONFIG_HOSTCMD_ALIGNED */
/* LPC command status byte masks */
/* EC has written a byte in the data register and host hasn't read it yet */
-#define EC_LPC_STATUS_TO_HOST 0x01
+#define EC_LPC_STATUS_TO_HOST 0x01
/* Host has written a command/data byte and the EC hasn't read it yet */
-#define EC_LPC_STATUS_FROM_HOST 0x02
+#define EC_LPC_STATUS_FROM_HOST 0x02
/* EC is processing a command */
-#define EC_LPC_STATUS_PROCESSING 0x04
+#define EC_LPC_STATUS_PROCESSING 0x04
/* Last write to EC was a command, not data */
-#define EC_LPC_STATUS_LAST_CMD 0x08
+#define EC_LPC_STATUS_LAST_CMD 0x08
/* EC is in burst mode */
-#define EC_LPC_STATUS_BURST_MODE 0x10
+#define EC_LPC_STATUS_BURST_MODE 0x10
/* SCI event is pending (requesting SCI query) */
#define EC_LPC_STATUS_SCI_PENDING 0x20
/* SMI event is pending (requesting SMI query) */
#define EC_LPC_STATUS_SMI_PENDING 0x40
/* (reserved) */
-#define EC_LPC_STATUS_RESERVED 0x80
+#define EC_LPC_STATUS_RESERVED 0x80
/*
* EC is busy. This covers both the EC processing a command, and the host has
@@ -632,21 +631,21 @@
EC_RES_INVALID_RESPONSE = 5,
EC_RES_INVALID_VERSION = 6,
EC_RES_INVALID_CHECKSUM = 7,
- EC_RES_IN_PROGRESS = 8, /* Accepted, command in progress */
- EC_RES_UNAVAILABLE = 9, /* No response available */
- EC_RES_TIMEOUT = 10, /* We got a timeout */
- EC_RES_OVERFLOW = 11, /* Table / data overflow */
- EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */
- EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */
- EC_RES_RESPONSE_TOO_BIG = 14, /* Response was too big to handle */
- EC_RES_BUS_ERROR = 15, /* Communications bus error */
- EC_RES_BUSY = 16, /* Up but too busy. Should retry */
- EC_RES_INVALID_HEADER_VERSION = 17, /* Header version invalid */
- EC_RES_INVALID_HEADER_CRC = 18, /* Header CRC invalid */
- EC_RES_INVALID_DATA_CRC = 19, /* Data CRC invalid */
- EC_RES_DUP_UNAVAILABLE = 20, /* Can't resend response */
+ EC_RES_IN_PROGRESS = 8, /* Accepted, command in progress */
+ EC_RES_UNAVAILABLE = 9, /* No response available */
+ EC_RES_TIMEOUT = 10, /* We got a timeout */
+ EC_RES_OVERFLOW = 11, /* Table / data overflow */
+ EC_RES_INVALID_HEADER = 12, /* Header contains invalid data */
+ EC_RES_REQUEST_TRUNCATED = 13, /* Didn't get the entire request */
+ EC_RES_RESPONSE_TOO_BIG = 14, /* Response was too big to handle */
+ EC_RES_BUS_ERROR = 15, /* Communications bus error */
+ EC_RES_BUSY = 16, /* Up but too busy. Should retry */
+ EC_RES_INVALID_HEADER_VERSION = 17, /* Header version invalid */
+ EC_RES_INVALID_HEADER_CRC = 18, /* Header CRC invalid */
+ EC_RES_INVALID_DATA_CRC = 19, /* Data CRC invalid */
+ EC_RES_DUP_UNAVAILABLE = 20, /* Can't resend response */
- EC_RES_MAX = UINT16_MAX /**< Force enum to be 16 bits */
+ EC_RES_MAX = UINT16_MAX /**< Force enum to be 16 bits */
} __packed;
BUILD_ASSERT(sizeof(enum ec_status) == sizeof(uint16_t));
@@ -741,7 +740,7 @@
EC_HOST_EVENT_INVALID = 32
};
/* Host event mask */
-#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code) - 1)
+#define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code)-1)
/**
* struct ec_lpc_host_args - Arguments at EC_LPC_ADDR_HOST_ARGS
@@ -776,7 +775,7 @@
* response. Command version is 0 and response data from EC is at
* EC_LPC_ADDR_OLD_PARAM with unknown length.
*/
-#define EC_HOST_ARGS_FLAG_TO_HOST 0x02
+#define EC_HOST_ARGS_FLAG_TO_HOST 0x02
/*****************************************************************************/
/*
@@ -818,12 +817,12 @@
* request, the AP will clock in bytes until it sees the framing byte, then
* clock in the response packet.
*/
-#define EC_SPI_FRAME_START 0xec
+#define EC_SPI_FRAME_START 0xec
/*
* Padding bytes which are clocked out after the end of a response packet.
*/
-#define EC_SPI_PAST_END 0xed
+#define EC_SPI_PAST_END 0xed
/*
* EC is ready to receive, and has ignored the byte sent by the AP. EC expects
@@ -834,36 +833,36 @@
* CS goes low. This macro has the Most Significant Bit set to zero,
* so SDO will not be driven high when CS goes low.
*/
-#define EC_SPI_RX_READY 0x78
+#define EC_SPI_RX_READY 0x78
/*
* EC has started receiving the request from the AP, but hasn't started
* processing it yet.
*/
-#define EC_SPI_RECEIVING 0xf9
+#define EC_SPI_RECEIVING 0xf9
/* EC has received the entire request from the AP and is processing it. */
-#define EC_SPI_PROCESSING 0xfa
+#define EC_SPI_PROCESSING 0xfa
/*
* EC received bad data from the AP, such as a packet header with an invalid
* length. EC will ignore all data until chip select deasserts.
*/
-#define EC_SPI_RX_BAD_DATA 0xfb
+#define EC_SPI_RX_BAD_DATA 0xfb
/*
* EC received data from the AP before it was ready. That is, the AP asserted
* chip select and started clocking data before the EC was ready to receive it.
* EC will ignore all data until chip select deasserts.
*/
-#define EC_SPI_NOT_READY 0xfc
+#define EC_SPI_NOT_READY 0xfc
/*
* EC was ready to receive a request from the AP. EC has treated the byte sent
* by the AP as part of a request packet, or (for old-style ECs) is processing
* a fully received packet but is not ready to respond yet.
*/
-#define EC_SPI_OLD_READY 0xfd
+#define EC_SPI_OLD_READY 0xfd
/*****************************************************************************/
@@ -885,22 +884,22 @@
*/
#define EC_PROTO2_REQUEST_HEADER_BYTES 3
#define EC_PROTO2_REQUEST_TRAILER_BYTES 1
-#define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \
- EC_PROTO2_REQUEST_TRAILER_BYTES)
+#define EC_PROTO2_REQUEST_OVERHEAD \
+ (EC_PROTO2_REQUEST_HEADER_BYTES + EC_PROTO2_REQUEST_TRAILER_BYTES)
#define EC_PROTO2_RESPONSE_HEADER_BYTES 2
#define EC_PROTO2_RESPONSE_TRAILER_BYTES 1
-#define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \
- EC_PROTO2_RESPONSE_TRAILER_BYTES)
+#define EC_PROTO2_RESPONSE_OVERHEAD \
+ (EC_PROTO2_RESPONSE_HEADER_BYTES + EC_PROTO2_RESPONSE_TRAILER_BYTES)
/* Parameter length was limited by the LPC interface */
#define EC_PROTO2_MAX_PARAM_SIZE 0xfc
/* Maximum request and response packet sizes for protocol version 2 */
-#define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \
- EC_PROTO2_MAX_PARAM_SIZE)
-#define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \
- EC_PROTO2_MAX_PARAM_SIZE)
+#define EC_PROTO2_MAX_REQUEST_SIZE \
+ (EC_PROTO2_REQUEST_OVERHEAD + EC_PROTO2_MAX_PARAM_SIZE)
+#define EC_PROTO2_MAX_RESPONSE_SIZE \
+ (EC_PROTO2_RESPONSE_OVERHEAD + EC_PROTO2_MAX_PARAM_SIZE)
/*****************************************************************************/
@@ -1072,15 +1071,15 @@
} __ec_align4;
/* Fields in fields0 byte */
-#define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f
-#define EC_PACKET4_0_IS_RESPONSE_MASK 0x10
-#define EC_PACKET4_0_SEQ_NUM_SHIFT 5
-#define EC_PACKET4_0_SEQ_NUM_MASK 0x60
-#define EC_PACKET4_0_SEQ_DUP_MASK 0x80
+#define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f
+#define EC_PACKET4_0_IS_RESPONSE_MASK 0x10
+#define EC_PACKET4_0_SEQ_NUM_SHIFT 5
+#define EC_PACKET4_0_SEQ_NUM_MASK 0x60
+#define EC_PACKET4_0_SEQ_DUP_MASK 0x80
/* Fields in fields1 byte */
-#define EC_PACKET4_1_COMMAND_VERSION_MASK 0x1f /* (request only) */
-#define EC_PACKET4_1_DATA_CRC_PRESENT_MASK 0x80
+#define EC_PACKET4_1_COMMAND_VERSION_MASK 0x1f /* (request only) */
+#define EC_PACKET4_1_DATA_CRC_PRESENT_MASK 0x80
/*****************************************************************************/
/*
@@ -1167,7 +1166,7 @@
struct ec_response_get_version {
char version_string_ro[32];
char version_string_rw[32];
- char reserved[32]; /* Changed to cros_fwid_ro in version 1 */
+ char reserved[32]; /* Changed to cros_fwid_ro in version 1 */
uint32_t current_image;
} __ec_align4;
@@ -1187,9 +1186,9 @@
struct ec_response_get_version_v1 {
char version_string_ro[32];
char version_string_rw[32];
- char cros_fwid_ro[32]; /* Added in version 1 (Used to be reserved) */
+ char cros_fwid_ro[32]; /* Added in version 1 (Used to be reserved) */
uint32_t current_image;
- char cros_fwid_rw[32]; /* Added in version 1 */
+ char cros_fwid_rw[32]; /* Added in version 1 */
} __ec_align4;
/* Read test */
@@ -1302,11 +1301,11 @@
* lpc must read the status from the command register. Attempting this on
* lpc will overwrite the args/parameter space and corrupt its data.
*/
-#define EC_CMD_GET_COMMS_STATUS 0x0009
+#define EC_CMD_GET_COMMS_STATUS 0x0009
/* Avoid using ec_status which is for return values */
enum ec_comms_status {
- EC_COMMS_STATUS_PROCESSING = BIT(0), /* Processing cmd */
+ EC_COMMS_STATUS_PROCESSING = BIT(0), /* Processing cmd */
};
/**
@@ -1315,11 +1314,11 @@
* @flags: Mask of enum ec_comms_status.
*/
struct ec_response_get_comms_status {
- uint32_t flags; /* Mask of enum ec_comms_status */
+ uint32_t flags; /* Mask of enum ec_comms_status */
} __ec_align4;
/* Fake a variety of responses, purely for testing purposes. */
-#define EC_CMD_TEST_PROTOCOL 0x000A
+#define EC_CMD_TEST_PROTOCOL 0x000A
/* Tell the EC what to send back to us. */
struct ec_params_test_protocol {
@@ -1334,7 +1333,7 @@
} __ec_align4;
/* Get protocol information */
-#define EC_CMD_GET_PROTOCOL_INFO 0x000B
+#define EC_CMD_GET_PROTOCOL_INFO 0x000B
/* Flags for ec_response_get_protocol_info.flags */
/* EC_RES_IN_PROGRESS may be returned if a command is slow */
@@ -1356,12 +1355,11 @@
uint32_t flags;
} __ec_align4;
-
/*****************************************************************************/
/* Get/Set miscellaneous values */
/* The upper byte of .flags tells what to do (nothing means "get") */
-#define EC_GSV_SET 0x80000000
+#define EC_GSV_SET 0x80000000
/*
* The lower three bytes of .flags identifies the parameter, if that has
@@ -1380,11 +1378,11 @@
} __ec_align4;
/* More than one command can use these structs to get/set parameters. */
-#define EC_CMD_GSV_PAUSE_IN_S5 0x000C
+#define EC_CMD_GSV_PAUSE_IN_S5 0x000C
/*****************************************************************************/
/* List the features supported by the firmware */
-#define EC_CMD_GET_FEATURES 0x000D
+#define EC_CMD_GET_FEATURES 0x000D
/* Supported features */
enum ec_feature_code {
@@ -1723,9 +1721,9 @@
* permitted while erasing. (For instance, STM32F4).
*/
enum ec_flash_erase_cmd {
- FLASH_ERASE_SECTOR, /* Erase and wait for result */
- FLASH_ERASE_SECTOR_ASYNC, /* Erase and return immediately. */
- FLASH_ERASE_GET_RESULT, /* Ask for last erase result */
+ FLASH_ERASE_SECTOR, /* Erase and wait for result */
+ FLASH_ERASE_SECTOR_ASYNC, /* Erase and return immediately. */
+ FLASH_ERASE_GET_RESULT, /* Ask for last erase result */
};
/**
@@ -1736,8 +1734,8 @@
* @params: Same as v0 parameters.
*/
struct ec_params_flash_erase_v1 {
- uint8_t cmd;
- uint8_t reserved;
+ uint8_t cmd;
+ uint8_t reserved;
uint16_t flag;
struct ec_params_flash_erase params;
} __ec_align4;
@@ -1753,22 +1751,22 @@
* If mask=0, simply returns the current flags state.
*/
#define EC_CMD_FLASH_PROTECT 0x0015
-#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */
+#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */
/* Flags for flash protection */
/* RO flash code protected when the EC boots */
-#define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0)
+#define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0)
/*
* RO flash code protected now. If this bit is set, at-boot status cannot
* be changed.
*/
-#define EC_FLASH_PROTECT_RO_NOW BIT(1)
+#define EC_FLASH_PROTECT_RO_NOW BIT(1)
/* Entire flash code protected now, until reboot. */
-#define EC_FLASH_PROTECT_ALL_NOW BIT(2)
+#define EC_FLASH_PROTECT_ALL_NOW BIT(2)
/* Flash write protect GPIO is asserted now */
-#define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3)
+#define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3)
/* Error - at least one bank of flash is stuck locked, and cannot be unlocked */
-#define EC_FLASH_PROTECT_ERROR_STUCK BIT(4)
+#define EC_FLASH_PROTECT_ERROR_STUCK BIT(4)
/*
* Error - flash protection is in inconsistent state. At least one bank of
* flash which should be protected is not protected. Usually fixed by
@@ -1776,18 +1774,17 @@
*/
#define EC_FLASH_PROTECT_ERROR_INCONSISTENT BIT(5)
/* Entire flash code protected when the EC boots */
-#define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6)
+#define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6)
/* RW flash code protected when the EC boots */
-#define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7)
+#define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7)
/* RW flash code protected now. */
-#define EC_FLASH_PROTECT_RW_NOW BIT(8)
+#define EC_FLASH_PROTECT_RW_NOW BIT(8)
/* Rollback information flash region protected when the EC boots */
-#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9)
+#define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9)
/* Rollback information flash region protected now */
-#define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10)
+#define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10)
/* Error - Unknown error */
-#define EC_FLASH_PROTECT_ERROR_UNKNOWN BIT(11)
-
+#define EC_FLASH_PROTECT_ERROR_UNKNOWN BIT(11)
/**
* struct ec_params_flash_protect - Parameters for the flash protect command.
@@ -1883,7 +1880,6 @@
uint8_t sr1, sr2;
} __ec_align1;
-
/* Select flash during flash operations */
#define EC_CMD_FLASH_SELECT 0x0019
@@ -1895,22 +1891,21 @@
uint8_t select;
} __ec_align4;
-
/**
* Request random numbers to be generated and returned.
* Can be used to test the random number generator is truly random.
* See https://csrc.nist.gov/publications/detail/sp/800-22/rev-1a/final and
* https://webhome.phy.duke.edu/~rgb/General/dieharder.php.
*/
-#define EC_CMD_RAND_NUM 0x001A
+#define EC_CMD_RAND_NUM 0x001A
#define EC_VER_RAND_NUM 0
struct ec_params_rand_num {
- uint16_t num_rand_bytes; /**< num random bytes to generate */
+ uint16_t num_rand_bytes; /**< num random bytes to generate */
} __ec_align4;
struct ec_response_rand_num {
- uint8_t rand[0]; /**< generated random numbers */
+ uint8_t rand[0]; /**< generated random numbers */
} __ec_align4;
BUILD_ASSERT(sizeof(struct ec_response_rand_num) == 0);
@@ -1978,9 +1973,9 @@
};
struct ec_response_sysinfo {
- uint32_t reset_flags; /**< EC_RESET_FLAG_* flags */
- uint32_t current_image; /**< enum ec_current_image */
- uint32_t flags; /**< enum sysinfo_flags */
+ uint32_t reset_flags; /**< EC_RESET_FLAG_* flags */
+ uint32_t current_image; /**< enum ec_current_image */
+ uint32_t flags; /**< enum sysinfo_flags */
} __ec_align4;
/*****************************************************************************/
@@ -2053,20 +2048,20 @@
};
struct ec_params_pwm_set_duty {
- uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */
- uint8_t pwm_type; /* ec_pwm_type */
- uint8_t index; /* Type-specific index, or 0 if unique */
+ uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */
+ uint8_t pwm_type; /* ec_pwm_type */
+ uint8_t index; /* Type-specific index, or 0 if unique */
} __ec_align4;
#define EC_CMD_PWM_GET_DUTY 0x0026
struct ec_params_pwm_get_duty {
- uint8_t pwm_type; /* ec_pwm_type */
- uint8_t index; /* Type-specific index, or 0 if unique */
+ uint8_t pwm_type; /* ec_pwm_type */
+ uint8_t index; /* Type-specific index, or 0 if unique */
} __ec_align1;
struct ec_response_pwm_get_duty {
- uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */
+ uint16_t duty; /* Duty cycle, EC_PWM_MAX_DUTY = 100% */
} __ec_align2;
/*****************************************************************************/
@@ -2093,8 +2088,8 @@
int32_t google_ramp_up;
int32_t google_ramp_down;
int32_t s3s0_ramp_up;
- int32_t s0_tick_delay[2]; /* AC=0/1 */
- int32_t s0a_tick_delay[2]; /* AC=0/1 */
+ int32_t s0_tick_delay[2]; /* AC=0/1 */
+ int32_t s0a_tick_delay[2]; /* AC=0/1 */
int32_t s0s3_ramp_down;
int32_t s3_sleep_for;
int32_t s3_ramp_up;
@@ -2102,24 +2097,24 @@
/* Oscillation */
uint8_t new_s0;
- uint8_t osc_min[2]; /* AC=0/1 */
- uint8_t osc_max[2]; /* AC=0/1 */
- uint8_t w_ofs[2]; /* AC=0/1 */
+ uint8_t osc_min[2]; /* AC=0/1 */
+ uint8_t osc_max[2]; /* AC=0/1 */
+ uint8_t w_ofs[2]; /* AC=0/1 */
/* Brightness limits based on the backlight and AC. */
- uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */
- uint8_t bright_bl_on_min[2]; /* AC=0/1 */
- uint8_t bright_bl_on_max[2]; /* AC=0/1 */
+ uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */
+ uint8_t bright_bl_on_min[2]; /* AC=0/1 */
+ uint8_t bright_bl_on_max[2]; /* AC=0/1 */
/* Battery level thresholds */
uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
/* Map [AC][battery_level] to color index */
- uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */
- uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */
+ uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */
+ uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */
/* Color palette */
- struct rgb_s color[8]; /* 0-3 are Google colors */
+ struct rgb_s color[8]; /* 0-3 are Google colors */
} __ec_todo_packed;
struct lightbar_params_v1 {
@@ -2127,8 +2122,8 @@
int32_t google_ramp_up;
int32_t google_ramp_down;
int32_t s3s0_ramp_up;
- int32_t s0_tick_delay[2]; /* AC=0/1 */
- int32_t s0a_tick_delay[2]; /* AC=0/1 */
+ int32_t s0_tick_delay[2]; /* AC=0/1 */
+ int32_t s0a_tick_delay[2]; /* AC=0/1 */
int32_t s0s3_ramp_down;
int32_t s3_sleep_for;
int32_t s3_ramp_up;
@@ -2148,27 +2143,27 @@
uint8_t tap_idx[3];
/* Oscillation */
- uint8_t osc_min[2]; /* AC=0/1 */
- uint8_t osc_max[2]; /* AC=0/1 */
- uint8_t w_ofs[2]; /* AC=0/1 */
+ uint8_t osc_min[2]; /* AC=0/1 */
+ uint8_t osc_max[2]; /* AC=0/1 */
+ uint8_t w_ofs[2]; /* AC=0/1 */
/* Brightness limits based on the backlight and AC. */
- uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */
- uint8_t bright_bl_on_min[2]; /* AC=0/1 */
- uint8_t bright_bl_on_max[2]; /* AC=0/1 */
+ uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */
+ uint8_t bright_bl_on_min[2]; /* AC=0/1 */
+ uint8_t bright_bl_on_max[2]; /* AC=0/1 */
/* Battery level thresholds */
uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
/* Map [AC][battery_level] to color index */
- uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */
- uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */
+ uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */
+ uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */
/* s5: single color pulse on inhibited power-up */
uint8_t s5_idx;
/* Color palette */
- struct rgb_s color[8]; /* 0-3 are Google colors */
+ struct rgb_s color[8]; /* 0-3 are Google colors */
} __ec_todo_packed;
/* Lightbar command params v2
@@ -2185,8 +2180,8 @@
int32_t google_ramp_up;
int32_t google_ramp_down;
int32_t s3s0_ramp_up;
- int32_t s0_tick_delay[2]; /* AC=0/1 */
- int32_t s0a_tick_delay[2]; /* AC=0/1 */
+ int32_t s0_tick_delay[2]; /* AC=0/1 */
+ int32_t s0a_tick_delay[2]; /* AC=0/1 */
int32_t s0s3_ramp_down;
int32_t s3_sleep_for;
int32_t s3_ramp_up;
@@ -2210,16 +2205,16 @@
struct lightbar_params_v2_oscillation {
/* Oscillation */
- uint8_t osc_min[2]; /* AC=0/1 */
- uint8_t osc_max[2]; /* AC=0/1 */
- uint8_t w_ofs[2]; /* AC=0/1 */
+ uint8_t osc_min[2]; /* AC=0/1 */
+ uint8_t osc_max[2]; /* AC=0/1 */
+ uint8_t w_ofs[2]; /* AC=0/1 */
} __ec_todo_packed;
struct lightbar_params_v2_brightness {
/* Brightness limits based on the backlight and AC. */
- uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */
- uint8_t bright_bl_on_min[2]; /* AC=0/1 */
- uint8_t bright_bl_on_max[2]; /* AC=0/1 */
+ uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */
+ uint8_t bright_bl_on_min[2]; /* AC=0/1 */
+ uint8_t bright_bl_on_max[2]; /* AC=0/1 */
} __ec_todo_packed;
struct lightbar_params_v2_thresholds {
@@ -2229,14 +2224,14 @@
struct lightbar_params_v2_colors {
/* Map [AC][battery_level] to color index */
- uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */
- uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */
+ uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */
+ uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */
/* s5: single color pulse on inhibited power-up */
uint8_t s5_idx;
/* Color palette */
- struct rgb_s color[8]; /* 0-3 are Google colors */
+ struct rgb_s color[8]; /* 0-3 are Google colors */
} __ec_todo_packed;
/* Lightbar program. */
@@ -2247,7 +2242,7 @@
} __ec_todo_unpacked;
struct ec_params_lightbar {
- uint8_t cmd; /* Command (see enum lightbar_command) */
+ uint8_t cmd; /* Command (see enum lightbar_command) */
union {
/*
* The following commands have no args:
@@ -2312,7 +2307,6 @@
struct lightbar_params_v0 get_params_v0;
struct lightbar_params_v1 get_params_v1;
-
struct lightbar_params_v2_timing get_params_v2_timing;
struct lightbar_params_v2_tap get_params_v2_tap;
struct lightbar_params_v2_oscillation get_params_v2_osc;
@@ -2409,7 +2403,7 @@
/* LED control flags */
#define EC_LED_FLAGS_QUERY BIT(0) /* Query LED capability only */
-#define EC_LED_FLAGS_AUTO BIT(1) /* Switch LED back to automatic control */
+#define EC_LED_FLAGS_AUTO BIT(1) /* Switch LED back to automatic control */
enum ec_led_colors {
EC_LED_COLOR_RED = 0,
@@ -2423,8 +2417,8 @@
};
struct ec_params_led_control {
- uint8_t led_id; /* Which LED to control */
- uint8_t flags; /* Control flags */
+ uint8_t led_id; /* Which LED to control */
+ uint8_t flags; /* Control flags */
uint8_t brightness[EC_LED_COLOR_COUNT];
} __ec_align1;
@@ -2452,30 +2446,30 @@
#define EC_CMD_VBOOT_HASH 0x002A
struct ec_params_vboot_hash {
- uint8_t cmd; /* enum ec_vboot_hash_cmd */
- uint8_t hash_type; /* enum ec_vboot_hash_type */
- uint8_t nonce_size; /* Nonce size; may be 0 */
- uint8_t reserved0; /* Reserved; set 0 */
- uint32_t offset; /* Offset in flash to hash */
- uint32_t size; /* Number of bytes to hash */
- uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */
+ uint8_t cmd; /* enum ec_vboot_hash_cmd */
+ uint8_t hash_type; /* enum ec_vboot_hash_type */
+ uint8_t nonce_size; /* Nonce size; may be 0 */
+ uint8_t reserved0; /* Reserved; set 0 */
+ uint32_t offset; /* Offset in flash to hash */
+ uint32_t size; /* Number of bytes to hash */
+ uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */
} __ec_align4;
struct ec_response_vboot_hash {
- uint8_t status; /* enum ec_vboot_hash_status */
- uint8_t hash_type; /* enum ec_vboot_hash_type */
- uint8_t digest_size; /* Size of hash digest in bytes */
- uint8_t reserved0; /* Ignore; will be 0 */
- uint32_t offset; /* Offset in flash which was hashed */
- uint32_t size; /* Number of bytes hashed */
+ uint8_t status; /* enum ec_vboot_hash_status */
+ uint8_t hash_type; /* enum ec_vboot_hash_type */
+ uint8_t digest_size; /* Size of hash digest in bytes */
+ uint8_t reserved0; /* Ignore; will be 0 */
+ uint32_t offset; /* Offset in flash which was hashed */
+ uint32_t size; /* Number of bytes hashed */
uint8_t hash_digest[64]; /* Hash digest data */
} __ec_align4;
enum ec_vboot_hash_cmd {
- EC_VBOOT_HASH_GET = 0, /* Get current hash status */
- EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */
- EC_VBOOT_HASH_START = 2, /* Start computing a new hash */
- EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */
+ EC_VBOOT_HASH_GET = 0, /* Get current hash status */
+ EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */
+ EC_VBOOT_HASH_START = 2, /* Start computing a new hash */
+ EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */
};
enum ec_vboot_hash_type {
@@ -2493,9 +2487,9 @@
* If one of these is specified, the EC will automatically update offset and
* size to the correct values for the specified image (RO or RW).
*/
-#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe
-#define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd
-#define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc
+#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe
+#define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd
+#define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc
/*
* 'RW' is vague if there are multiple RW images; we mean the active one,
@@ -2726,16 +2720,16 @@
uint8_t sensor_num;
/* Each sensor is up to 3-axis. */
union {
- int16_t data[3];
+ int16_t data[3];
/* for sensors using unsigned data */
- uint16_t udata[3];
+ uint16_t udata[3];
struct __ec_todo_packed {
- uint16_t reserved;
- uint32_t timestamp;
+ uint16_t reserved;
+ uint32_t timestamp;
};
struct __ec_todo_unpacked {
struct ec_response_activity_data activity_data;
- int16_t add_info[2];
+ int16_t add_info[2];
};
};
} __ec_todo_packed;
@@ -2779,7 +2773,7 @@
struct ec_motion_sense_activity {
uint8_t sensor_num;
uint8_t activity; /* one of enum motionsensor_activity */
- uint8_t enable; /* 1: enable, 0: disable */
+ uint8_t enable; /* 1: enable, 0: disable */
uint8_t reserved;
uint16_t parameters[3]; /* activity dependent parameters */
} __ec_todo_unpacked;
@@ -2947,7 +2941,6 @@
uint16_t scale[3];
} sensor_scale;
-
/* Used for MOTIONSENSE_CMD_FIFO_INFO */
/* (no params) */
@@ -3031,7 +3024,7 @@
*/
struct __ec_todo_unpacked {
uint8_t sensor_num;
- uint8_t activity; /* enum motionsensor_activity */
+ uint8_t activity; /* enum motionsensor_activity */
} get_activity;
};
} __ec_todo_packed;
@@ -3132,19 +3125,19 @@
/* Current value of the parameter queried. */
int32_t ret;
} ec_rate, sensor_odr, sensor_range, kb_wake_angle,
- fifo_int_enable, spoof;
+ fifo_int_enable, spoof;
/*
* Used for MOTIONSENSE_CMD_SENSOR_OFFSET,
* PERFORM_CALIB.
*/
- struct __ec_todo_unpacked {
+ struct __ec_todo_unpacked {
int16_t temp;
int16_t offset[3];
} sensor_offset, perform_calib;
/* Used for MOTIONSENSE_CMD_SENSOR_SCALE */
- struct __ec_todo_unpacked {
+ struct __ec_todo_unpacked {
int16_t temp;
uint16_t scale[3];
} sensor_scale;
@@ -3247,8 +3240,8 @@
struct ec_params_usb_charge_set_mode {
uint8_t usb_port_id;
- uint8_t mode:7; /* enum usb_charge_mode */
- uint8_t inhibit_charge:1; /* enum usb_suspend_charge */
+ uint8_t mode : 7; /* enum usb_charge_mode */
+ uint8_t inhibit_charge : 1; /* enum usb_suspend_charge */
} __ec_align1;
/*****************************************************************************/
@@ -3275,16 +3268,16 @@
#define EC_CMD_PSTORE_READ 0x0041
struct ec_params_pstore_read {
- uint32_t offset; /* Byte offset to read */
- uint32_t size; /* Size to read in bytes */
+ uint32_t offset; /* Byte offset to read */
+ uint32_t size; /* Size to read in bytes */
} __ec_align4;
/* Write persistent storage */
#define EC_CMD_PSTORE_WRITE 0x0042
struct ec_params_pstore_write {
- uint32_t offset; /* Byte offset to write */
- uint32_t size; /* Size to write in bytes */
+ uint32_t offset; /* Byte offset to write */
+ uint32_t size; /* Size to write in bytes */
uint8_t data[EC_PSTORE_SIZE_MAX];
} __ec_align4;
@@ -3427,7 +3420,6 @@
uint16_t value;
} __ec_align2;
-
/* The version 1 structs are visible. */
enum ec_temp_thresholds {
EC_TEMP_THRESH_WARN = 0,
@@ -3462,8 +3454,8 @@
struct ec_thermal_config {
uint32_t temp_host[EC_TEMP_THRESH_COUNT]; /* levels of hotness */
uint32_t temp_host_release[EC_TEMP_THRESH_COUNT]; /* release levels */
- uint32_t temp_fan_off; /* no active cooling needed */
- uint32_t temp_fan_max; /* max active cooling needed */
+ uint32_t temp_fan_off; /* no active cooling needed */
+ uint32_t temp_fan_max; /* max active cooling needed */
} __ec_align4;
/* Version 1 - get config for one sensor. */
@@ -3543,7 +3535,6 @@
float val[0];
} __ec_align4;
-
/* Read raw TMP006 data */
#define EC_CMD_TMP006_GET_RAW 0x0055
@@ -3552,8 +3543,8 @@
} __ec_align1;
struct ec_response_tmp006_get_raw {
- int32_t t; /* In 1/100 K */
- int32_t v; /* In nV */
+ int32_t t; /* In 1/100 K */
+ int32_t v; /* In nV */
} __ec_align4;
/*****************************************************************************/
@@ -3653,17 +3644,17 @@
/* flags */
enum mkbp_config_flags {
- EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */
+ EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */
};
enum mkbp_config_valid {
- EC_MKBP_VALID_SCAN_PERIOD = BIT(0),
- EC_MKBP_VALID_POLL_TIMEOUT = BIT(1),
- EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3),
- EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4),
- EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5),
- EC_MKBP_VALID_DEBOUNCE_UP = BIT(6),
- EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7),
+ EC_MKBP_VALID_SCAN_PERIOD = BIT(0),
+ EC_MKBP_VALID_POLL_TIMEOUT = BIT(1),
+ EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3),
+ EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4),
+ EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5),
+ EC_MKBP_VALID_DEBOUNCE_UP = BIT(6),
+ EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7),
};
/*
@@ -3673,10 +3664,10 @@
* ec_{params/response}_mkbp_get_config.
*/
struct ec_mkbp_config {
- uint32_t valid_mask; /* valid fields */
- uint8_t flags; /* some flags (enum mkbp_config_flags) */
- uint8_t valid_flags; /* which flags are valid */
- uint16_t scan_period_us; /* period between start of scans */
+ uint32_t valid_mask; /* valid fields */
+ uint8_t flags; /* some flags (enum mkbp_config_flags) */
+ uint8_t valid_flags; /* which flags are valid */
+ uint16_t scan_period_us; /* period between start of scans */
/* revert to interrupt mode after no activity for this long */
uint32_t poll_timeout_us;
/*
@@ -3687,8 +3678,8 @@
uint16_t min_post_scan_delay_us;
/* delay between setting up output and waiting for it to settle */
uint16_t output_settle_us;
- uint16_t debounce_down_us; /* time for debounce on key down */
- uint16_t debounce_up_us; /* time for debounce on key up */
+ uint16_t debounce_down_us; /* time for debounce on key down */
+ uint16_t debounce_up_us; /* time for debounce on key up */
/* maximum depth to allow for fifo (0 = no keyscan output) */
uint8_t fifo_max_depth;
} __ec_align_size1;
@@ -3705,11 +3696,11 @@
#define EC_CMD_KEYSCAN_SEQ_CTRL 0x0066
enum ec_keyscan_seq_cmd {
- EC_KEYSCAN_SEQ_STATUS = 0, /* Get status information */
- EC_KEYSCAN_SEQ_CLEAR = 1, /* Clear sequence */
- EC_KEYSCAN_SEQ_ADD = 2, /* Add item to sequence */
- EC_KEYSCAN_SEQ_START = 3, /* Start running sequence */
- EC_KEYSCAN_SEQ_COLLECT = 4, /* Collect sequence summary data */
+ EC_KEYSCAN_SEQ_STATUS = 0, /* Get status information */
+ EC_KEYSCAN_SEQ_CLEAR = 1, /* Clear sequence */
+ EC_KEYSCAN_SEQ_ADD = 2, /* Add item to sequence */
+ EC_KEYSCAN_SEQ_START = 3, /* Start running sequence */
+ EC_KEYSCAN_SEQ_COLLECT = 4, /* Collect sequence summary data */
};
enum ec_collect_flags {
@@ -3717,19 +3708,19 @@
* Indicates this scan was processed by the EC. Due to timing, some
* scans may be skipped.
*/
- EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0),
+ EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0),
};
struct ec_collect_item {
- uint8_t flags; /* some flags (enum ec_collect_flags) */
+ uint8_t flags; /* some flags (enum ec_collect_flags) */
} __ec_align1;
struct ec_params_keyscan_seq_ctrl {
- uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */
+ uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */
union {
struct __ec_align1 {
- uint8_t active; /* still active */
- uint8_t num_items; /* number of items */
+ uint8_t active; /* still active */
+ uint8_t num_items; /* number of items */
/* Current item being presented */
uint8_t cur_item;
} status;
@@ -3739,11 +3730,11 @@
* start of the sequence.
*/
uint32_t time_us;
- uint8_t scan[0]; /* keyscan data */
+ uint8_t scan[0]; /* keyscan data */
} add;
struct __ec_align1 {
- uint8_t start_item; /* First item to return */
- uint8_t num_items; /* Number of items to return */
+ uint8_t start_item; /* First item to return */
+ uint8_t num_items; /* Number of items to return */
} collect;
};
} __ec_todo_packed;
@@ -3751,7 +3742,7 @@
struct ec_result_keyscan_seq_ctrl {
union {
struct __ec_todo_unpacked {
- uint8_t num_items; /* Number of items */
+ uint8_t num_items; /* Number of items */
/* Data for each item */
struct ec_collect_item item[0];
} collect;
@@ -3894,58 +3885,57 @@
/* Bit indices for buttons and switches.*/
/* Buttons */
-#define EC_MKBP_POWER_BUTTON 0
-#define EC_MKBP_VOL_UP 1
-#define EC_MKBP_VOL_DOWN 2
-#define EC_MKBP_RECOVERY 3
+#define EC_MKBP_POWER_BUTTON 0
+#define EC_MKBP_VOL_UP 1
+#define EC_MKBP_VOL_DOWN 2
+#define EC_MKBP_RECOVERY 3
/* Switches */
-#define EC_MKBP_LID_OPEN 0
-#define EC_MKBP_TABLET_MODE 1
-#define EC_MKBP_BASE_ATTACHED 2
-#define EC_MKBP_FRONT_PROXIMITY 3
+#define EC_MKBP_LID_OPEN 0
+#define EC_MKBP_TABLET_MODE 1
+#define EC_MKBP_BASE_ATTACHED 2
+#define EC_MKBP_FRONT_PROXIMITY 3
/* Run keyboard factory test scanning */
#define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068
struct ec_response_keyboard_factory_test {
- uint16_t shorted; /* Keyboard pins are shorted */
+ uint16_t shorted; /* Keyboard pins are shorted */
} __ec_align2;
/* Fingerprint events in 'fp_events' for EC_MKBP_EVENT_FINGERPRINT */
-#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF)
-#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events) & 0x0000000F)
+#define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events)&0x00FFFFFF)
+#define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events)&0x0000000F)
#define EC_MKBP_FP_ENROLL_PROGRESS_OFFSET 4
-#define EC_MKBP_FP_ENROLL_PROGRESS(fpe) (((fpe) & 0x00000FF0) \
- >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET)
+#define EC_MKBP_FP_ENROLL_PROGRESS(fpe) \
+ (((fpe)&0x00000FF0) >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET)
#define EC_MKBP_FP_MATCH_IDX_OFFSET 12
#define EC_MKBP_FP_MATCH_IDX_MASK 0x0000F000
-#define EC_MKBP_FP_MATCH_IDX(fpe) (((fpe) & EC_MKBP_FP_MATCH_IDX_MASK) \
- >> EC_MKBP_FP_MATCH_IDX_OFFSET)
-#define EC_MKBP_FP_ENROLL BIT(27)
-#define EC_MKBP_FP_MATCH BIT(28)
-#define EC_MKBP_FP_FINGER_DOWN BIT(29)
-#define EC_MKBP_FP_FINGER_UP BIT(30)
-#define EC_MKBP_FP_IMAGE_READY BIT(31)
+#define EC_MKBP_FP_MATCH_IDX(fpe) \
+ (((fpe)&EC_MKBP_FP_MATCH_IDX_MASK) >> EC_MKBP_FP_MATCH_IDX_OFFSET)
+#define EC_MKBP_FP_ENROLL BIT(27)
+#define EC_MKBP_FP_MATCH BIT(28)
+#define EC_MKBP_FP_FINGER_DOWN BIT(29)
+#define EC_MKBP_FP_FINGER_UP BIT(30)
+#define EC_MKBP_FP_IMAGE_READY BIT(31)
/* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_ENROLL is set */
-#define EC_MKBP_FP_ERR_ENROLL_OK 0
-#define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1
-#define EC_MKBP_FP_ERR_ENROLL_IMMOBILE 2
-#define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE 3
-#define EC_MKBP_FP_ERR_ENROLL_INTERNAL 5
+#define EC_MKBP_FP_ERR_ENROLL_OK 0
+#define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1
+#define EC_MKBP_FP_ERR_ENROLL_IMMOBILE 2
+#define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE 3
+#define EC_MKBP_FP_ERR_ENROLL_INTERNAL 5
/* Can be used to detect if image was usable for enrollment or not. */
-#define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK 1
+#define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK 1
/* code given by EC_MKBP_FP_ERRCODE() when EC_MKBP_FP_MATCH is set */
-#define EC_MKBP_FP_ERR_MATCH_NO 0
-#define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6
-#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7
-#define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2
-#define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4
-#define EC_MKBP_FP_ERR_MATCH_YES 1
-#define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3
+#define EC_MKBP_FP_ERR_MATCH_NO 0
+#define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6
+#define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7
+#define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2
+#define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4
+#define EC_MKBP_FP_ERR_MATCH_YES 1
+#define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3
#define EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED 5
-
#define EC_CMD_MKBP_WAKE_MASK 0x0069
enum ec_mkbp_event_mask_action {
/* Retrieve the value of a wake mask. */
@@ -4023,7 +4013,6 @@
/*****************************************************************************/
/* Host event commands */
-
/* Obsolete. New implementation should use EC_CMD_HOST_EVENT instead */
/*
* Host event mask params and response structures, shared by all of the host
@@ -4038,17 +4027,17 @@
} __ec_align4;
/* These all use ec_response_host_event_mask */
-#define EC_CMD_HOST_EVENT_GET_B 0x0087
-#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088
-#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089
+#define EC_CMD_HOST_EVENT_GET_B 0x0087
+#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088
+#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089
#define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x008D
/* These all use ec_params_host_event_mask */
-#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A
-#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B
-#define EC_CMD_HOST_EVENT_CLEAR 0x008C
+#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A
+#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B
+#define EC_CMD_HOST_EVENT_CLEAR 0x008C
#define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x008E
-#define EC_CMD_HOST_EVENT_CLEAR_B 0x008F
+#define EC_CMD_HOST_EVENT_CLEAR_B 0x008F
/*
* Unified host event programming interface - Should be used by newer versions
@@ -4060,7 +4049,6 @@
*/
struct ec_params_host_event {
-
/* Action requested by host - one of enum ec_host_event_action. */
uint8_t action;
@@ -4083,7 +4071,6 @@
*/
struct ec_response_host_event {
-
/* Mask value in case of get operation */
uint64_t value;
} __ec_align4;
@@ -4132,7 +4119,7 @@
EC_HOST_EVENT_LAZY_WAKE_MASK_S5,
};
-#define EC_CMD_HOST_EVENT 0x00A4
+#define EC_CMD_HOST_EVENT 0x00A4
/*****************************************************************************/
/* Switch commands */
@@ -4288,10 +4275,11 @@
CHARGE_CONTROL_COUNT,
};
-#define EC_CHARGE_MODE_TEXT { \
- [CHARGE_CONTROL_NORMAL] = "NORMAL", \
- [CHARGE_CONTROL_IDLE] = "IDLE", \
- [CHARGE_CONTROL_DISCHARGE] = "DISCHARGE", \
+#define EC_CHARGE_MODE_TEXT \
+ { \
+ [CHARGE_CONTROL_NORMAL] = "NORMAL", \
+ [CHARGE_CONTROL_IDLE] = "IDLE", \
+ [CHARGE_CONTROL_DISCHARGE] = "DISCHARGE", \
}
enum ec_charge_control_cmd {
@@ -4300,10 +4288,10 @@
};
struct ec_params_charge_control {
- uint32_t mode; /* enum charge_control_mode */
+ uint32_t mode; /* enum charge_control_mode */
/* Below are the fields added in V2. */
- uint8_t cmd; /* enum ec_charge_control_cmd. */
+ uint8_t cmd; /* enum ec_charge_control_cmd. */
uint8_t reserved;
/*
* Lower and upper thresholds for battery sustainer. This struct isn't
@@ -4314,15 +4302,15 @@
* lower=-1, upper=-1.
*/
struct {
- int8_t lower; /* Display SoC in percentage. */
- int8_t upper; /* Display SoC in percentage. */
+ int8_t lower; /* Display SoC in percentage. */
+ int8_t upper; /* Display SoC in percentage. */
} sustain_soc;
} __ec_align4;
/* Added in v2 */
struct ec_response_charge_control {
- uint32_t mode; /* enum charge_control_mode */
- struct { /* Battery sustainer thresholds */
+ uint32_t mode; /* enum charge_control_mode */
+ struct { /* Battery sustainer thresholds */
int8_t lower;
int8_t upper;
} sustain_soc;
@@ -4348,10 +4336,7 @@
*/
#define EC_CMD_CONSOLE_READ 0x0098
-enum ec_console_read_subcmd {
- CONSOLE_READ_NEXT = 0,
- CONSOLE_READ_RECENT
-};
+enum ec_console_read_subcmd { CONSOLE_READ_NEXT = 0, CONSOLE_READ_RECENT };
struct ec_params_console_read_v1 {
uint8_t subcmd; /* enum ec_console_read_subcmd */
@@ -4368,7 +4353,7 @@
*/
#define EC_CMD_BATTERY_CUT_OFF 0x0099
-#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0)
+#define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0)
struct ec_params_battery_cutoff {
uint8_t flags;
@@ -4390,8 +4375,8 @@
/* LDOs / FETs control. */
enum ec_ldo_state {
- EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */
- EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */
+ EC_LDO_STATE_OFF = 0, /* the LDO / FET is shut down */
+ EC_LDO_STATE_ON = 1, /* the LDO / FET is ON / providing power */
};
/*
@@ -4492,33 +4477,33 @@
#define EC_CMD_I2C_PASSTHRU 0x009E
/* Read data; if not present, message is a write */
-#define EC_I2C_FLAG_READ BIT(15)
+#define EC_I2C_FLAG_READ BIT(15)
/* Mask for address */
-#define EC_I2C_ADDR_MASK 0x3ff
+#define EC_I2C_ADDR_MASK 0x3ff
-#define EC_I2C_STATUS_NAK BIT(0) /* Transfer was not acknowledged */
-#define EC_I2C_STATUS_TIMEOUT BIT(1) /* Timeout during transfer */
+#define EC_I2C_STATUS_NAK BIT(0) /* Transfer was not acknowledged */
+#define EC_I2C_STATUS_TIMEOUT BIT(1) /* Timeout during transfer */
/* Any error */
-#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)
+#define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)
struct ec_params_i2c_passthru_msg {
- uint16_t addr_flags; /* I2C peripheral address and flags */
- uint16_t len; /* Number of bytes to read or write */
+ uint16_t addr_flags; /* I2C peripheral address and flags */
+ uint16_t len; /* Number of bytes to read or write */
} __ec_align2;
struct ec_params_i2c_passthru {
- uint8_t port; /* I2C port number */
- uint8_t num_msgs; /* Number of messages */
+ uint8_t port; /* I2C port number */
+ uint8_t num_msgs; /* Number of messages */
struct ec_params_i2c_passthru_msg msg[];
/* Data to write for all messages is concatenated here */
} __ec_align2;
struct ec_response_i2c_passthru {
- uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */
- uint8_t num_msgs; /* Number of messages processed */
- uint8_t data[]; /* Data read by messages concatenated here */
+ uint8_t i2c_status; /* Status flags (EC_I2C_STATUS_...) */
+ uint8_t num_msgs; /* Number of messages processed */
+ uint8_t data[]; /* Data read by messages concatenated here */
} __ec_align1;
/*****************************************************************************/
@@ -4528,16 +4513,16 @@
/* Reasons to start hang detection timer */
/* Power button pressed */
-#define EC_HANG_START_ON_POWER_PRESS BIT(0)
+#define EC_HANG_START_ON_POWER_PRESS BIT(0)
/* Lid closed */
-#define EC_HANG_START_ON_LID_CLOSE BIT(1)
+#define EC_HANG_START_ON_LID_CLOSE BIT(1)
- /* Lid opened */
-#define EC_HANG_START_ON_LID_OPEN BIT(2)
+/* Lid opened */
+#define EC_HANG_START_ON_LID_OPEN BIT(2)
/* Start of AP S3->S0 transition (booting or resuming from suspend) */
-#define EC_HANG_START_ON_RESUME BIT(3)
+#define EC_HANG_START_ON_RESUME BIT(3)
/* Reasons to cancel hang detection */
@@ -4545,10 +4530,10 @@
#define EC_HANG_STOP_ON_POWER_RELEASE BIT(8)
/* Any host command from AP received */
-#define EC_HANG_STOP_ON_HOST_COMMAND BIT(9)
+#define EC_HANG_STOP_ON_HOST_COMMAND BIT(9)
/* Stop on end of AP S0->S3 transition (suspending or shutting down) */
-#define EC_HANG_STOP_ON_SUSPEND BIT(10)
+#define EC_HANG_STOP_ON_SUSPEND BIT(10)
/*
* If this flag is set, all the other fields are ignored, and the hang detect
@@ -4556,14 +4541,14 @@
* without reconfiguring any of the other hang detect settings. Note that
* you must previously have configured the timeouts.
*/
-#define EC_HANG_START_NOW BIT(30)
+#define EC_HANG_START_NOW BIT(30)
/*
* If this flag is set, all the other fields are ignored (including
* EC_HANG_START_NOW). This provides the AP a way to stop the hang timer
* without reconfiguring any of the other hang detect settings.
*/
-#define EC_HANG_STOP_NOW BIT(31)
+#define EC_HANG_STOP_NOW BIT(31)
struct ec_params_hang_detect {
/* Flags; see EC_HANG_* */
@@ -4598,16 +4583,16 @@
* params, which are handled by the particular implementations.
*/
enum charge_state_params {
- CS_PARAM_CHG_VOLTAGE, /* charger voltage limit */
- CS_PARAM_CHG_CURRENT, /* charger current limit */
- CS_PARAM_CHG_INPUT_CURRENT, /* charger input current limit */
- CS_PARAM_CHG_STATUS, /* charger-specific status */
- CS_PARAM_CHG_OPTION, /* charger-specific options */
- CS_PARAM_LIMIT_POWER, /*
- * Check if power is limited due to
- * low battery and / or a weak external
- * charger. READ ONLY.
- */
+ CS_PARAM_CHG_VOLTAGE, /* charger voltage limit */
+ CS_PARAM_CHG_CURRENT, /* charger current limit */
+ CS_PARAM_CHG_INPUT_CURRENT, /* charger input current limit */
+ CS_PARAM_CHG_STATUS, /* charger-specific status */
+ CS_PARAM_CHG_OPTION, /* charger-specific options */
+ CS_PARAM_LIMIT_POWER, /*
+ * Check if power is limited due to
+ * low battery and / or a weak external
+ * charger. READ ONLY.
+ */
/* How many so far? */
CS_NUM_BASE_PARAMS,
@@ -4630,20 +4615,20 @@
};
struct ec_params_charge_state {
- uint8_t cmd; /* enum charge_state_command */
+ uint8_t cmd; /* enum charge_state_command */
union {
/* get_state has no args */
struct __ec_todo_unpacked {
- uint32_t param; /* enum charge_state_param */
+ uint32_t param; /* enum charge_state_param */
} __ec_todo_packed get_param; /* coreboot change */
struct __ec_todo_unpacked {
- uint32_t param; /* param to set */
- uint32_t value; /* value to set */
+ uint32_t param; /* param to set */
+ uint32_t value; /* value to set */
} __ec_todo_packed set_param; /* coreboot change */
};
- uint8_t chgnum; /* Version 1 supports chgnum */
+ uint8_t chgnum; /* Version 1 supports chgnum */
} __ec_todo_packed;
struct ec_response_charge_state {
@@ -4664,7 +4649,6 @@
};
} __ec_align4;
-
/*
* Set maximum battery charging current.
*/
@@ -4768,10 +4752,10 @@
#define EC_CMD_HOST_SLEEP_EVENT 0x00A9
enum host_sleep_event {
- HOST_SLEEP_EVENT_S3_SUSPEND = 1,
- HOST_SLEEP_EVENT_S3_RESUME = 2,
+ HOST_SLEEP_EVENT_S3_SUSPEND = 1,
+ HOST_SLEEP_EVENT_S3_RESUME = 2,
HOST_SLEEP_EVENT_S0IX_SUSPEND = 3,
- HOST_SLEEP_EVENT_S0IX_RESUME = 4,
+ HOST_SLEEP_EVENT_S0IX_RESUME = 4,
/* S3 suspend with additional enabled wake sources */
HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND = 5,
};
@@ -4872,13 +4856,13 @@
/* Smart battery pass-through */
/* Get / Set 16-bit smart battery registers */
-#define EC_CMD_SB_READ_WORD 0x00B0
-#define EC_CMD_SB_WRITE_WORD 0x00B1
+#define EC_CMD_SB_READ_WORD 0x00B0
+#define EC_CMD_SB_WRITE_WORD 0x00B1
/* Get / Set string smart battery parameters
* formatted as SMBUS "block".
*/
-#define EC_CMD_SB_READ_BLOCK 0x00B2
+#define EC_CMD_SB_READ_BLOCK 0x00B2
#define EC_CMD_SB_WRITE_BLOCK 0x00B3
struct ec_params_sb_rd {
@@ -4936,14 +4920,14 @@
#define EC_CMD_SB_FW_UPDATE 0x00B5
enum ec_sb_fw_update_subcmd {
- EC_SB_FW_UPDATE_PREPARE = 0x0,
- EC_SB_FW_UPDATE_INFO = 0x1, /*query sb info */
- EC_SB_FW_UPDATE_BEGIN = 0x2, /*check if protected */
- EC_SB_FW_UPDATE_WRITE = 0x3, /*check if protected */
- EC_SB_FW_UPDATE_END = 0x4,
- EC_SB_FW_UPDATE_STATUS = 0x5,
- EC_SB_FW_UPDATE_PROTECT = 0x6,
- EC_SB_FW_UPDATE_MAX = 0x7,
+ EC_SB_FW_UPDATE_PREPARE = 0x0,
+ EC_SB_FW_UPDATE_INFO = 0x1, /*query sb info */
+ EC_SB_FW_UPDATE_BEGIN = 0x2, /*check if protected */
+ EC_SB_FW_UPDATE_WRITE = 0x3, /*check if protected */
+ EC_SB_FW_UPDATE_END = 0x4,
+ EC_SB_FW_UPDATE_STATUS = 0x5,
+ EC_SB_FW_UPDATE_PROTECT = 0x6,
+ EC_SB_FW_UPDATE_MAX = 0x7,
};
#define SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE 32
@@ -4951,8 +4935,8 @@
#define SB_FW_UPDATE_CMD_INFO_SIZE 8
struct ec_sb_fw_update_header {
- uint16_t subcmd; /* enum ec_sb_fw_update_subcmd */
- uint16_t fw_id; /* firmware id */
+ uint16_t subcmd; /* enum ec_sb_fw_update_subcmd */
+ uint16_t fw_id; /* firmware id */
} __ec_align4;
struct ec_params_sb_fw_update {
@@ -4968,7 +4952,7 @@
/* EC_SB_FW_UPDATE_WRITE = 0x3 */
struct __ec_align4 {
- uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE];
+ uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE];
} write;
};
} __ec_align4;
@@ -5001,9 +4985,9 @@
int vboot_mode;
} __ec_align4;
-#define VBOOT_MODE_NORMAL 0
+#define VBOOT_MODE_NORMAL 0
#define VBOOT_MODE_DEVELOPER 1
-#define VBOOT_MODE_RECOVERY 2
+#define VBOOT_MODE_RECOVERY 2
/*****************************************************************************/
/*
@@ -5020,14 +5004,13 @@
struct ec_params_i2c_passthru_protect {
uint8_t subcmd;
- uint8_t port; /* I2C port number */
+ uint8_t port; /* I2C port number */
} __ec_align1;
struct ec_response_i2c_passthru_protect {
- uint8_t status; /* Status flags (0: unlocked, 1: locked) */
+ uint8_t status; /* Status flags (0: unlocked, 1: locked) */
} __ec_align1;
-
/*****************************************************************************/
/*
* HDMI CEC commands
@@ -5097,9 +5080,9 @@
/* Events from CEC to AP */
enum mkbp_cec_event {
/* Outgoing message was acknowledged by a follower */
- EC_MKBP_CEC_SEND_OK = BIT(0),
+ EC_MKBP_CEC_SEND_OK = BIT(0),
/* Outgoing message was not acknowledged */
- EC_MKBP_CEC_SEND_FAILED = BIT(1),
+ EC_MKBP_CEC_SEND_FAILED = BIT(1),
};
/*****************************************************************************/
@@ -5148,10 +5131,8 @@
uint8_t reserved[3];
union {
- struct ec_param_ec_codec_get_shm_addr
- get_shm_addr_param;
- struct ec_param_ec_codec_set_shm_addr
- set_shm_addr_param;
+ struct ec_param_ec_codec_get_shm_addr get_shm_addr_param;
+ struct ec_param_ec_codec_set_shm_addr set_shm_addr_param;
};
};
@@ -5206,10 +5187,8 @@
uint8_t reserved[3];
union {
- struct ec_param_ec_codec_dmic_set_gain_idx
- set_gain_idx_param;
- struct ec_param_ec_codec_dmic_get_gain_idx
- get_gain_idx_param;
+ struct ec_param_ec_codec_dmic_set_gain_idx set_gain_idx_param;
+ struct ec_param_ec_codec_dmic_get_gain_idx get_gain_idx_param;
};
};
@@ -5276,11 +5255,9 @@
union {
struct ec_param_ec_codec_i2s_rx_set_sample_depth
- set_sample_depth_param;
- struct ec_param_ec_codec_i2s_rx_set_daifmt
- set_daifmt_param;
- struct ec_param_ec_codec_i2s_rx_set_bclk
- set_bclk_param;
+ set_sample_depth_param;
+ struct ec_param_ec_codec_i2s_rx_set_daifmt set_daifmt_param;
+ struct ec_param_ec_codec_i2s_rx_set_bclk set_bclk_param;
};
};
@@ -5325,10 +5302,8 @@
uint8_t reserved[3];
union {
- struct ec_param_ec_codec_wov_set_lang
- set_lang_param;
- struct ec_param_ec_codec_wov_set_lang_shm
- set_lang_shm_param;
+ struct ec_param_ec_codec_wov_set_lang set_lang_param;
+ struct ec_param_ec_codec_wov_set_lang_shm set_lang_shm_param;
};
};
@@ -5359,8 +5334,8 @@
};
struct __ec_align1 ec_params_pse {
- uint8_t cmd; /* enum ec_pse_subcmd */
- uint8_t port; /* PSE port */
+ uint8_t cmd; /* enum ec_pse_subcmd */
+ uint8_t port; /* PSE port */
};
enum ec_pse_status {
@@ -5370,7 +5345,7 @@
};
struct __ec_align1 ec_response_pse_status {
- uint8_t status; /* enum ec_pse_status */
+ uint8_t status; /* enum ec_pse_status */
};
/*****************************************************************************/
@@ -5384,27 +5359,27 @@
/* Command */
enum ec_reboot_cmd {
- EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */
- EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */
- EC_REBOOT_JUMP_RW = 2, /* Jump to active RW without rebooting */
+ EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */
+ EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */
+ EC_REBOOT_JUMP_RW = 2, /* Jump to active RW without rebooting */
/* (command 3 was jump to RW-B) */
- EC_REBOOT_COLD = 4, /* Cold-reboot */
- EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */
- EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */
+ EC_REBOOT_COLD = 4, /* Cold-reboot */
+ EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */
+ EC_REBOOT_HIBERNATE = 6, /* Hibernate EC */
EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7, /* and clears AP_IDLE flag */
- EC_REBOOT_COLD_AP_OFF = 8, /* Cold-reboot and don't boot AP */
- EC_REBOOT_NO_OP = 9, /* Do nothing but apply the flags. */
+ EC_REBOOT_COLD_AP_OFF = 8, /* Cold-reboot and don't boot AP */
+ EC_REBOOT_NO_OP = 9, /* Do nothing but apply the flags. */
};
/* Flags for ec_params_reboot_ec.reboot_flags */
-#define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */
-#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */
-#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2) /* Switch RW slot */
-#define EC_REBOOT_FLAG_CLEAR_AP_IDLE BIT(3) /* Clear AP_IDLE flag */
+#define EC_REBOOT_FLAG_RESERVED0 BIT(0) /* Was recovery request */
+#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1) /* Reboot after AP shutdown */
+#define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2) /* Switch RW slot */
+#define EC_REBOOT_FLAG_CLEAR_AP_IDLE BIT(3) /* Clear AP_IDLE flag */
struct ec_params_reboot_ec {
- uint8_t cmd; /* enum ec_reboot_cmd */
- uint8_t flags; /* See EC_REBOOT_FLAG_* */
+ uint8_t cmd; /* enum ec_reboot_cmd */
+ uint8_t flags; /* See EC_REBOOT_FLAG_* */
} __ec_align1;
/*
@@ -5432,7 +5407,7 @@
*
* Use EC_CMD_REBOOT_EC to reboot the EC more politely.
*/
-#define EC_CMD_REBOOT 0x00D1 /* Think "die" */
+#define EC_CMD_REBOOT 0x00D1 /* Think "die" */
/*
* Resend last response (not supported on LPC).
@@ -5468,49 +5443,48 @@
enum pd_charge_state {
PD_CHARGE_NO_CHANGE = 0, /* Don't change charge state */
- PD_CHARGE_NONE, /* No charging allowed */
- PD_CHARGE_5V, /* 5V charging only */
- PD_CHARGE_MAX /* Charge at max voltage */
+ PD_CHARGE_NONE, /* No charging allowed */
+ PD_CHARGE_5V, /* 5V charging only */
+ PD_CHARGE_MAX /* Charge at max voltage */
};
/* Status of EC being sent to PD */
-#define EC_STATUS_HIBERNATING BIT(0)
+#define EC_STATUS_HIBERNATING BIT(0)
struct ec_params_pd_status {
- uint8_t status; /* EC status */
- int8_t batt_soc; /* battery state of charge */
+ uint8_t status; /* EC status */
+ int8_t batt_soc; /* battery state of charge */
uint8_t charge_state; /* charging state (from enum pd_charge_state) */
} __ec_align1;
/* Status of PD being sent back to EC */
-#define PD_STATUS_HOST_EVENT BIT(0) /* Forward host event to AP */
-#define PD_STATUS_IN_RW BIT(1) /* Running RW image */
+#define PD_STATUS_HOST_EVENT BIT(0) /* Forward host event to AP */
+#define PD_STATUS_IN_RW BIT(1) /* Running RW image */
#define PD_STATUS_JUMPED_TO_IMAGE BIT(2) /* Current image was jumped to */
-#define PD_STATUS_TCPC_ALERT_0 BIT(3) /* Alert active in port 0 TCPC */
-#define PD_STATUS_TCPC_ALERT_1 BIT(4) /* Alert active in port 1 TCPC */
-#define PD_STATUS_TCPC_ALERT_2 BIT(5) /* Alert active in port 2 TCPC */
-#define PD_STATUS_TCPC_ALERT_3 BIT(6) /* Alert active in port 3 TCPC */
-#define PD_STATUS_EC_INT_ACTIVE (PD_STATUS_TCPC_ALERT_0 | \
- PD_STATUS_TCPC_ALERT_1 | \
- PD_STATUS_HOST_EVENT)
+#define PD_STATUS_TCPC_ALERT_0 BIT(3) /* Alert active in port 0 TCPC */
+#define PD_STATUS_TCPC_ALERT_1 BIT(4) /* Alert active in port 1 TCPC */
+#define PD_STATUS_TCPC_ALERT_2 BIT(5) /* Alert active in port 2 TCPC */
+#define PD_STATUS_TCPC_ALERT_3 BIT(6) /* Alert active in port 3 TCPC */
+#define PD_STATUS_EC_INT_ACTIVE \
+ (PD_STATUS_TCPC_ALERT_0 | PD_STATUS_TCPC_ALERT_1 | PD_STATUS_HOST_EVENT)
struct ec_response_pd_status {
- uint32_t curr_lim_ma; /* input current limit */
- uint16_t status; /* PD MCU status */
- int8_t active_charge_port; /* active charging port */
+ uint32_t curr_lim_ma; /* input current limit */
+ uint16_t status; /* PD MCU status */
+ int8_t active_charge_port; /* active charging port */
} __ec_align_size1;
/* AP to PD MCU host event status command, cleared on read */
#define EC_CMD_PD_HOST_EVENT_STATUS 0x0104
/* PD MCU host event status bits */
-#define PD_EVENT_UPDATE_DEVICE BIT(0)
-#define PD_EVENT_POWER_CHANGE BIT(1)
-#define PD_EVENT_IDENTITY_RECEIVED BIT(2)
-#define PD_EVENT_DATA_SWAP BIT(3)
-#define PD_EVENT_TYPEC BIT(4)
+#define PD_EVENT_UPDATE_DEVICE BIT(0)
+#define PD_EVENT_POWER_CHANGE BIT(1)
+#define PD_EVENT_IDENTITY_RECEIVED BIT(2)
+#define PD_EVENT_DATA_SWAP BIT(3)
+#define PD_EVENT_TYPEC BIT(4)
struct ec_response_host_event_status {
- uint32_t status; /* PD MCU host event status */
+ uint32_t status; /* PD MCU host event status */
} __ec_align4;
/*
@@ -5557,17 +5531,18 @@
uint8_t swap;
} __ec_align1;
-#define PD_CTRL_RESP_ENABLED_COMMS BIT(0) /* Communication enabled */
-#define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1) /* Device connected */
+#define PD_CTRL_RESP_ENABLED_COMMS BIT(0) /* Communication enabled */
+#define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1) /* Device connected */
#define PD_CTRL_RESP_ENABLED_PD_CAPABLE BIT(2) /* Partner is PD capable */
-#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */
-#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */
-#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */
-#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */
-#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */
-#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */
-#define PD_CTRL_RESP_ROLE_UNCONSTRAINED BIT(6) /* Partner unconstrained power */
+#define PD_CTRL_RESP_ROLE_POWER BIT(0) /* 0=SNK/1=SRC */
+#define PD_CTRL_RESP_ROLE_DATA BIT(1) /* 0=UFP/1=DFP */
+#define PD_CTRL_RESP_ROLE_VCONN BIT(2) /* Vconn status */
+#define PD_CTRL_RESP_ROLE_DR_POWER BIT(3) /* Partner is dualrole power */
+#define PD_CTRL_RESP_ROLE_DR_DATA BIT(4) /* Partner is dualrole data */
+#define PD_CTRL_RESP_ROLE_USB_COMM BIT(5) /* Partner USB comm capable */
+#define PD_CTRL_RESP_ROLE_UNCONSTRAINED BIT(6) /* Partner unconstrained power \
+ */
struct ec_response_usb_pd_control {
uint8_t enabled;
@@ -5585,39 +5560,39 @@
/* Possible port partner connections based on CC line states */
enum pd_cc_states {
- PD_CC_NONE = 0, /* No port partner attached */
+ PD_CC_NONE = 0, /* No port partner attached */
/* From DFP perspective */
- PD_CC_UFP_NONE = 1, /* No UFP accessory connected */
- PD_CC_UFP_AUDIO_ACC = 2, /* UFP Audio accessory connected */
- PD_CC_UFP_DEBUG_ACC = 3, /* UFP Debug accessory connected */
- PD_CC_UFP_ATTACHED = 4, /* Plain UFP attached */
+ PD_CC_UFP_NONE = 1, /* No UFP accessory connected */
+ PD_CC_UFP_AUDIO_ACC = 2, /* UFP Audio accessory connected */
+ PD_CC_UFP_DEBUG_ACC = 3, /* UFP Debug accessory connected */
+ PD_CC_UFP_ATTACHED = 4, /* Plain UFP attached */
/* From UFP perspective */
- PD_CC_DFP_ATTACHED = 5, /* Plain DFP attached */
- PD_CC_DFP_DEBUG_ACC = 6, /* DFP debug accessory connected */
+ PD_CC_DFP_ATTACHED = 5, /* Plain DFP attached */
+ PD_CC_DFP_DEBUG_ACC = 6, /* DFP debug accessory connected */
};
/* Active/Passive Cable */
-#define USB_PD_CTRL_ACTIVE_CABLE BIT(0)
+#define USB_PD_CTRL_ACTIVE_CABLE BIT(0)
/* Optical/Non-optical cable */
-#define USB_PD_CTRL_OPTICAL_CABLE BIT(1)
+#define USB_PD_CTRL_OPTICAL_CABLE BIT(1)
/* 3rd Gen TBT device (or AMA)/2nd gen tbt Adapter */
-#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2)
+#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2)
/* Active Link Uni-Direction */
-#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3)
+#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3)
struct ec_response_usb_pd_control_v2 {
uint8_t enabled;
uint8_t role;
uint8_t polarity;
char state[32];
- uint8_t cc_state; /* enum pd_cc_states representing cc state */
- uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */
- uint8_t reserved; /* Reserved for future use */
- uint8_t control_flags; /* USB_PD_CTRL_*flags */
- uint8_t cable_speed; /* TBT_SS_* cable speed */
- uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */
+ uint8_t cc_state; /* enum pd_cc_states representing cc state */
+ uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */
+ uint8_t reserved; /* Reserved for future use */
+ uint8_t control_flags; /* USB_PD_CTRL_*flags */
+ uint8_t cable_speed; /* TBT_SS_* cable speed */
+ uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */
} __ec_align1;
#define EC_CMD_USB_PD_PORTS 0x0102
@@ -5672,7 +5647,6 @@
uint32_t max_power;
} __ec_align4;
-
/*
* This command will return the number of USB PD charge port + the number
* of dedicated port present.
@@ -5706,7 +5680,7 @@
uint16_t dev_id;
uint8_t cmd;
uint8_t port;
- uint32_t size; /* Size to write in bytes */
+ uint32_t size; /* Size to write in bytes */
/* Followed by data to write */
} __ec_align4;
@@ -5717,12 +5691,12 @@
struct ec_params_usb_pd_rw_hash_entry {
uint16_t dev_id;
uint8_t dev_rw_hash[PD_RW_HASH_SIZE];
- uint8_t reserved; /*
- * For alignment of current_image
- * TODO(rspangler) but it's not aligned!
- * Should have been reserved[2].
- */
- uint32_t current_image; /* One of ec_image */
+ uint8_t reserved; /*
+ * For alignment of current_image
+ * TODO(rspangler) but it's not aligned!
+ * Should have been reserved[2].
+ */
+ uint32_t current_image; /* One of ec_image */
} __ec_align1;
/* Read USB-PD Accessory info */
@@ -5735,8 +5709,8 @@
/* Read USB-PD Device discovery info */
#define EC_CMD_USB_PD_DISCOVERY 0x0113
struct ec_params_usb_pd_discovery_entry {
- uint16_t vid; /* USB-IF VID */
- uint16_t pid; /* USB-IF PID */
+ uint16_t vid; /* USB-IF VID */
+ uint16_t pid; /* USB-IF PID */
uint8_t ptype; /* product type (hub,periph,cable,ama) */
} __ec_align_size1;
@@ -5763,43 +5737,43 @@
struct ec_response_pd_log {
uint32_t timestamp; /* relative timestamp in milliseconds */
- uint8_t type; /* event type : see PD_EVENT_xx below */
- uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */
- uint16_t data; /* type-defined data payload */
+ uint8_t type; /* event type : see PD_EVENT_xx below */
+ uint8_t size_port; /* [7:5] port number [4:0] payload size in bytes */
+ uint16_t data; /* type-defined data payload */
uint8_t payload[0]; /* optional additional data payload: 0..16 bytes */
} __ec_align4;
/* The timestamp is the microsecond counter shifted to get about a ms. */
#define PD_LOG_TIMESTAMP_SHIFT 10 /* 1 LSB = 1024us */
-#define PD_LOG_SIZE_MASK 0x1f
-#define PD_LOG_PORT_MASK 0xe0
-#define PD_LOG_PORT_SHIFT 5
-#define PD_LOG_PORT_SIZE(port, size) (((port) << PD_LOG_PORT_SHIFT) | \
- ((size) & PD_LOG_SIZE_MASK))
+#define PD_LOG_SIZE_MASK 0x1f
+#define PD_LOG_PORT_MASK 0xe0
+#define PD_LOG_PORT_SHIFT 5
+#define PD_LOG_PORT_SIZE(port, size) \
+ (((port) << PD_LOG_PORT_SHIFT) | ((size)&PD_LOG_SIZE_MASK))
#define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT)
-#define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK)
+#define PD_LOG_SIZE(size_port) ((size_port)&PD_LOG_SIZE_MASK)
/* PD event log : entry types */
/* PD MCU events */
-#define PD_EVENT_MCU_BASE 0x00
-#define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE+0)
-#define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE+1)
+#define PD_EVENT_MCU_BASE 0x00
+#define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE + 0)
+#define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE + 1)
/* Reserved for custom board event */
-#define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE+2)
+#define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE + 2)
/* PD generic accessory events */
-#define PD_EVENT_ACC_BASE 0x20
-#define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE+0)
-#define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE+1)
+#define PD_EVENT_ACC_BASE 0x20
+#define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE + 0)
+#define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE + 1)
/* PD power supply events */
-#define PD_EVENT_PS_BASE 0x40
-#define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE+0)
+#define PD_EVENT_PS_BASE 0x40
+#define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE + 0)
/* PD video dongles events */
-#define PD_EVENT_VIDEO_BASE 0x60
-#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE+0)
-#define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE+1)
+#define PD_EVENT_VIDEO_BASE 0x60
+#define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE + 0)
+#define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE + 1)
/* Returned in the "type" field, when there is no entry available */
-#define PD_EVENT_NO_ENTRY 0xff
+#define PD_EVENT_NO_ENTRY 0xff
/*
* PD_EVENT_MCU_CHARGE event definition :
@@ -5807,24 +5781,24 @@
* the data field contains the port state flags as defined below :
*/
/* Port partner is a dual role device */
-#define CHARGE_FLAGS_DUAL_ROLE BIT(15)
+#define CHARGE_FLAGS_DUAL_ROLE BIT(15)
/* Port is the pending override port */
-#define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14)
+#define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14)
/* Port is the override port */
-#define CHARGE_FLAGS_OVERRIDE BIT(13)
+#define CHARGE_FLAGS_OVERRIDE BIT(13)
/* Charger type */
-#define CHARGE_FLAGS_TYPE_SHIFT 3
-#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT)
+#define CHARGE_FLAGS_TYPE_SHIFT 3
+#define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT)
/* Power delivery role */
-#define CHARGE_FLAGS_ROLE_MASK (7 << 0)
+#define CHARGE_FLAGS_ROLE_MASK (7 << 0)
/*
* PD_EVENT_PS_FAULT data field flags definition :
*/
-#define PS_FAULT_OCP 1
-#define PS_FAULT_FAST_OCP 2
-#define PS_FAULT_OVP 3
-#define PS_FAULT_DISCH 4
+#define PS_FAULT_OCP 1
+#define PS_FAULT_FAST_OCP 2
+#define PS_FAULT_OVP 3
+#define PS_FAULT_DISCH 4
/*
* PD_EVENT_VIDEO_CODEC payload is "struct mcdp_info".
@@ -5850,12 +5824,12 @@
#define EC_CMD_USB_PD_GET_AMODE 0x0116
struct ec_params_usb_pd_get_mode_request {
uint16_t svid_idx; /* SVID index to get */
- uint8_t port; /* port */
+ uint8_t port; /* port */
} __ec_align_size1;
struct ec_params_usb_pd_get_mode_response {
- uint16_t svid; /* SVID */
- uint16_t opos; /* Object Position */
+ uint16_t svid; /* SVID */
+ uint16_t opos; /* Object Position */
uint32_t vdo[6]; /* Mode VDOs */
} __ec_align4;
@@ -5869,10 +5843,10 @@
};
struct ec_params_usb_pd_set_mode_request {
- uint32_t cmd; /* enum pd_mode_cmd */
+ uint32_t cmd; /* enum pd_mode_cmd */
uint16_t svid; /* SVID to set */
- uint8_t opos; /* Object Position */
- uint8_t port; /* port */
+ uint8_t opos; /* Object Position */
+ uint8_t port; /* port */
} __ec_align4;
/* Ask the PD MCU to record a log of a requested type */
@@ -5883,20 +5857,19 @@
uint8_t port; /* port#, or 0 for events unrelated to a given port */
} __ec_align1;
-
/* Control USB-PD chip */
#define EC_CMD_PD_CONTROL 0x0119
enum ec_pd_control_cmd {
- PD_SUSPEND = 0, /* Suspend the PD chip (EC: stop talking to PD) */
- PD_RESUME, /* Resume the PD chip (EC: start talking to PD) */
- PD_RESET, /* Force reset the PD chip */
- PD_CONTROL_DISABLE, /* Disable further calls to this command */
- PD_CHIP_ON, /* Power on the PD chip */
+ PD_SUSPEND = 0, /* Suspend the PD chip (EC: stop talking to PD) */
+ PD_RESUME, /* Resume the PD chip (EC: start talking to PD) */
+ PD_RESET, /* Force reset the PD chip */
+ PD_CONTROL_DISABLE, /* Disable further calls to this command */
+ PD_CHIP_ON, /* Power on the PD chip */
};
struct ec_params_pd_control {
- uint8_t chip; /* chip id */
+ uint8_t chip; /* chip id */
uint8_t subcmd;
} __ec_align1;
@@ -5908,29 +5881,29 @@
} __ec_align1;
/* Flags representing mux state */
-#define USB_PD_MUX_NONE 0 /* Open switch */
-#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */
-#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */
-#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */
-#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */
-#define USB_PD_MUX_HPD_IRQ_DEASSERTED 0 /* HPD IRQ is deasserted */
-#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */
-#define USB_PD_MUX_HPD_LVL_DEASSERTED 0 /* HPD level is deasserted */
-#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */
+#define USB_PD_MUX_NONE 0 /* Open switch */
+#define USB_PD_MUX_USB_ENABLED BIT(0) /* USB connected */
+#define USB_PD_MUX_DP_ENABLED BIT(1) /* DP connected */
+#define USB_PD_MUX_POLARITY_INVERTED BIT(2) /* CC line Polarity inverted */
+#define USB_PD_MUX_HPD_IRQ BIT(3) /* HPD IRQ is asserted */
+#define USB_PD_MUX_HPD_IRQ_DEASSERTED 0 /* HPD IRQ is deasserted */
+#define USB_PD_MUX_HPD_LVL BIT(4) /* HPD level is asserted */
+#define USB_PD_MUX_HPD_LVL_DEASSERTED 0 /* HPD level is deasserted */
+#define USB_PD_MUX_SAFE_MODE BIT(5) /* DP is in safe mode */
#define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6) /* TBT compat enabled */
-#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */
+#define USB_PD_MUX_USB4_ENABLED BIT(7) /* USB4 enabled */
/* USB-C Dock connected */
-#define USB_PD_MUX_DOCK (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED)
+#define USB_PD_MUX_DOCK (USB_PD_MUX_USB_ENABLED | USB_PD_MUX_DP_ENABLED)
struct ec_response_usb_pd_mux_info {
uint8_t flags; /* USB_PD_MUX_*-encoded USB mux state */
} __ec_align1;
-#define EC_CMD_PD_CHIP_INFO 0x011B
+#define EC_CMD_PD_CHIP_INFO 0x011B
struct ec_params_pd_chip_info {
- uint8_t port; /* USB-C port number */
+ uint8_t port; /* USB-C port number */
/*
* Fetch the live chip info or hard-coded + cached chip info
* 0: hardcoded value for VID/PID, cached value for FW version
@@ -5964,18 +5937,18 @@
} __ec_align2;
/* Run RW signature verification and get status */
-#define EC_CMD_RWSIG_CHECK_STATUS 0x011C
+#define EC_CMD_RWSIG_CHECK_STATUS 0x011C
struct ec_response_rwsig_check_status {
uint32_t status;
} __ec_align4;
/* For controlling RWSIG task */
-#define EC_CMD_RWSIG_ACTION 0x011D
+#define EC_CMD_RWSIG_ACTION 0x011D
enum rwsig_action {
- RWSIG_ACTION_ABORT = 0, /* Abort RWSIG and prevent jumping */
- RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */
+ RWSIG_ACTION_ABORT = 0, /* Abort RWSIG and prevent jumping */
+ RWSIG_ACTION_CONTINUE = 1, /* Jump to RW immediately */
};
struct ec_params_rwsig_action {
@@ -5983,10 +5956,10 @@
} __ec_align4;
/* Run verification on a slot */
-#define EC_CMD_EFS_VERIFY 0x011E
+#define EC_CMD_EFS_VERIFY 0x011E
struct ec_params_efs_verify {
- uint8_t region; /* enum ec_flash_region */
+ uint8_t region; /* enum ec_flash_region */
} __ec_align1;
/*
@@ -5994,25 +5967,25 @@
* type. Integers return a uint32. Strings return a string, using the response
* size to determine how big it is.
*/
-#define EC_CMD_GET_CROS_BOARD_INFO 0x011F
+#define EC_CMD_GET_CROS_BOARD_INFO 0x011F
/*
* Write info into Cros Board Info on EEPROM. Write fails if the board has
* hardware write-protect enabled.
*/
-#define EC_CMD_SET_CROS_BOARD_INFO 0x0120
+#define EC_CMD_SET_CROS_BOARD_INFO 0x0120
enum cbi_data_tag {
CBI_TAG_BOARD_VERSION = 0, /* uint32_t or smaller */
- CBI_TAG_OEM_ID = 1, /* uint32_t or smaller */
- CBI_TAG_SKU_ID = 2, /* uint32_t or smaller */
+ CBI_TAG_OEM_ID = 1, /* uint32_t or smaller */
+ CBI_TAG_SKU_ID = 2, /* uint32_t or smaller */
CBI_TAG_DRAM_PART_NUM = 3, /* variable length ascii, nul terminated. */
- CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */
- CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */
- CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */
- CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */
+ CBI_TAG_OEM_NAME = 4, /* variable length ascii, nul terminated. */
+ CBI_TAG_MODEL_ID = 5, /* uint32_t or smaller */
+ CBI_TAG_FW_CONFIG = 6, /* uint32_t bit field */
+ CBI_TAG_PCB_SUPPLIER = 7, /* uint32_t or smaller */
/* Second Source Factory Cache */
- CBI_TAG_SSFC = 8, /* uint32_t bit field */
- CBI_TAG_REWORK_ID = 9, /* uint64_t or smaller */
+ CBI_TAG_SSFC = 8, /* uint32_t bit field */
+ CBI_TAG_REWORK_ID = 9, /* uint64_t or smaller */
CBI_TAG_COUNT,
};
@@ -6022,11 +5995,11 @@
* RELOAD: Invalidate cache and read data from EEPROM. Useful to verify
* write was successful without reboot.
*/
-#define CBI_GET_RELOAD BIT(0)
+#define CBI_GET_RELOAD BIT(0)
struct ec_params_get_cbi {
- uint32_t tag; /* enum cbi_data_tag */
- uint32_t flag; /* CBI_GET_* */
+ uint32_t tag; /* enum cbi_data_tag */
+ uint32_t flag; /* CBI_GET_* */
} __ec_align4;
/*
@@ -6037,14 +6010,14 @@
* INIT: Need to be set when creating a new CBI from scratch. All fields
* will be initialized to zero first.
*/
-#define CBI_SET_NO_SYNC BIT(0)
-#define CBI_SET_INIT BIT(1)
+#define CBI_SET_NO_SYNC BIT(0)
+#define CBI_SET_INIT BIT(1)
struct ec_params_set_cbi {
- uint32_t tag; /* enum cbi_data_tag */
- uint32_t flag; /* CBI_SET_* */
- uint32_t size; /* Data size */
- uint8_t data[]; /* For string and raw data */
+ uint32_t tag; /* enum cbi_data_tag */
+ uint32_t flag; /* CBI_SET_* */
+ uint32_t size; /* Data size */
+ uint8_t data[]; /* For string and raw data */
} __ec_align1;
/*
@@ -6053,33 +6026,36 @@
#define EC_CMD_GET_UPTIME_INFO 0x0121
/* EC reset causes */
-#define EC_RESET_FLAG_OTHER BIT(0) /* Other known reason */
-#define EC_RESET_FLAG_RESET_PIN BIT(1) /* Reset pin asserted */
-#define EC_RESET_FLAG_BROWNOUT BIT(2) /* Brownout */
-#define EC_RESET_FLAG_POWER_ON BIT(3) /* Power-on reset */
-#define EC_RESET_FLAG_WATCHDOG BIT(4) /* Watchdog timer reset */
-#define EC_RESET_FLAG_SOFT BIT(5) /* Soft reset trigger by core */
-#define EC_RESET_FLAG_HIBERNATE BIT(6) /* Wake from hibernate */
-#define EC_RESET_FLAG_RTC_ALARM BIT(7) /* RTC alarm wake */
-#define EC_RESET_FLAG_WAKE_PIN BIT(8) /* Wake pin triggered wake */
-#define EC_RESET_FLAG_LOW_BATTERY BIT(9) /* Low battery triggered wake */
-#define EC_RESET_FLAG_SYSJUMP BIT(10) /* Jumped directly to this image */
-#define EC_RESET_FLAG_HARD BIT(11) /* Hard reset from software */
-#define EC_RESET_FLAG_AP_OFF BIT(12) /* Do not power on AP */
-#define EC_RESET_FLAG_PRESERVED BIT(13) /* Some reset flags preserved from
- * previous boot
- */
-#define EC_RESET_FLAG_USB_RESUME BIT(14) /* USB resume triggered wake */
-#define EC_RESET_FLAG_RDD BIT(15) /* USB Type-C debug cable */
-#define EC_RESET_FLAG_RBOX BIT(16) /* Fixed Reset Functionality */
-#define EC_RESET_FLAG_SECURITY BIT(17) /* Security threat */
-#define EC_RESET_FLAG_AP_WATCHDOG BIT(18) /* AP experienced a watchdog reset */
-#define EC_RESET_FLAG_STAY_IN_RO BIT(19) /* Do not select RW in EFS. This
- * enables PD in RO for Chromebox.
- */
-#define EC_RESET_FLAG_EFS BIT(20) /* Jumped to this image by EFS */
-#define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */
-#define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */
+#define EC_RESET_FLAG_OTHER BIT(0) /* Other known reason */
+#define EC_RESET_FLAG_RESET_PIN BIT(1) /* Reset pin asserted */
+#define EC_RESET_FLAG_BROWNOUT BIT(2) /* Brownout */
+#define EC_RESET_FLAG_POWER_ON BIT(3) /* Power-on reset */
+#define EC_RESET_FLAG_WATCHDOG BIT(4) /* Watchdog timer reset */
+#define EC_RESET_FLAG_SOFT BIT(5) /* Soft reset trigger by core */
+#define EC_RESET_FLAG_HIBERNATE BIT(6) /* Wake from hibernate */
+#define EC_RESET_FLAG_RTC_ALARM BIT(7) /* RTC alarm wake */
+#define EC_RESET_FLAG_WAKE_PIN BIT(8) /* Wake pin triggered wake */
+#define EC_RESET_FLAG_LOW_BATTERY BIT(9) /* Low battery triggered wake */
+#define EC_RESET_FLAG_SYSJUMP BIT(10) /* Jumped directly to this image */
+#define EC_RESET_FLAG_HARD BIT(11) /* Hard reset from software */
+#define EC_RESET_FLAG_AP_OFF BIT(12) /* Do not power on AP */
+#define EC_RESET_FLAG_PRESERVED \
+ BIT(13) /* Some reset flags preserved from \
+ * previous boot \
+ */
+#define EC_RESET_FLAG_USB_RESUME BIT(14) /* USB resume triggered wake */
+#define EC_RESET_FLAG_RDD BIT(15) /* USB Type-C debug cable */
+#define EC_RESET_FLAG_RBOX BIT(16) /* Fixed Reset Functionality */
+#define EC_RESET_FLAG_SECURITY BIT(17) /* Security threat */
+#define EC_RESET_FLAG_AP_WATCHDOG BIT(18) /* AP experienced a watchdog reset \
+ */
+#define EC_RESET_FLAG_STAY_IN_RO \
+ BIT(19) /* Do not select RW in EFS. This \
+ * enables PD in RO for Chromebox. \
+ */
+#define EC_RESET_FLAG_EFS BIT(20) /* Jumped to this image by EFS */
+#define EC_RESET_FLAG_AP_IDLE BIT(21) /* Leave alone AP */
+#define EC_RESET_FLAG_INITIAL_PWR BIT(22) /* EC had power, then was reset */
/*
* Reason codes used by the AP after a shutdown to figure out why it was reset
@@ -6147,7 +6123,6 @@
CHIPSET_SHUTDOWN_COUNT, /* End of shutdown reasons. */
};
-
struct ec_response_uptime_info {
/*
* Number of milliseconds since the last EC boot. Sysjump resets
@@ -6196,7 +6171,7 @@
* Depending on the chip, the operation may take a long time (e.g. to erase
* flash), so the commands are asynchronous.
*/
-#define EC_CMD_ADD_ENTROPY 0x0122
+#define EC_CMD_ADD_ENTROPY 0x0122
enum add_entropy_action {
/* Add entropy to the current secret. */
@@ -6218,7 +6193,7 @@
/*
* Perform a single read of a given ADC channel.
*/
-#define EC_CMD_ADC_READ 0x0123
+#define EC_CMD_ADC_READ 0x0123
struct ec_params_adc_read {
uint8_t adc_channel;
@@ -6231,7 +6206,7 @@
/*
* Read back rollback info
*/
-#define EC_CMD_ROLLBACK_INFO 0x0124
+#define EC_CMD_ROLLBACK_INFO 0x0124
struct ec_response_rollback_info {
int32_t id; /* Incrementing number to indicate which region to use. */
@@ -6239,7 +6214,6 @@
int32_t rw_rollback_version;
} __ec_align4;
-
/* Issue AP reset */
#define EC_CMD_AP_RESET 0x0125
@@ -6268,23 +6242,22 @@
};
struct ec_i2c_info {
- uint16_t port; /* Physical port for device */
- uint16_t addr_flags; /* 7-bit (or 10-bit) address */
+ uint16_t port; /* Physical port for device */
+ uint16_t addr_flags; /* 7-bit (or 10-bit) address */
};
struct ec_params_locate_chip {
- uint8_t type; /* enum ec_chip_type */
- uint8_t index; /* Specifies one instance of chip type */
+ uint8_t type; /* enum ec_chip_type */
+ uint8_t index; /* Specifies one instance of chip type */
/* Used for type specific parameters in future */
union {
uint16_t reserved;
};
} __ec_align2;
-
struct ec_response_locate_chip {
- uint8_t bus_type; /* enum ec_bus_type */
- uint8_t reserved; /* Aligning the following union to 2 bytes */
+ uint8_t bus_type; /* enum ec_bus_type */
+ uint8_t reserved; /* Aligning the following union to 2 bytes */
union {
struct ec_i2c_info i2c_info;
};
@@ -6355,27 +6328,27 @@
* left side, while BACK_LEFT means the leftmost port on the back of the
* device.
*/
- EC_PD_PORT_LOCATION_LEFT = 1,
- EC_PD_PORT_LOCATION_RIGHT = 2,
- EC_PD_PORT_LOCATION_BACK = 3,
- EC_PD_PORT_LOCATION_FRONT = 4,
- EC_PD_PORT_LOCATION_LEFT_FRONT = 5,
- EC_PD_PORT_LOCATION_LEFT_BACK = 6,
+ EC_PD_PORT_LOCATION_LEFT = 1,
+ EC_PD_PORT_LOCATION_RIGHT = 2,
+ EC_PD_PORT_LOCATION_BACK = 3,
+ EC_PD_PORT_LOCATION_FRONT = 4,
+ EC_PD_PORT_LOCATION_LEFT_FRONT = 5,
+ EC_PD_PORT_LOCATION_LEFT_BACK = 6,
EC_PD_PORT_LOCATION_RIGHT_FRONT = 7,
- EC_PD_PORT_LOCATION_RIGHT_BACK = 8,
- EC_PD_PORT_LOCATION_BACK_LEFT = 9,
- EC_PD_PORT_LOCATION_BACK_RIGHT = 10,
+ EC_PD_PORT_LOCATION_RIGHT_BACK = 8,
+ EC_PD_PORT_LOCATION_BACK_LEFT = 9,
+ EC_PD_PORT_LOCATION_BACK_RIGHT = 10,
};
struct ec_params_get_pd_port_caps {
- uint8_t port; /* Which port to interrogate */
+ uint8_t port; /* Which port to interrogate */
} __ec_align1;
struct ec_response_get_pd_port_caps {
- uint8_t pd_power_role_cap; /* enum ec_pd_power_role_caps */
- uint8_t pd_try_power_role_cap; /* enum ec_pd_try_power_role_caps */
- uint8_t pd_data_role_cap; /* enum ec_pd_data_role_caps */
- uint8_t pd_port_location; /* enum ec_pd_port_location */
+ uint8_t pd_power_role_cap; /* enum ec_pd_power_role_caps */
+ uint8_t pd_try_power_role_cap; /* enum ec_pd_try_power_role_caps */
+ uint8_t pd_data_role_cap; /* enum ec_pd_data_role_caps */
+ uint8_t pd_port_location; /* enum ec_pd_port_location */
} __ec_align1;
/*****************************************************************************/
@@ -6392,25 +6365,25 @@
struct ec_params_button {
/* Button mask aligned to enum keyboard_button_type */
- uint32_t btn_mask;
+ uint32_t btn_mask;
/* Duration in milliseconds button needs to be pressed */
- uint32_t press_ms;
+ uint32_t press_ms;
} __ec_align1;
enum keyboard_button_type {
- KEYBOARD_BUTTON_POWER = 0,
+ KEYBOARD_BUTTON_POWER = 0,
KEYBOARD_BUTTON_VOLUME_DOWN = 1,
- KEYBOARD_BUTTON_VOLUME_UP = 2,
- KEYBOARD_BUTTON_RECOVERY = 3,
- KEYBOARD_BUTTON_CAPSENSE_1 = 4,
- KEYBOARD_BUTTON_CAPSENSE_2 = 5,
- KEYBOARD_BUTTON_CAPSENSE_3 = 6,
- KEYBOARD_BUTTON_CAPSENSE_4 = 7,
- KEYBOARD_BUTTON_CAPSENSE_5 = 8,
- KEYBOARD_BUTTON_CAPSENSE_6 = 9,
- KEYBOARD_BUTTON_CAPSENSE_7 = 10,
- KEYBOARD_BUTTON_CAPSENSE_8 = 11,
+ KEYBOARD_BUTTON_VOLUME_UP = 2,
+ KEYBOARD_BUTTON_RECOVERY = 3,
+ KEYBOARD_BUTTON_CAPSENSE_1 = 4,
+ KEYBOARD_BUTTON_CAPSENSE_2 = 5,
+ KEYBOARD_BUTTON_CAPSENSE_3 = 6,
+ KEYBOARD_BUTTON_CAPSENSE_4 = 7,
+ KEYBOARD_BUTTON_CAPSENSE_5 = 8,
+ KEYBOARD_BUTTON_CAPSENSE_6 = 9,
+ KEYBOARD_BUTTON_CAPSENSE_7 = 10,
+ KEYBOARD_BUTTON_CAPSENSE_8 = 11,
KEYBOARD_BUTTON_COUNT
};
@@ -6466,15 +6439,15 @@
* action keys. This is possible for e.g. if the keyboard has a
* dedicated Fn key.
*/
-#define KEYBD_CAP_FUNCTION_KEYS BIT(0)
+#define KEYBD_CAP_FUNCTION_KEYS BIT(0)
/*
* Whether the keyboard has a dedicated numeric keyboard.
*/
-#define KEYBD_CAP_NUMERIC_KEYPAD BIT(1)
+#define KEYBD_CAP_NUMERIC_KEYPAD BIT(1)
/*
* Whether the keyboard has a screenlock key.
*/
-#define KEYBD_CAP_SCRNLOCK_KEY BIT(2)
+#define KEYBD_CAP_SCRNLOCK_KEY BIT(2)
struct ec_response_keybd_config {
/*
@@ -6501,12 +6474,12 @@
*/
#define EC_CMD_SMART_DISCHARGE 0x012B
-#define EC_SMART_DISCHARGE_FLAGS_SET BIT(0)
+#define EC_SMART_DISCHARGE_FLAGS_SET BIT(0)
/* Discharge rates when the system is in cutoff or hibernation. */
struct discharge_rate {
- uint16_t cutoff; /* Discharge rate (uA) in cutoff */
- uint16_t hibern; /* Discharge rate (uA) in hibernation */
+ uint16_t cutoff; /* Discharge rate (uA) in cutoff */
+ uint16_t hibern; /* Discharge rate (uA) in hibernation */
};
struct smart_discharge_zone {
@@ -6517,7 +6490,7 @@
};
struct ec_params_smart_discharge {
- uint8_t flags; /* EC_SMART_DISCHARGE_FLAGS_* */
+ uint8_t flags; /* EC_SMART_DISCHARGE_FLAGS_* */
/*
* Desired hours for the battery to survive before reaching 0%. Set to
* zero to disable smart discharging. That is, the system hibernates as
@@ -6642,13 +6615,13 @@
struct svid_mode_info {
uint16_t svid;
- uint16_t mode_count; /* Number of modes partner sent */
+ uint16_t mode_count; /* Number of modes partner sent */
uint32_t mode_vdo[6]; /* Max VDOs allowed after VDM header is 6 */
};
struct ec_response_typec_discovery {
- uint8_t identity_count; /* Number of identity VDOs partner sent */
- uint8_t svid_count; /* Number of SVIDs partner sent */
+ uint8_t identity_count; /* Number of identity VDOs partner sent */
+ uint8_t svid_count; /* Number of SVIDs partner sent */
uint16_t reserved;
uint32_t discovery_vdo[6]; /* Max VDOs allowed after VDM header is 6 */
struct svid_mode_info svids[0];
@@ -6679,13 +6652,13 @@
};
struct typec_usb_mux_set {
- uint8_t mux_index; /* Index of the mux to set in the chain */
- uint8_t mux_flags; /* USB_PD_MUX_*-encoded USB mux state to set */
+ uint8_t mux_index; /* Index of the mux to set in the chain */
+ uint8_t mux_flags; /* USB_PD_MUX_*-encoded USB mux state to set */
} __ec_align1;
struct ec_params_typec_control {
uint8_t port;
- uint8_t command; /* enum typec_control_command */
+ uint8_t command; /* enum typec_control_command */
uint16_t reserved;
/*
@@ -6725,10 +6698,7 @@
* the Power Delivery Specification Revision 3.0 (See
* 6.2.1.1.4 Port Power Role).
*/
-enum pd_power_role {
- PD_ROLE_SINK = 0,
- PD_ROLE_SOURCE = 1
-};
+enum pd_power_role { PD_ROLE_SINK = 0, PD_ROLE_SOURCE = 1 };
/*
* Data role.
@@ -6777,20 +6747,20 @@
POLARITY_COUNT
};
-#define MODE_DP_PIN_A BIT(0)
-#define MODE_DP_PIN_B BIT(1)
-#define MODE_DP_PIN_C BIT(2)
-#define MODE_DP_PIN_D BIT(3)
-#define MODE_DP_PIN_E BIT(4)
-#define MODE_DP_PIN_F BIT(5)
-#define MODE_DP_PIN_ALL GENMASK(5, 0)
+#define MODE_DP_PIN_A BIT(0)
+#define MODE_DP_PIN_B BIT(1)
+#define MODE_DP_PIN_C BIT(2)
+#define MODE_DP_PIN_D BIT(3)
+#define MODE_DP_PIN_E BIT(4)
+#define MODE_DP_PIN_F BIT(5)
+#define MODE_DP_PIN_ALL GENMASK(5, 0)
-#define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0)
-#define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1)
-#define PD_STATUS_EVENT_HARD_RESET BIT(2)
-#define PD_STATUS_EVENT_DISCONNECTED BIT(3)
-#define PD_STATUS_EVENT_MUX_0_SET_DONE BIT(4)
-#define PD_STATUS_EVENT_MUX_1_SET_DONE BIT(5)
+#define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0)
+#define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1)
+#define PD_STATUS_EVENT_HARD_RESET BIT(2)
+#define PD_STATUS_EVENT_DISCONNECTED BIT(3)
+#define PD_STATUS_EVENT_MUX_0_SET_DONE BIT(4)
+#define PD_STATUS_EVENT_MUX_1_SET_DONE BIT(5)
/*
* Encode and decode for BCD revision response
@@ -6799,9 +6769,9 @@
* Specification Revision from the PD header, which currently only maps to PD
* 1.0-3.0 with the major revision being one greater than the binary value.
*/
-#define PD_STATUS_REV_SET_MAJOR(r) ((r + 1) << 12)
-#define PD_STATUS_REV_GET_MAJOR(r) ((r >> 12) & 0xF)
-#define PD_STATUS_REV_GET_MINOR(r) ((r >> 8) & 0xF)
+#define PD_STATUS_REV_SET_MAJOR(r) ((r + 1) << 12)
+#define PD_STATUS_REV_GET_MAJOR(r) ((r >> 12) & 0xF)
+#define PD_STATUS_REV_GET_MINOR(r) ((r >> 8) & 0xF)
/*
* Decode helpers for Source and Sink Capability PDOs
@@ -6809,11 +6779,11 @@
* Note: The Power Delivery Specification should be considered the ultimate
* source of truth on the decoding of these PDOs
*/
-#define PDO_TYPE_FIXED (0 << 30)
-#define PDO_TYPE_BATTERY (1 << 30)
-#define PDO_TYPE_VARIABLE (2 << 30)
+#define PDO_TYPE_FIXED (0 << 30)
+#define PDO_TYPE_BATTERY (1 << 30)
+#define PDO_TYPE_VARIABLE (2 << 30)
#define PDO_TYPE_AUGMENTED (3 << 30)
-#define PDO_TYPE_MASK (3 << 30)
+#define PDO_TYPE_MASK (3 << 30)
/*
* From Table 6-9 and Table 6-14 PD Rev 3.0 Ver 2.0
@@ -6828,13 +6798,13 @@
* <19:10> : Voltage in 50mV Units
* <9:0> : Maximum Current in 10mA units
*/
-#define PDO_FIXED_DUAL_ROLE BIT(29)
-#define PDO_FIXED_UNCONSTRAINED BIT(27)
-#define PDO_FIXED_COMM_CAP BIT(26)
-#define PDO_FIXED_DATA_SWAP BIT(25)
+#define PDO_FIXED_DUAL_ROLE BIT(29)
+#define PDO_FIXED_UNCONSTRAINED BIT(27)
+#define PDO_FIXED_COMM_CAP BIT(26)
+#define PDO_FIXED_DATA_SWAP BIT(25)
#define PDO_FIXED_FRS_CURR_MASK GENMASK(24, 23) /* Sink Cap only */
-#define PDO_FIXED_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50)
-#define PDO_FIXED_CURRENT(p) ((p & 0x3FF) * 10)
+#define PDO_FIXED_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50)
+#define PDO_FIXED_CURRENT(p) ((p & 0x3FF) * 10)
/*
* From Table 6-12 and Table 6-16 PD Rev 3.0 Ver 2.0
@@ -6844,9 +6814,9 @@
* <19:10> : Minimum Voltage in 50mV units
* <9:0> : Maximum Allowable Power in 250mW units
*/
-#define PDO_BATT_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50)
-#define PDO_BATT_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50)
-#define PDO_BATT_MAX_POWER(p) ((p & 0x3FF) * 250)
+#define PDO_BATT_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50)
+#define PDO_BATT_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50)
+#define PDO_BATT_MAX_POWER(p) ((p & 0x3FF) * 250)
/*
* From Table 6-11 and Table 6-15 PD Rev 3.0 Ver 2.0
@@ -6856,9 +6826,9 @@
* <19:10> : Minimum Voltage in 50mV units
* <9:0> : Operational Current in 10mA units
*/
-#define PDO_VAR_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50)
-#define PDO_VAR_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50)
-#define PDO_VAR_MAX_CURRENT(p) ((p & 0x3FF) * 10)
+#define PDO_VAR_MAX_VOLTAGE(p) ((p >> 20 & 0x3FF) * 50)
+#define PDO_VAR_MIN_VOLTAGE(p) ((p >> 10 & 0x3FF) * 50)
+#define PDO_VAR_MAX_CURRENT(p) ((p & 0x3FF) * 10)
/*
* From Table 6-13 and Table 6-17 PD Rev 3.0 Ver 2.0
@@ -6876,33 +6846,33 @@
* <7> : Reserved
* <6:0> : Maximum Current in 50mA increments
*/
-#define PDO_AUG_MAX_VOLTAGE(p) ((p >> 17 & 0xFF) * 100)
-#define PDO_AUG_MIN_VOLTAGE(p) ((p >> 8 & 0xFF) * 100)
-#define PDO_AUG_MAX_CURRENT(p) ((p & 0x7F) * 50)
+#define PDO_AUG_MAX_VOLTAGE(p) ((p >> 17 & 0xFF) * 100)
+#define PDO_AUG_MIN_VOLTAGE(p) ((p >> 8 & 0xFF) * 100)
+#define PDO_AUG_MAX_CURRENT(p) ((p & 0x7F) * 50)
struct ec_params_typec_status {
uint8_t port;
} __ec_align1;
struct ec_response_typec_status {
- uint8_t pd_enabled; /* PD communication enabled - bool */
- uint8_t dev_connected; /* Device connected - bool */
- uint8_t sop_connected; /* Device is SOP PD capable - bool */
- uint8_t source_cap_count; /* Number of Source Cap PDOs */
+ uint8_t pd_enabled; /* PD communication enabled - bool */
+ uint8_t dev_connected; /* Device connected - bool */
+ uint8_t sop_connected; /* Device is SOP PD capable - bool */
+ uint8_t source_cap_count; /* Number of Source Cap PDOs */
- uint8_t power_role; /* enum pd_power_role */
- uint8_t data_role; /* enum pd_data_role */
- uint8_t vconn_role; /* enum pd_vconn_role */
- uint8_t sink_cap_count; /* Number of Sink Cap PDOs */
+ uint8_t power_role; /* enum pd_power_role */
+ uint8_t data_role; /* enum pd_data_role */
+ uint8_t vconn_role; /* enum pd_vconn_role */
+ uint8_t sink_cap_count; /* Number of Sink Cap PDOs */
- uint8_t polarity; /* enum tcpc_cc_polarity */
- uint8_t cc_state; /* enum pd_cc_states */
- uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */
- uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */
+ uint8_t polarity; /* enum tcpc_cc_polarity */
+ uint8_t cc_state; /* enum pd_cc_states */
+ uint8_t dp_pin; /* DP pin mode (MODE_DP_IN_[A-E]) */
+ uint8_t mux_state; /* USB_PD_MUX* - encoded mux state */
- char tc_state[32]; /* TC state name */
+ char tc_state[32]; /* TC state name */
- uint32_t events; /* PD_STATUS_EVENT bitmask */
+ uint32_t events; /* PD_STATUS_EVENT bitmask */
/*
* BCD PD revisions for partners
@@ -6917,9 +6887,9 @@
uint16_t sop_revision;
uint16_t sop_prime_revision;
- uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */
+ uint32_t source_cap_pdos[7]; /* Max 7 PDOs can be present */
- uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */
+ uint32_t sink_cap_pdos[7]; /* Max 7 PDOs can be present */
} __ec_align1;
/**
@@ -6943,8 +6913,8 @@
} __ec_align1;
struct ec_response_pchg {
- uint32_t error; /* enum pchg_error */
- uint8_t state; /* enum pchg_state state */
+ uint32_t error; /* enum pchg_error */
+ uint8_t state; /* enum pchg_state state */
uint8_t battery_percentage;
uint8_t unused0;
uint8_t unused1;
@@ -6954,8 +6924,8 @@
} __ec_align4;
struct ec_response_pchg_v2 {
- uint32_t error; /* enum pchg_error */
- uint8_t state; /* enum pchg_state state */
+ uint32_t error; /* enum pchg_error */
+ uint8_t state; /* enum pchg_state state */
uint8_t battery_percentage;
uint8_t unused0;
uint8_t unused1;
@@ -6989,16 +6959,16 @@
PCHG_STATE_COUNT,
};
-#define EC_PCHG_STATE_TEXT { \
- [PCHG_STATE_RESET] = "RESET", \
- [PCHG_STATE_INITIALIZED] = "INITIALIZED", \
- [PCHG_STATE_ENABLED] = "ENABLED", \
- [PCHG_STATE_DETECTED] = "DETECTED", \
- [PCHG_STATE_CHARGING] = "CHARGING", \
- [PCHG_STATE_FULL] = "FULL", \
- [PCHG_STATE_DOWNLOAD] = "DOWNLOAD", \
- [PCHG_STATE_DOWNLOADING] = "DOWNLOADING", \
- [PCHG_STATE_CONNECTED] = "CONNECTED", \
+#define EC_PCHG_STATE_TEXT \
+ { \
+ [PCHG_STATE_RESET] = "RESET", \
+ [PCHG_STATE_INITIALIZED] = "INITIALIZED", \
+ [PCHG_STATE_ENABLED] = "ENABLED", \
+ [PCHG_STATE_DETECTED] = "DETECTED", \
+ [PCHG_STATE_CHARGING] = "CHARGING", \
+ [PCHG_STATE_FULL] = "FULL", [PCHG_STATE_DOWNLOAD] = "DOWNLOAD", \
+ [PCHG_STATE_DOWNLOADING] = "DOWNLOADING", \
+ [PCHG_STATE_CONNECTED] = "CONNECTED", \
}
/**
@@ -7007,19 +6977,18 @@
#define EC_CMD_PCHG_UPDATE 0x0136
/* Port number is encoded in bit[28:31]. */
-#define EC_MKBP_PCHG_PORT_SHIFT 28
+#define EC_MKBP_PCHG_PORT_SHIFT 28
/* Utility macros for converting MKBP event <-> port number. */
-#define EC_MKBP_PCHG_EVENT_TO_PORT(e) (((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf)
-#define EC_MKBP_PCHG_PORT_TO_EVENT(p) ((p) << EC_MKBP_PCHG_PORT_SHIFT)
+#define EC_MKBP_PCHG_EVENT_TO_PORT(e) (((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf)
+#define EC_MKBP_PCHG_PORT_TO_EVENT(p) ((p) << EC_MKBP_PCHG_PORT_SHIFT)
/* Utility macro for extracting event bits. */
-#define EC_MKBP_PCHG_EVENT_MASK(e) ((e) \
- & GENMASK(EC_MKBP_PCHG_PORT_SHIFT-1, 0))
+#define EC_MKBP_PCHG_EVENT_MASK(e) ((e)&GENMASK(EC_MKBP_PCHG_PORT_SHIFT - 1, 0))
-#define EC_MKBP_PCHG_UPDATE_OPENED BIT(0)
-#define EC_MKBP_PCHG_WRITE_COMPLETE BIT(1)
-#define EC_MKBP_PCHG_UPDATE_CLOSED BIT(2)
-#define EC_MKBP_PCHG_UPDATE_ERROR BIT(3)
-#define EC_MKBP_PCHG_DEVICE_EVENT BIT(4)
+#define EC_MKBP_PCHG_UPDATE_OPENED BIT(0)
+#define EC_MKBP_PCHG_WRITE_COMPLETE BIT(1)
+#define EC_MKBP_PCHG_UPDATE_CLOSED BIT(2)
+#define EC_MKBP_PCHG_UPDATE_ERROR BIT(3)
+#define EC_MKBP_PCHG_DEVICE_EVENT BIT(4)
enum ec_pchg_update_cmd {
/* Reset chip to normal mode. */
@@ -7054,28 +7023,26 @@
uint8_t data[];
} __ec_align4;
-BUILD_ASSERT(EC_PCHG_UPDATE_CMD_COUNT
- < BIT(sizeof(((struct ec_params_pchg_update *)0)->cmd)*8));
+BUILD_ASSERT(EC_PCHG_UPDATE_CMD_COUNT <
+ BIT(sizeof(((struct ec_params_pchg_update *)0)->cmd) * 8));
struct ec_response_pchg_update {
/* Block size */
uint32_t block_size;
} __ec_align4;
-
#define EC_CMD_DISPLAY_SOC 0x0137
struct ec_response_display_soc {
- int16_t display_soc; /* Display charge in 10ths of a % (1000=100.0%) */
- int16_t full_factor; /* Full factor in 10ths of a % (1000=100.0%) */
+ int16_t display_soc; /* Display charge in 10ths of a % (1000=100.0%) */
+ int16_t full_factor; /* Full factor in 10ths of a % (1000=100.0%) */
int16_t shutdown_soc; /* Shutdown SoC in 10ths of a % (1000=100.0%) */
} __ec_align2;
-
#define EC_CMD_SET_BASE_STATE 0x0138
struct ec_params_set_base_state {
- uint8_t cmd; /* enum ec_set_base_state_cmd */
+ uint8_t cmd; /* enum ec_set_base_state_cmd */
} __ec_align1;
enum ec_set_base_state_cmd {
@@ -7096,8 +7063,8 @@
#define EC_I2C_CONTROL_SPEED_UNKNOWN 0
struct ec_params_i2c_control {
- uint8_t port; /* I2C port number */
- uint8_t cmd; /* enum ec_i2c_control_command */
+ uint8_t port; /* I2C port number */
+ uint8_t cmd; /* enum ec_i2c_control_command */
union {
uint16_t speed_khz;
} cmd_params;
@@ -7109,12 +7076,12 @@
} cmd_response;
} __ec_align_size1;
-#define EC_CMD_RGBKBD_SET_COLOR 0x013A
-#define EC_CMD_RGBKBD 0x013B
+#define EC_CMD_RGBKBD_SET_COLOR 0x013A
+#define EC_CMD_RGBKBD 0x013B
-#define EC_RGBKBD_MAX_KEY_COUNT 128
-#define EC_RGBKBD_MAX_RGB_COLOR 0xFFFFFF
-#define EC_RGBKBD_MAX_SCALE 0xFF
+#define EC_RGBKBD_MAX_KEY_COUNT 128
+#define EC_RGBKBD_MAX_RGB_COLOR 0xFFFFFF
+#define EC_RGBKBD_MAX_SCALE 0xFF
enum rgbkbd_state {
/* RGB keyboard is reset and not initialized. */
@@ -7152,10 +7119,10 @@
};
struct ec_params_rgbkbd {
- uint8_t subcmd; /* Sub-command (enum ec_rgbkbd_subcmd) */
+ uint8_t subcmd; /* Sub-command (enum ec_rgbkbd_subcmd) */
union {
- struct rgb_s color; /* EC_RGBKBD_SUBCMD_CLEAR */
- uint8_t demo; /* EC_RGBKBD_SUBCMD_DEMO */
+ struct rgb_s color; /* EC_RGBKBD_SUBCMD_CLEAR */
+ uint8_t demo; /* EC_RGBKBD_SUBCMD_DEMO */
struct ec_rgbkbd_set_scale set_scale;
};
} __ec_align1;
@@ -7188,49 +7155,44 @@
#define EC_FP_FLAG_NOT_COMPLETE 0x1
struct ec_params_fp_passthru {
- uint16_t len; /* Number of bytes to write then read */
- uint16_t flags; /* EC_FP_FLAG_xxx */
- uint8_t data[]; /* Data to send */
+ uint16_t len; /* Number of bytes to write then read */
+ uint16_t flags; /* EC_FP_FLAG_xxx */
+ uint8_t data[]; /* Data to send */
} __ec_align2;
/* Configure the Fingerprint MCU behavior */
#define EC_CMD_FP_MODE 0x0402
/* Put the sensor in its lowest power mode */
-#define FP_MODE_DEEPSLEEP BIT(0)
+#define FP_MODE_DEEPSLEEP BIT(0)
/* Wait to see a finger on the sensor */
-#define FP_MODE_FINGER_DOWN BIT(1)
+#define FP_MODE_FINGER_DOWN BIT(1)
/* Poll until the finger has left the sensor */
-#define FP_MODE_FINGER_UP BIT(2)
+#define FP_MODE_FINGER_UP BIT(2)
/* Capture the current finger image */
-#define FP_MODE_CAPTURE BIT(3)
+#define FP_MODE_CAPTURE BIT(3)
/* Finger enrollment session on-going */
#define FP_MODE_ENROLL_SESSION BIT(4)
/* Enroll the current finger image */
-#define FP_MODE_ENROLL_IMAGE BIT(5)
+#define FP_MODE_ENROLL_IMAGE BIT(5)
/* Try to match the current finger image */
-#define FP_MODE_MATCH BIT(6)
+#define FP_MODE_MATCH BIT(6)
/* Reset and re-initialize the sensor. */
-#define FP_MODE_RESET_SENSOR BIT(7)
+#define FP_MODE_RESET_SENSOR BIT(7)
/* Sensor maintenance for dead pixels. */
#define FP_MODE_SENSOR_MAINTENANCE BIT(8)
/* special value: don't change anything just read back current mode */
-#define FP_MODE_DONT_CHANGE BIT(31)
+#define FP_MODE_DONT_CHANGE BIT(31)
-#define FP_VALID_MODES (FP_MODE_DEEPSLEEP | \
- FP_MODE_FINGER_DOWN | \
- FP_MODE_FINGER_UP | \
- FP_MODE_CAPTURE | \
- FP_MODE_ENROLL_SESSION | \
- FP_MODE_ENROLL_IMAGE | \
- FP_MODE_MATCH | \
- FP_MODE_RESET_SENSOR | \
- FP_MODE_SENSOR_MAINTENANCE | \
- FP_MODE_DONT_CHANGE)
+#define FP_VALID_MODES \
+ (FP_MODE_DEEPSLEEP | FP_MODE_FINGER_DOWN | FP_MODE_FINGER_UP | \
+ FP_MODE_CAPTURE | FP_MODE_ENROLL_SESSION | FP_MODE_ENROLL_IMAGE | \
+ FP_MODE_MATCH | FP_MODE_RESET_SENSOR | FP_MODE_SENSOR_MAINTENANCE | \
+ FP_MODE_DONT_CHANGE)
/* Capture types defined in bits [30..28] */
#define FP_MODE_CAPTURE_TYPE_SHIFT 28
-#define FP_MODE_CAPTURE_TYPE_MASK (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT)
+#define FP_MODE_CAPTURE_TYPE_MASK (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT)
/**
* enum fp_capture_type - Specifies the "mode" when capturing images.
*
@@ -7257,8 +7219,8 @@
FP_CAPTURE_TYPE_MAX,
};
/* Extracts the capture type from the sensor 'mode' word */
-#define FP_CAPTURE_TYPE(mode) (((mode) & FP_MODE_CAPTURE_TYPE_MASK) \
- >> FP_MODE_CAPTURE_TYPE_SHIFT)
+#define FP_CAPTURE_TYPE(mode) \
+ (((mode)&FP_MODE_CAPTURE_TYPE_MASK) >> FP_MODE_CAPTURE_TYPE_SHIFT)
struct ec_params_fp_mode {
uint32_t mode; /* as defined by FP_MODE_ constants */
@@ -7272,15 +7234,15 @@
#define EC_CMD_FP_INFO 0x0403
/* Number of dead pixels detected on the last maintenance */
-#define FP_ERROR_DEAD_PIXELS(errors) ((errors) & 0x3FF)
+#define FP_ERROR_DEAD_PIXELS(errors) ((errors)&0x3FF)
/* Unknown number of dead pixels detected on the last maintenance */
#define FP_ERROR_DEAD_PIXELS_UNKNOWN (0x3FF)
/* No interrupt from the sensor */
-#define FP_ERROR_NO_IRQ BIT(12)
+#define FP_ERROR_NO_IRQ BIT(12)
/* SPI communication error */
-#define FP_ERROR_SPI_COMM BIT(13)
+#define FP_ERROR_SPI_COMM BIT(13)
/* Invalid sensor Hardware ID */
-#define FP_ERROR_BAD_HWID BIT(14)
+#define FP_ERROR_BAD_HWID BIT(14)
/* Sensor initialization failed */
#define FP_ERROR_INIT_FAIL BIT(15)
@@ -7313,8 +7275,8 @@
uint16_t bpp;
uint16_t errors; /* see FP_ERROR_ flags above */
/* Template/finger current information */
- uint32_t template_size; /* max template size in bytes */
- uint16_t template_max; /* maximum number of fingers/templates */
+ uint32_t template_size; /* max template size in bytes */
+ uint16_t template_max; /* maximum number of fingers/templates */
uint16_t template_valid; /* number of valid fingers/templates */
uint32_t template_dirty; /* bitmap of templates with MCU side changes */
uint32_t template_version; /* version of the template format */
@@ -7324,13 +7286,13 @@
#define EC_CMD_FP_FRAME 0x0404
/* constants defining the 'offset' field which also contains the frame index */
-#define FP_FRAME_INDEX_SHIFT 28
+#define FP_FRAME_INDEX_SHIFT 28
/* Frame buffer where the captured image is stored */
-#define FP_FRAME_INDEX_RAW_IMAGE 0
+#define FP_FRAME_INDEX_RAW_IMAGE 0
/* First frame buffer holding a template */
-#define FP_FRAME_INDEX_TEMPLATE 1
+#define FP_FRAME_INDEX_TEMPLATE 1
#define FP_FRAME_GET_BUFFER_INDEX(offset) ((offset) >> FP_FRAME_INDEX_SHIFT)
-#define FP_FRAME_OFFSET_MASK 0x0FFFFFFF
+#define FP_FRAME_OFFSET_MASK 0x0FFFFFFF
/* Version of the format of the encrypted templates. */
#define FP_TEMPLATE_FORMAT_VERSION 4
@@ -7397,14 +7359,14 @@
/* Version 1 of the command is "asynchronous". */
struct ec_params_fp_context_v1 {
- uint8_t action; /**< enum fp_context_action */
- uint8_t reserved[3]; /**< padding for alignment */
+ uint8_t action; /**< enum fp_context_action */
+ uint8_t reserved[3]; /**< padding for alignment */
uint32_t userid[FP_CONTEXT_USERID_WORDS];
} __ec_align4;
#define EC_CMD_FP_STATS 0x0407
-#define FPSTATS_CAPTURE_INV BIT(0)
+#define FPSTATS_CAPTURE_INV BIT(0)
#define FPSTATS_MATCHING_INV BIT(1)
struct ec_response_fp_stats {
@@ -7674,14 +7636,14 @@
* switch to the new names soon, as the old names may not be carried forward
* forever.
*/
-#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE
-#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1
-#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE
+#define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE
+#define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1
+#define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE
-#endif /* !__ACPI__ */
+#endif /* !__ACPI__ */
#ifdef __cplusplus
}
#endif
-#endif /* __CROS_EC_EC_COMMANDS_H */
+#endif /* __CROS_EC_EC_COMMANDS_H */