diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/soc/intel/broadwell/pch/lpc.c
index cf6e7d7..4cb1620 100644
--- a/src/soc/intel/broadwell/pch/lpc.c
+++ b/src/soc/intel/broadwell/pch/lpc.c
@@ -128,8 +128,6 @@
 {
 	u16 reg16;
 	const char *state;
-	/* Get the chip configuration */
-	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
 	int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 
 	/* Which state do we want to goto after g3 (power restored)?
@@ -161,12 +159,16 @@
 	pci_write_config16(dev, GEN_PMCON_3, reg16);
 	printk(BIOS_INFO, "Set power %s after power failure.\n", state);
 
-	/* GPE setup based on device tree configuration */
-	enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
-		       config->gpe0_en_3, config->gpe0_en_4);
+	if (dev->chip_info) {
+		const struct soc_intel_broadwell_pch_config *config = dev->chip_info;
 
-	/* SMI setup based on device tree configuration */
-	enable_alt_smi(config->alt_gp_smi_en);
+		/* GPE setup based on device tree configuration */
+		enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2,
+			       config->gpe0_en_3, config->gpe0_en_4);
+
+		/* SMI setup based on device tree configuration */
+		enable_alt_smi(config->alt_gp_smi_en);
+	}
 }
 
 static void pch_misc_init(struct device *dev)
@@ -335,7 +337,10 @@
 
 static void pch_init_deep_sx(struct device *dev)
 {
-	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
+	const struct soc_intel_broadwell_pch_config *config = dev->chip_info;
+
+	if (!config)
+		return;
 
 	if (config->deep_sx_enable_ac) {
 		RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_AC);
@@ -566,7 +571,6 @@
 static void pch_lpc_add_io_resources(struct device *dev)
 {
 	struct resource *res;
-	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
 
 	/* Add the default claimed IO range for the LPC device. */
 	res = new_resource(dev, 0);
@@ -582,10 +586,13 @@
 	pch_lpc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PMBASE);
 
 	/* LPC Generic IO Decode range. */
-	pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC);
-	pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC);
-	pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC);
-	pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC);
+	if (dev->chip_info) {
+		const struct soc_intel_broadwell_pch_config *config = dev->chip_info;
+		pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC);
+		pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC);
+		pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC);
+		pch_lpc_add_gen_io_resources(dev, config->gen4_dec, LPC_GEN4_DEC);
+	}
 }
 
 static void pch_lpc_read_resources(struct device *dev)