sb/intel/bd82x6x: Use array for PCIe ASPM overrides
Using an array reduces the amount of boilerplate code.
Change-Id: Ic6a48a01d3b96e69273dc28bdb6699ce7c0931b2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55246
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
index 9dee30f..725cbd1 100644
--- a/src/mainboard/google/butterfly/devicetree.cb
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -72,7 +72,7 @@
device pci 1c.1 on end # PCIe Port #2 (ETH0)
device pci 1c.2 on end # PCIe Port #3 (Card Reader)
#force ASPM for PCIe bridge to Card Reader
- register "pcie_aspm_f2" = "0x3"
+ register "pcie_aspm[2]" = "0x3"
device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
index 1ec596e..914ab60 100644
--- a/src/mainboard/google/stout/devicetree.cb
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -76,7 +76,7 @@
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 on end # PCIe Port #2 (WLAN)
device pci 1c.2 on end # PCIe Port #3 (Card Reader)
- register "pcie_aspm_f2" = "0x3"
+ register "pcie_aspm[2]" = "0x3"
device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 on end # PCIe Port #6 (LAN)