| commit | 01bd79ff697b4a6976e2b03ff15f4853fa561c0d | [log] [tgz] |
|---|---|---|
| author | zbao <fishbaozi@gmail.com> | Fri Mar 23 11:36:08 2012 +0800 |
| committer | Marc Jones <marcj303@gmail.com> | Mon Apr 02 20:35:03 2012 +0200 |
| tree | f277f59e299dcdadb141616a230ee2d47d6666d4 | |
| parent | 971804ed68347f4fe7ca985a3c924b28041a4079 [diff] [blame] |
Add sb800 spi support. It is for S3, storing the recovring data in the nonvolatile storage, i.e., flash. Change-Id: Ie9e4f42a80c93d92d2e442f0e833ce06d88294f9 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: zbao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/620 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marcj303@gmail.com>
diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc index 30d2133..2b55fee 100644 --- a/src/southbridge/amd/cimx/sb800/Makefile.inc +++ b/src/southbridge/amd/cimx/sb800/Makefile.inc
@@ -27,6 +27,8 @@ ramstage-y += cfg.c ramstage-y += late.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c + driver-y += smbus.c driver-y += lpc.c