diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index 3209d81..d39d2f6 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -121,7 +121,10 @@
 	post_code(0x30);
 
 	printk(BIOS_DEBUG, "Initializing memory\n");
-	sdram_initialize(0, spd_addrmap);
+	if (MCHBAR32(0xf14) & (1 << 8)) /* HOT RESET */
+		sdram_initialize(BOOT_PATH_RESET, spd_addrmap);
+	else
+		sdram_initialize(BOOT_PATH_NORMAL, spd_addrmap);
 	printk(BIOS_DEBUG, "Memory initialized\n");
 
 	post_code(0x31);
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c
index a45b4da..6988058 100644
--- a/src/northbridge/intel/pineview/raminit.c
+++ b/src/northbridge/intel/pineview/raminit.c
@@ -569,6 +569,8 @@
 	PRINTK_DEBUG("Drive Memory at %dMHz with CAS = %d clocks\n", ddr_reg_to_mhz(s->selected_timings.mem_clock), s->selected_timings.CAS);
 
 	// Set memory frequency
+	if (s->boot_path == BOOT_PATH_RESET)
+		return;
 	MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x1;
 	reg32 = (MCHBAR32(0xc00) & (~0x70)) | (1 << 10);
 	if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) {
@@ -676,7 +678,8 @@
 		reg8 = 1;
 		reg16 = (1 << 8) | (1 << 5);
 	}
-	MCHBAR16(0x1c0) = (MCHBAR16(0x1c0) & ~(0x033f)) | reg16;
+	if (s->boot_path != BOOT_PATH_RESET)
+		MCHBAR16(0x1c0) = (MCHBAR16(0x1c0) & ~(0x033f)) | reg16;
 
 	MCHBAR32(0x220) = 0x58001117;
 	MCHBAR32(0x248) = (MCHBAR32(0x248) | (1 << 23));
@@ -2540,12 +2543,14 @@
 {
 	struct sysinfo si;
 	u8 reg8;
+	const char *boot_str[] = { "Normal", "Reset", "Resume"};
 
 	PRINTK_DEBUG("Setting up RAM controller.\n");
 
 	memset(&si, 0, sizeof(si));
 
 	si.boot_path = boot_path;
+	printk(BIOS_DEBUG, "Boot path: %s\n", boot_str[boot_path]);
 	si.spd_map[0] = spd_addresses[0];
 	si.spd_map[1] = spd_addresses[1];
 	si.spd_map[2] = spd_addresses[2];
@@ -2578,18 +2583,25 @@
 	sdram_timings(&si);
 	PRINTK_DEBUG("Done timings (dqs dll enabled)\n");
 
-	sdram_dlltiming(&si);
-	PRINTK_DEBUG("Done dlltiming\n");
+	if (si.boot_path != BOOT_PATH_RESET) {
+		sdram_dlltiming(&si);
+		PRINTK_DEBUG("Done dlltiming\n");
+	}
 
 	hpet_udelay(200000);
 
-	sdram_rcomp(&si);
-	PRINTK_DEBUG("Done RCOMP\n");
+	if (si.boot_path != BOOT_PATH_RESET) {
+		sdram_rcomp(&si);
+		PRINTK_DEBUG("Done RCOMP\n");
+	}
 
 	sdram_odt(&si);
 	PRINTK_DEBUG("Done odt\n");
 
-	while ((MCHBAR8(0x130) & 0x1) != 0);
+	if (si.boot_path != BOOT_PATH_RESET) {
+		while ((MCHBAR8(0x130) & 0x1) != 0)
+			;
+	}
 
 	sdram_mmap(&si);
 	PRINTK_DEBUG("Done mmap\n");