| Paul Menzel | b5fece3 | 2018-02-02 07:59:10 +0100 | [diff] [blame] | 1 | # This image was built using coreboot TIMELESS |
| 2 | CONFIG_VENDOR_ASROCK=y | ||||
| 3 | CONFIG_VGA_BIOS=y | ||||
| 4 | CONFIG_VGA_BIOS_FILE="pci1002,9802.rom.lzma" | ||||
| 5 | CONFIG_BOARD_ASROCK_E350M1=y | ||||
| 6 | CONFIG_PCIEXP_L1_SUB_STATE=y | ||||
| 7 | CONFIG_NO_POST=y | ||||
| 8 | CONFIG_PCIEXP_ASPM=y | ||||
| 9 | # CONFIG_CONSOLE_SERIAL is not set | ||||
| 10 | CONFIG_SEABIOS_MASTER=y | ||||
| 11 | CONFIG_COREINFO_SECONDARY_PAYLOAD=y | ||||
| 12 | CONFIG_MEMTEST_SECONDARY_PAYLOAD=y | ||||
| 13 | CONFIG_NVRAMCUI_SECONDARY_PAYLOAD=y | ||||
| 14 | CONFIG_TINT_SECONDARY_PAYLOAD=y | ||||