| David Hendricks | 0b6f4d4 | 2017-09-05 23:56:13 -0700 | [diff] [blame] | 1 | # This image was built using coreboot 4.6-1357-g3fd259c91d |
| 2 | CONFIG_COLLECT_TIMESTAMPS=y |
| 3 | CONFIG_USE_BLOBS=y |
| 4 | CONFIG_VENDOR_INTEL=y |
| 5 | CONFIG_FSP_FILE="../FSP-BayTrail/BayTrailFspBinPkg/FspBin/BayTrailFSP.fd" |
| 6 | # CONFIG_ENABLE_FSP_FAST_BOOT is not set |
| 7 | CONFIG_PAYLOAD_CONFIGFILE="../../../../seabios/.config" |
| 8 | CONFIG_VGA_BIOS=y |
| 9 | CONFIG_VGA_BIOS_FILE="../FSP-BayTrail/BayTrailFspBinPkg/Vbios/Vga.dat" |
| 10 | CONFIG_HAVE_IFD_BIN=y |
| 11 | CONFIG_HAVE_ME_BIN=y |
| 12 | CONFIG_BOARD_INTEL_MINNOWMAX=y |
| 13 | CONFIG_IFD_BIN_PATH="../intel/fd_from_uefi_0.96_release.bin" |
| 14 | CONFIG_ME_BIN_PATH="../intel/me_from_uefi_0.96_release.bin" |
| 15 | CONFIG_PCIEXP_L1_SUB_STATE=y |
| 16 | CONFIG_PCIEXP_ASPM=y |
| 17 | CONFIG_PCIEXP_COMMON_CLOCK=y |
| 18 | CONFIG_PCIEXP_CLK_PM=y |
| 19 | CONFIG_CPU_MICROCODE_HEADER_FILES="../intel/M0130679901.h" |
| 20 | CONFIG_LOCK_MANAGEMENT_ENGINE=y |
| 21 | CONFIG_HAVE_FSP_BIN=y |
| 22 | CONFIG_VGA_ROM_RUN=y |
| 23 | CONFIG_ON_DEVICE_ROM_LOAD=y |
| 24 | CONFIG_FRAMEBUFFER_SET_VESA_MODE=y |
| 25 | # CONFIG_SQUELCH_EARLY_SMP is not set |
| 26 | CONFIG_CMOS_POST=y |
| 27 | CONFIG_CMOS_POST_OFFSET=0x80 |
| 28 | CONFIG_CMOS_POST_EXTRA=y |
| 29 | CONFIG_CONSOLE_POST=y |
| 30 | CONFIG_SEABIOS_MASTER=y |
| 31 | CONFIG_DEBUG_CBFS=y |
| 32 | CONFIG_DEBUG_SMI=y |
| 33 | CONFIG_DEBUG_SMM_RELOCATION=y |
| 34 | CONFIG_DEBUG_MALLOC=y |
| 35 | CONFIG_DEBUG_ACPI=y |
| 36 | CONFIG_REALMODE_DEBUG=y |
| 37 | CONFIG_DEBUG_SPI_FLASH=y |
| 38 | CONFIG_DEBUG_BOOT_STATE=y |