| *** Pre-CBMEM romstage console overflowed, log truncated! *** |
| 8T |
| Selected tWTR : 8T |
| Selected tRFC : 243T |
| Done dimm mapping |
| Update PCI-E configuration space: |
| PCI(0, 0, 0)[a0] = 0 |
| PCI(0, 0, 0)[a4] = 4 |
| PCI(0, 0, 0)[bc] = 82a00000 |
| PCI(0, 0, 0)[a8] = 7b600000 |
| PCI(0, 0, 0)[ac] = 4 |
| PCI(0, 0, 0)[b8] = 80000000 |
| PCI(0, 0, 0)[b0] = 80a00000 |
| PCI(0, 0, 0)[b4] = 80800000 |
| PCI(0, 0, 0)[7c] = 7f |
| PCI(0, 0, 0)[70] = fe000000 |
| PCI(0, 0, 0)[74] = 3 |
| PCI(0, 0, 0)[78] = fe000c00 |
| Done memory map |
| Done io registers |
| Done jedec reset |
| Done MRS commands |
| t123: 1663, 6000, 7620 |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : NO |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Recovery |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Normal |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Pseudo-global reset |
| ME: Progress Phase State : Waiting for DID BIOS message |
| ME: FWS2: 0x161f017a |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x1 |
| ME: Invoke MEBx : 0x1 |
| ME: CPU replaced : 0x1 |
| ME: MBP ready : 0x1 |
| ME: MFS failure : 0x1 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x1 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0x1f |
| ME: Current PM event: 0x6 |
| ME: Progress code : 0x1 |
| Full training required |
| PASSED! Tell ME that DRAM is ready |
| Timestamp - waiting for ME acknowledgement of raminit: 3666696470 |
| Timestamp - finished waiting for ME response: 3670088756 |
| ME: FWS2: 0x162c017a |
| ME: Bist in progress: 0x0 |
| ME: ICC Status : 0x1 |
| ME: Invoke MEBx : 0x1 |
| ME: CPU replaced : 0x1 |
| ME: MBP ready : 0x1 |
| ME: MFS failure : 0x1 |
| ME: Warm reset req : 0x0 |
| ME: CPU repl valid : 0x1 |
| ME: (Reserved) : 0x0 |
| ME: FW update req : 0x0 |
| ME: (Reserved) : 0x0 |
| ME: Current state : 0x2c |
| ME: Current PM event: 0x6 |
| ME: Progress code : 0x1 |
| ME: Requested BIOS Action: Continue to boot |
| ME: FW Partition Table : OK |
| ME: Bringup Loader Failure : NO |
| ME: Firmware Init Complete : NO |
| ME: Manufacturing Mode : NO |
| ME: Boot Options Present : NO |
| ME: Update In Progress : NO |
| ME: Current Working State : Recovery |
| ME: Current Operation State : Bring up |
| ME: Current Operation Mode : Normal |
| ME: Error Code : No Error |
| ME: Progress Phase : BUP Phase |
| ME: Power Management Event : Pseudo-global reset |
| ME: Progress Phase State : 0x2c |
| memcfg DDR3 ref clock 133 MHz |
| memcfg DDR3 clock 1862 MHz |
| memcfg channel assignment: A: 0, B 1, C 2 |
| memcfg channel[0] config (00620020): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 8192 MB width x8 dual rank, selected |
| DIMMB 0 MB width x8 single rank |
| memcfg channel[1] config (00620020): |
| ECC inactive |
| enhanced interleave mode on |
| rank interleave on |
| DIMMA 8192 MB width x8 dual rank, selected |
| DIMMB 0 MB width x8 single rank |
| CBMEM: |
| IMD: root @ 0x7ffff000 254 entries. |
| IMD: root @ 0x7fffec00 62 entries. |
| External stage cache: |
| IMD: root @ 0x803ff000 254 entries. |
| IMD: root @ 0x803fec00 62 entries. |
| CBMEM entry for DIMM info: 0x7fffe960 |
| Timestamp - after RAM initialization: 3675227266 |
| POST: 0x3b |
| POST: 0x3c |
| POST: 0x3d |
| POST: 0x3f |
| SMM Memory Map |
| SMRAM : 0x80000000 0x800000 |
| Subregion 0: 0x80000000 0x300000 |
| Subregion 1: 0x80300000 0x100000 |
| Subregion 2: 0x80400000 0x400000 |
| MTRR Range: Start=7f800000 End=80000000 (Size 800000) |
| MTRR Range: Start=80000000 End=80800000 (Size 800000) |
| MTRR Range: Start=ff000000 End=0 (Size 1000000) |
| FMAP: area COREBOOT found @ c10200 (4128256 bytes) |
| CBFS: Locating 'fallback/postcar' |
| CBFS: Checking offset 0 |
| CBFS: File @ offset 0 size 20 |
| CBFS: Unmatched 'cbfs master header' at 0 |
| CBFS: Checking offset 80 |
| CBFS: File @ offset 80 size 14b4c |
| CBFS: Unmatched 'fallback/romstage' at 80 |
| CBFS: Checking offset 14c40 |
| CBFS: File @ offset 14c40 size 6800 |
| CBFS: Unmatched 'cpu_microcode_blob.bin' at 14c40 |
| CBFS: Checking offset 1b4c0 |
| CBFS: File @ offset 1b4c0 size 1721a |
| CBFS: Unmatched 'fallback/ramstage' at 1b4c0 |
| CBFS: Checking offset 32740 |
| CBFS: File @ offset 32740 size 511 |
| CBFS: Unmatched 'config' at 32740 |
| CBFS: Checking offset 32cc0 |
| CBFS: File @ offset 32cc0 size 2a2 |
| CBFS: Unmatched 'revision' at 32cc0 |
| CBFS: Checking offset 32fc0 |
| CBFS: File @ offset 32fc0 size bd3a |
| CBFS: Unmatched 'bootsplash.jpg' at 32fc0 |
| CBFS: Checking offset 3ed40 |
| CBFS: File @ offset 3ed40 size 3926 |
| CBFS: Unmatched 'fallback/dsdt.aml' at 3ed40 |
| CBFS: Checking offset 426c0 |
| CBFS: File @ offset 426c0 size 581 |
| CBFS: Unmatched 'vbt.bin' at 426c0 |
| CBFS: Checking offset 42c80 |
| CBFS: File @ offset 42c80 size 100 |
| CBFS: Unmatched 'cmos.default' at 42c80 |
| CBFS: Checking offset 42dc0 |
| CBFS: File @ offset 42dc0 size 78c |
| CBFS: Unmatched 'cmos_layout.bin' at 42dc0 |
| CBFS: Checking offset 435c0 |
| CBFS: File @ offset 435c0 size 10000 |
| CBFS: Unmatched 'pci8086,0166.rom' at 435c0 |
| CBFS: Checking offset 53640 |
| CBFS: File @ offset 53640 size 5af0 |
| CBFS: Found @ offset 53640 size 5af0 |
| Decompressing stage fallback/postcar @ 0x7ffd0fc0 (39248 bytes) |
| Loading module at 0x7ffd1000 with entry 0x7ffd1000. filesize: 0x5610 memsize: 0x9910 |
| Processing 289 relocs. Offset value of 0x7dfd1000 |
| Timestamp - end of romstage: 3691959898 |
| BS: romstage times (exec / console): total (unknown) / 2 ms |
| |
| |
| coreboot-4.12-681-gdc6bb6cb82 Sat Jun 13 12:26:34 UTC 2020 postcar starting (log level: 7)... |
| Timestamp - start of postcar: 3695554080 |
| Timestamp - end of postcar: 3695562200 |
| FMAP: area COREBOOT found @ c10200 (4128256 bytes) |
| CBFS: Locating 'fallback/ramstage' |
| CBFS: Found @ offset 1b4c0 size 1721a |
| Timestamp - starting to load ramstage: 3695591878 |
| Decompressing stage fallback/ramstage @ 0x7ff89fc0 (285168 bytes) |
| Timestamp - starting LZMA decompress (ignore for x86): 3695608127 |
| Timestamp - finished LZMA decompress (ignore for x86): 3761608134 |
| Loading module at 0x7ff8a000 with entry 0x7ff8a000. filesize: 0x304b8 memsize: 0x459b0 |
| Processing 3378 relocs. Offset value of 0x7f18a000 |
| Timestamp - finished loading ramstage: 3761994646 |
| BS: postcar times (exec / console): total (unknown) / 0 ms |
| |
| |
| coreboot-4.12-681-gdc6bb6cb82 Sat Jun 13 12:26:34 UTC 2020 ramstage starting (log level: 7)... |
| POST: 0x39 |
| Timestamp - start of ramstage: 3762287122 |
| POST: 0x80 |
| Normal boot |
| POST: 0x70 |
| POST: 0x71 |
| Timestamp - device enumeration: 3762308794 |
| POST: 0x72 |
| Enumerating buses... |
| Root Device scanning... |
| CPU_CLUSTER: 0 enabled |
| DOMAIN: 0000 enabled |
| DOMAIN: 0000 scanning... |
| PCI: pci_scan_bus for bus 00 |
| POST: 0x24 |
| PCI: 00:00.0 [8086/0154] enabled |
| PCI: Static device PCI: 00:01.0 not found, disabling it. |
| PCI: 00:02.0 [8086/0166] enabled |
| PCI: 00:04.0 [8086/0153] enabled |
| PCI: 00:14.0 [8086/1e31] enabled |
| PCI: 00:16.0: Disabling device |
| PCI: 00:16.0 [8086/1e3a] disabled |
| PCI: 00:16.1: Disabling device |
| PCI: 00:16.2: Disabling device |
| PCI: 00:16.3: Disabling device |
| PCI: 00:19.0 [8086/1502] enabled |
| PCI: 00:1a.0 [8086/1e2d] enabled |
| PCI: 00:1b.0 [8086/1e20] enabled |
| PCH: PCIe Root Port coalescing is enabled |
| PCI: 00:1c.0: Disabling device |
| PCI: 00:1c.0: check set enabled |
| PCI: 00:1c.0 [8086/1e10] disabled |
| PCH: Remap PCIe function 1 to 0 |
| PCI: 00:1c.1 [8086/1e12] enabled |
| PCH: Remap PCIe function 2 to 0 |
| PCI: 00:1c.2 [8086/1e14] enabled |
| PCI: 00:1c.3: Disabling device |
| PCI: 00:1c.3 [8086/1e16] disabled |
| PCH: Remap PCIe function 4 to 0 |
| PCI: 00:1c.4 [8086/1e18] enabled |
| PCI: 00:1c.5: Disabling device |
| PCI: 00:1c.6: Disabling device |
| PCI: 00:1c.7: Disabling device |
| PCH: PCIe map 1c.0 -> 1c.4 |
| PCH: PCIe map 1c.1 -> 1c.0 |
| PCH: PCIe map 1c.2 -> 1c.1 |
| PCH: PCIe map 1c.4 -> 1c.2 |
| PCI: 00:1d.0 [8086/1e26] enabled |
| PCI: 00:1e.0: Disabling device |
| PCI: 00:1e.0 [8086/2448] disabled |
| PCI: 00:1f.0 [8086/1e55] enabled |
| PCI: 00:1f.2 [8086/1e01] enabled |
| PCI: 00:1f.3 [8086/1e22] enabled |
| PCI: 00:1f.5: Disabling device |
| PCI: 00:1f.5 [8086/1e09] disabled No operations |
| PCI: 00:1f.6 [8086/1e24] enabled |
| POST: 0x25 |
| PCI: Leftover static devices: |
| PCI: 00:01.0 |
| PCI: 00:16.1 |
| PCI: 00:16.2 |
| PCI: 00:16.3 |
| PCI: 00:1c.5 |
| PCI: 00:1c.6 |
| PCI: 00:1c.7 |
| PCI: Check your devicetree.cb. |
| PCI: 00:1c.0 scanning... |
| PCI: pci_scan_bus for bus 01 |
| POST: 0x24 |
| PCI: 01:00.0 [14e4/43a0] enabled |
| POST: 0x25 |
| POST: 0x55 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L0s and L1 |
| PCIe: Max_Payload_Size adjusted to 128 |
| scan_bus: bus PCI: 00:1c.0 finished in 0 msecs |
| PCI: 00:1c.1 scanning... |
| PCI: pci_scan_bus for bus 02 |
| POST: 0x24 |
| PCI: 02:00.0 [1180/e822] enabled |
| POST: 0x25 |
| POST: 0x55 |
| Enabling Common Clock Configuration |
| ASPM: Enabled L0s and L1 |
| PCIe: Max_Payload_Size adjusted to 128 |
| Failed to enable LTR for dev = PCI: 02:00.0 |
| scan_bus: bus PCI: 00:1c.1 finished in 0 msecs |
| PCI: 00:1c.2 scanning... |
| PCI: pci_scan_bus for bus 03 |
| POST: 0x24 |
| POST: 0x25 |
| POST: 0x55 |
| scan_bus: bus PCI: 00:1c.2 finished in 0 msecs |
| PCI: 00:1f.0 scanning... |
| PMH7: ID 05 Revision 12 |
| PNP: 00ff.1 enabled |
| PNP: 0c31.0 enabled |
| H8: EC Firmware ID G7HT39WW-3.22, Version 5.01B |
| H8: WWAN detection not implemented. Assuming WWAN installed |
| PNP: 00ff.2 enabled |
| scan_bus: bus PCI: 00:1f.0 finished in 4 msecs |
| PCI: 00:1f.3 scanning... |
| bus: PCI: 00:1f.3[0]->I2C: 01:54 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled |
| bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled |
| scan_bus: bus PCI: 00:1f.3 finished in 0 msecs |
| POST: 0x55 |
| scan_bus: bus DOMAIN: 0000 finished in 5 msecs |
| scan_bus: bus Root Device finished in 5 msecs |
| done |
| BS: BS_DEV_ENUMERATE run times (exec / console): 6 / 0 ms |
| FMAP: area RW_MRC_CACHE found @ c00000 (65536 bytes) |
| MRC: Checking cached data update for 'RW_MRC_CACHE'. |
| Manufacturer: ef |
| SF: Detected ef 4018 with sector size 0x1000, total 0x1000000 |
| MRC: no data in 'RW_MRC_CACHE' |
| MRC: cache data 'RW_MRC_CACHE' needs update. |
| MRC: updated 'RW_MRC_CACHE'. |
| BS: BS_DEV_ENUMERATE exit times (exec / console): 4 / 0 ms |
| POST: 0x73 |
| Timestamp - device configuration: 3791702808 |
| found VGA at PCI: 00:02.0 |
| Setting up VGA for PCI: 00:02.0 |
| Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| Allocating resources... |
| Reading resources... |
| Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| TOUUD 0x47b600000 TOLUD 0x82a00000 TOM 0x400000000 |
| MEBASE 0x3fe000000 |
| IGD decoded, subtracting 32M UMA and 2M GTT |
| TSEG base 0x80000000 size 8M |
| Available memory below 4GB: 2048M |
| Available memory above 4GB: 14262M |
| PNP: 00ff.1 missing read_resources |
| PNP: 00ff.2 missing read_resources |
| Done reading resources. |
| ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === |
| PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff |
| PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| PCI: 01:00.0 18 * [0x0 - 0x1fffff] mem |
| PCI: 01:00.0 10 * [0x200000 - 0x207fff] mem |
| PCI: 00:1c.0 mem: size: 300000 align: 21 gran: 20 limit: ffffffff done |
| PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff |
| NONE 18 * [0x0 - 0xfff] io |
| PCI: 00:1c.1 io: size: 1000 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| NONE 10 * [0x0 - 0x7fffff] mem |
| PCI: 02:00.0 10 * [0x800000 - 0x8000ff] mem |
| PCI: 00:1c.1 mem: size: 900000 align: 22 gran: 20 limit: ffffffff done |
| PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| NONE 14 * [0x0 - 0x7fffff] prefmem |
| PCI: 00:1c.1 prefmem: size: 800000 align: 22 gran: 20 limit: ffffffff done |
| PCI: 00:1c.2 io: size: 0 align: 12 gran: 12 limit: ffff |
| NONE 18 * [0x0 - 0xfff] io |
| PCI: 00:1c.2 io: size: 1000 align: 12 gran: 12 limit: ffff done |
| PCI: 00:1c.2 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| NONE 10 * [0x0 - 0x7fffff] mem |
| PCI: 00:1c.2 mem: size: 800000 align: 22 gran: 20 limit: ffffffff done |
| PCI: 00:1c.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| NONE 14 * [0x0 - 0x7fffff] prefmem |
| PCI: 00:1c.2 prefmem: size: 800000 align: 22 gran: 20 limit: ffffffff done |
| === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === |
| DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| update_constraints: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) |
| update_constraints: PCI: 00:1f.0 10000200 base 00001600 limit 0000167b io (fixed) |
| update_constraints: PCI: 00:1f.0 10000300 base 000015e0 limit 000015eb io (fixed) |
| update_constraints: PNP: 00ff.1 77 base 000015e0 limit 000015ef io (fixed) |
| update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed) |
| DOMAIN: 0000: Resource ranges: |
| * Base: 1000, Size: 5e0, Tag: 100 |
| * Base: 15f0, Size: 10, Tag: 100 |
| * Base: 167c, Size: e984, Tag: 100 |
| PCI: 00:1c.1 1c * [0x2000 - 0x2fff] limit: 2fff io |
| PCI: 00:1c.2 1c * [0x3000 - 0x3fff] limit: 3fff io |
| PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io |
| PCI: 00:19.0 18 * [0x1040 - 0x105f] limit: 105f io |
| PCI: 00:1f.2 20 * [0x1060 - 0x107f] limit: 107f io |
| PCI: 00:1f.2 10 * [0x1080 - 0x1087] limit: 1087 io |
| PCI: 00:1f.2 18 * [0x1088 - 0x108f] limit: 108f io |
| PCI: 00:1f.2 14 * [0x1090 - 0x1093] limit: 1093 io |
| PCI: 00:1f.2 1c * [0x1094 - 0x1097] limit: 1097 io |
| DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done |
| DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff |
| update_constraints: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed) |
| update_constraints: PCI: 00:00.0 03 base 00000000 limit 0009ffff mem (fixed) |
| update_constraints: PCI: 00:00.0 04 base 00100000 limit 7fffffff mem (fixed) |
| update_constraints: PCI: 00:00.0 05 base 100000000 limit 47b5fffff mem (fixed) |
| update_constraints: PCI: 00:00.0 06 base 80000000 limit 829fffff mem (fixed) |
| update_constraints: PCI: 00:00.0 07 base 000a0000 limit 000bffff mem (fixed) |
| update_constraints: PCI: 00:00.0 08 base 000c0000 limit 000fffff mem (fixed) |
| update_constraints: PCI: 00:00.0 09 base fed90000 limit fed90fff mem (fixed) |
| update_constraints: PCI: 00:00.0 0a base fed91000 limit fed91fff mem (fixed) |
| update_constraints: PCI: 00:1f.0 10000100 base ff000000 limit ffffffff mem (fixed) |
| update_constraints: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed) |
| update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed) |
| DOMAIN: 0000: Resource ranges: |
| * Base: 82a00000, Size: 6d600000, Tag: 200 |
| * Base: f4000000, Size: ac00000, Tag: 200 |
| * Base: fec01000, Size: 13f000, Tag: 200 |
| * Base: fed45000, Size: 4b000, Tag: 200 |
| * Base: fed92000, Size: 26e000, Tag: 200 |
| * Base: 47b600000, Size: b84a00000, Tag: 100200 |
| PCI: 00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem |
| PCI: 00:1c.1 20 * [0x82c00000 - 0x834fffff] limit: 834fffff mem |
| PCI: 00:1c.1 24 * [0x83800000 - 0x83ffffff] limit: 83ffffff prefmem |
| PCI: 00:1c.2 24 * [0x84000000 - 0x847fffff] limit: 847fffff prefmem |
| PCI: 00:1c.2 20 * [0x84800000 - 0x84ffffff] limit: 84ffffff mem |
| PCI: 00:02.0 10 * [0x85000000 - 0x853fffff] limit: 853fffff mem |
| PCI: 00:1c.0 20 * [0x85400000 - 0x856fffff] limit: 856fffff mem |
| PCI: 00:19.0 10 * [0x82a00000 - 0x82a1ffff] limit: 82a1ffff mem |
| PCI: 00:14.0 10 * [0x82a20000 - 0x82a2ffff] limit: 82a2ffff mem |
| PCI: 00:04.0 10 * [0x82a30000 - 0x82a37fff] limit: 82a37fff mem |
| PCI: 00:1b.0 10 * [0x82a38000 - 0x82a3bfff] limit: 82a3bfff mem |
| PCI: 00:19.0 14 * [0x82a3c000 - 0x82a3cfff] limit: 82a3cfff mem |
| PCI: 00:1f.6 10 * [0x82a3d000 - 0x82a3dfff] limit: 82a3dfff mem |
| PCI: 00:1f.2 24 * [0x82a3e000 - 0x82a3e7ff] limit: 82a3e7ff mem |
| PCI: 00:1a.0 10 * [0x82a3f000 - 0x82a3f3ff] limit: 82a3f3ff mem |
| PCI: 00:1d.0 10 * [0x82a40000 - 0x82a403ff] limit: 82a403ff mem |
| PCI: 00:1f.3 10 * [0x82a41000 - 0x82a410ff] limit: 82a410ff mem |
| DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done |
| PCI: 00:1c.0 mem: base: 85400000 size: 300000 align: 21 gran: 20 limit: 856fffff |
| PCI: 00:1c.0: Resource ranges: |
| * Base: 85400000, Size: 300000, Tag: 200 |
| PCI: 01:00.0 18 * [0x85400000 - 0x855fffff] limit: 855fffff mem |
| PCI: 01:00.0 10 * [0x85600000 - 0x85607fff] limit: 85607fff mem |
| PCI: 00:1c.0 mem: base: 85400000 size: 300000 align: 21 gran: 20 limit: 856fffff done |
| PCI: 00:1c.1 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff |
| PCI: 00:1c.1: Resource ranges: |
| * Base: 2000, Size: 1000, Tag: 100 |
| NONE 18 * [0x2000 - 0x2fff] limit: 2fff io |
| PCI: 00:1c.1 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff done |
| PCI: 00:1c.1 prefmem: base: 83800000 size: 800000 align: 22 gran: 20 limit: 83ffffff |
| PCI: 00:1c.1: Resource ranges: |
| * Base: 83800000, Size: 800000, Tag: 1200 |
| NONE 14 * [0x83800000 - 0x83ffffff] limit: 83ffffff prefmem |
| PCI: 00:1c.1 prefmem: base: 83800000 size: 800000 align: 22 gran: 20 limit: 83ffffff done |
| PCI: 00:1c.1 mem: base: 82c00000 size: 900000 align: 22 gran: 20 limit: 834fffff |
| PCI: 00:1c.1: Resource ranges: |
| * Base: 82c00000, Size: 900000, Tag: 200 |
| NONE 10 * [0x82c00000 - 0x833fffff] limit: 833fffff mem |
| PCI: 02:00.0 10 * [0x83400000 - 0x834000ff] limit: 834000ff mem |
| PCI: 00:1c.1 mem: base: 82c00000 size: 900000 align: 22 gran: 20 limit: 834fffff done |
| PCI: 00:1c.2 io: base: 3000 size: 1000 align: 12 gran: 12 limit: 3fff |
| PCI: 00:1c.2: Resource ranges: |
| * Base: 3000, Size: 1000, Tag: 100 |
| NONE 18 * [0x3000 - 0x3fff] limit: 3fff io |
| PCI: 00:1c.2 io: base: 3000 size: 1000 align: 12 gran: 12 limit: 3fff done |
| PCI: 00:1c.2 prefmem: base: 84000000 size: 800000 align: 22 gran: 20 limit: 847fffff |
| PCI: 00:1c.2: Resource ranges: |
| * Base: 84000000, Size: 800000, Tag: 1200 |
| NONE 14 * [0x84000000 - 0x847fffff] limit: 847fffff prefmem |
| PCI: 00:1c.2 prefmem: base: 84000000 size: 800000 align: 22 gran: 20 limit: 847fffff done |
| PCI: 00:1c.2 mem: base: 84800000 size: 800000 align: 22 gran: 20 limit: 84ffffff |
| PCI: 00:1c.2: Resource ranges: |
| * Base: 84800000, Size: 800000, Tag: 200 |
| NONE 10 * [0x84800000 - 0x84ffffff] limit: 84ffffff mem |
| PCI: 00:1c.2 mem: base: 84800000 size: 800000 align: 22 gran: 20 limit: 84ffffff done |
| === Resource allocator: DOMAIN: 0000 - resource allocation complete === |
| PCI: 00:02.0 10 <- [0x0085000000 - 0x00853fffff] size 0x00400000 gran 0x16 mem64 |
| PCI: 00:02.0 18 <- [0x0090000000 - 0x009fffffff] size 0x10000000 gran 0x1c prefmem64 |
| PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io |
| PCI: 00:04.0 10 <- [0x0082a30000 - 0x0082a37fff] size 0x00008000 gran 0x0f mem64 |
| PCI: 00:14.0 10 <- [0x0082a20000 - 0x0082a2ffff] size 0x00010000 gran 0x10 mem64 |
| PCI: 00:19.0 10 <- [0x0082a00000 - 0x0082a1ffff] size 0x00020000 gran 0x11 mem |
| PCI: 00:19.0 14 <- [0x0082a3c000 - 0x0082a3cfff] size 0x00001000 gran 0x0c mem |
| PCI: 00:19.0 18 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io |
| PCI: 00:1a.0 10 <- [0x0082a3f000 - 0x0082a3f3ff] size 0x00000400 gran 0x0a mem |
| PCI: 00:1b.0 10 <- [0x0082a38000 - 0x0082a3bfff] size 0x00004000 gran 0x0e mem64 |
| PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| PCI: 00:1c.0 20 <- [0x0085400000 - 0x00856fffff] size 0x00300000 gran 0x14 bus 01 mem |
| PCI: 01:00.0 10 <- [0x0085600000 - 0x0085607fff] size 0x00008000 gran 0x0f mem64 |
| PCI: 01:00.0 18 <- [0x0085400000 - 0x00855fffff] size 0x00200000 gran 0x15 mem64 |
| PCI: 00:1c.1 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 02 io |
| PCI: 00:1c.1 24 <- [0x0083800000 - 0x0083ffffff] size 0x00800000 gran 0x14 bus 02 prefmem |
| PCI: 00:1c.1 20 <- [0x0082c00000 - 0x00834fffff] size 0x00900000 gran 0x14 bus 02 mem |
| PCI: 02:00.0 10 <- [0x0083400000 - 0x00834000ff] size 0x00000100 gran 0x08 mem |
| NONE missing set_resources |
| PCI: 00:1c.2 1c <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x0c bus 03 io |
| PCI: 00:1c.2 24 <- [0x0084000000 - 0x00847fffff] size 0x00800000 gran 0x14 bus 03 prefmem |
| PCI: 00:1c.2 20 <- [0x0084800000 - 0x0084ffffff] size 0x00800000 gran 0x14 bus 03 mem |
| NONE missing set_resources |
| PCI: 00:1d.0 10 <- [0x0082a40000 - 0x0082a403ff] size 0x00000400 gran 0x0a mem |
| PNP: 00ff.1 missing set_resources |
| PNP: 00ff.2 missing set_resources |
| PCI: 00:1f.2 10 <- [0x0000001080 - 0x0000001087] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 14 <- [0x0000001090 - 0x0000001093] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 18 <- [0x0000001088 - 0x000000108f] size 0x00000008 gran 0x03 io |
| PCI: 00:1f.2 1c <- [0x0000001094 - 0x0000001097] size 0x00000004 gran 0x02 io |
| PCI: 00:1f.2 20 <- [0x0000001060 - 0x000000107f] size 0x00000020 gran 0x05 io |
| PCI: 00:1f.2 24 <- [0x0082a3e000 - 0x0082a3e7ff] size 0x00000800 gran 0x0b mem |
| PCI: 00:1f.3 10 <- [0x0082a41000 - 0x0082a410ff] size 0x00000100 gran 0x08 mem64 |
| PCI: 00:1f.6 10 <- [0x0082a3d000 - 0x0082a3dfff] size 0x00001000 gran 0x0c mem64 |
| Done setting resources. |
| Done allocating resources. |
| BS: BS_DEV_RESOURCES run times (exec / console): 2 / 0 ms |
| POST: 0x74 |
| Timestamp - device enable: 3797423705 |
| Enabling resources... |
| PCI: 00:00.0 subsystem <- 8086/0154 |
| PCI: 00:00.0 cmd <- 06 |
| PCI: 00:02.0 subsystem <- 8086/0166 |
| PCI: 00:02.0 cmd <- 03 |
| PCI: 00:04.0 cmd <- 02 |
| PCI: 00:14.0 subsystem <- 8086/1e31 |
| PCI: 00:14.0 cmd <- 102 |
| PCI: 00:19.0 subsystem <- 17aa/21f3 |
| PCI: 00:19.0 cmd <- 103 |
| PCI: 00:1a.0 subsystem <- 8086/1e2d |
| PCI: 00:1a.0 cmd <- 102 |
| PCI: 00:1b.0 subsystem <- 8086/1e20 |
| PCI: 00:1b.0 cmd <- 102 |
| PCI: 00:1c.0 bridge ctrl <- 0013 |
| PCI: 00:1c.0 subsystem <- 8086/1e12 |
| PCI: 00:1c.0 cmd <- 106 |
| PCI: 00:1c.1 bridge ctrl <- 0013 |
| PCI: 00:1c.1 subsystem <- 8086/1e14 |
| PCI: 00:1c.1 cmd <- 107 |
| PCI: 00:1c.2 bridge ctrl <- 0013 |
| PCI: 00:1c.2 subsystem <- 8086/1e18 |
| PCI: 00:1c.2 cmd <- 107 |
| PCI: 00:1d.0 subsystem <- 8086/1e26 |
| PCI: 00:1d.0 cmd <- 102 |
| PCI: 00:1f.0 subsystem <- 8086/1e55 |
| PCI: 00:1f.0 cmd <- 107 |
| PCI: 00:1f.2 subsystem <- 8086/1e03 |
| PCI: 00:1f.2 cmd <- 03 |
| PCI: 00:1f.3 subsystem <- 8086/1e22 |
| PCI: 00:1f.3 cmd <- 103 |
| PCI: 00:1f.6 subsystem <- 8086/1e24 |
| PCI: 00:1f.6 cmd <- 02 |
| PCI: 01:00.0 cmd <- 02 |
| PCI: 02:00.0 cmd <- 06 |
| done. |
| Found TPM ST33ZP24 by ST Microelectronics |
| TPM: Startup |
| TPM: command 0x99 returned 0x0 |
| TPM: Asserting physical presence |
| TPM: command 0x4000000a returned 0x0 |
| TPM: command 0x65 returned 0x801 |
| TPM: Continue self test |
| TPM: command 0x53 returned 0x0 |
| TPM: command 0x65 returned 0x0 |
| TPM: flags disable=0, deactivated=0, nvlocked=1 |
| TPM: setup succeeded |
| BS: BS_DEV_INIT entry times (exec / console): 140 / 0 ms |
| POST: 0x75 |
| Timestamp - device initialization: 4205495378 |
| Initializing devices... |
| POST: 0x75 |
| CPU_CLUSTER: 0 init |
| MTRR: Physical address space: |
| 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 |
| 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 |
| 0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6 |
| 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 0 |
| 0x0000000090000000 - 0x00000000a0000000 size 0x10000000 type 1 |
| 0x00000000a0000000 - 0x0000000100000000 size 0x60000000 type 0 |
| 0x0000000100000000 - 0x000000047b600000 size 0x37b600000 type 6 |
| MTRR: Fixed MSR 0x250 0x0606060606060606 |
| MTRR: Fixed MSR 0x258 0x0606060606060606 |
| MTRR: Fixed MSR 0x259 0x0000000000000000 |
| MTRR: Fixed MSR 0x268 0x0606060606060606 |
| MTRR: Fixed MSR 0x269 0x0606060606060606 |
| MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| CPU physical address size: 36 bits |
| MTRR: default type WB/UC MTRR counts: 4/5. |
| MTRR: WB selected as default type. |
| MTRR: 0 base 0x0000000080000000 mask 0x0000000ff0000000 type 0 |
| MTRR: 1 base 0x0000000090000000 mask 0x0000000ff0000000 type 1 |
| MTRR: 2 base 0x00000000a0000000 mask 0x0000000fe0000000 type 0 |
| MTRR: 3 base 0x00000000c0000000 mask 0x0000000fc0000000 type 0 |
| |
| MTRR check |
| Fixed MTRRs : Enabled |
| Variable MTRRs: Enabled |
| |
| POST: 0x93 |
| CPU has 2 cores, 4 threads enabled. |
| Setting up SMI for CPU |
| Will perform SMM setup. |
| FMAP: area COREBOOT found @ c10200 (4128256 bytes) |
| CBFS: Locating 'cpu_microcode_blob.bin' |
| CBFS: Found @ offset 14c40 size 6800 |
| microcode: sig=0x306a9 pf=0x10 revision=0x21 |
| CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz. |
| Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170 |
| Processing 16 relocs. Offset value of 0x00030000 |
| Attempting to start 3 APs |
| Waiting for 10ms after sending INIT. |
| Waiting for 1st SIPI to complete...done. |
| Waiting for 2nd SIPI to complete...AP: slot 1 apic_id 1. |
| done. |
| AP: slot 2 apic_id 3. |
| AP: slot 3 apic_id 2. |
| Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8 |
| Processing 13 relocs. Offset value of 0x00038000 |
| SMM Module: stub loaded at 0x00038000. Will call 0x7ffa1a76(0x00000000) |
| Installing SMM handler to 0x80000000 |
| Loading module at 0x80010000 with entry 0x80010627. filesize: 0x1d50 memsize: 0x5da8 |
| Processing 84 relocs. Offset value of 0x80010000 |
| Loading module at 0x80008000 with entry 0x80008000. filesize: 0x1b8 memsize: 0x1b8 |
| Processing 13 relocs. Offset value of 0x80008000 |
| SMM Module: placing jmp sequence at 0x80007c00 rel16 0x03fd |
| SMM Module: placing jmp sequence at 0x80007800 rel16 0x07fd |
| SMM Module: placing jmp sequence at 0x80007400 rel16 0x0bfd |
| SMM Module: stub loaded at 0x80008000. Will call 0x80010627(0x00000000) |
| Initializing Southbridge SMI... |
| |
| New SMBASE 0x80000000 |
| In relocation handler: cpu 0 |
| New SMBASE=0x80000000 IEDBASE=0x80400000 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| microcode: Update skipped, already up-to-date |
| New SMBASE 0x7ffffc00 |
| In relocation handler: cpu 1 |
| New SMBASE=0x7ffffc00 IEDBASE=0x80400000 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| microcode: Update skipped, already up-to-date |
| New SMBASE 0x7ffff800 |
| In relocation handler: cpu 2 |
| New SMBASE=0x7ffff800 IEDBASE=0x80400000 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| microcode: Update skipped, already up-to-date |
| New SMBASE 0x7ffff400 |
| In relocation handler: cpu 3 |
| New SMBASE=0x7ffff400 IEDBASE=0x80400000 |
| Writing SMRR. base = 0x80000006, mask=0xff800800 |
| Relocation complete. |
| microcode: Update skipped, already up-to-date |
| Initializing CPU #0 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz. |
| CPU: platform id 4 |
| CPU: cpuid(1) 0x306a9 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| Setting up local APIC... |
| apic_id: 0x00 done. |
| IA32_FEATURE_CONTROL already locked; VMX status: enabled |
| IA32_FEATURE_CONTROL already locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2900 |
| Turbo is available but hidden |
| Turbo is available and visible |
| CPU #0 initialized |
| Initializing CPU #1 |
| Initializing CPU #2 |
| Initializing CPU #3 |
| CPU: vendor Intel device 306a9 |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| POST: 0x60 |
| Enabling cache |
| Enabling cache |
| CPU: vendor Intel device 306a9 |
| CPU: family 06, model 3a, stepping 09 |
| POST: 0x60 |
| Enabling cache |
| CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz. |
| CPU: platform id 4 |
| CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz. |
| CPU: cpuid(1) 0x306a9 |
| CPU: platform id 4 |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| CPU: cpuid(1) 0x306a9 |
| Setting up local APIC... |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| CPU: Intel(R) Core(TM) i7-3520M CPU @ 2.90GHz. |
| apic_id: 0x02 done. |
| Setting up local APIC... |
| IA32_FEATURE_CONTROL already locked; VMX status: enabled |
| CPU: platform id 4 |
| apic_id: 0x03 done. |
| IA32_FEATURE_CONTROL already locked |
| IA32_FEATURE_CONTROL already locked; VMX status: enabled |
| CPU: cpuid(1) 0x306a9 |
| IA32_FEATURE_CONTROL already locked |
| CPU: AES supported |
| CPU: TXT supported |
| CPU: VT supported |
| Setting up local APIC... |
| apic_id: 0x01 done. |
| IA32_FEATURE_CONTROL already locked; VMX status: enabled |
| IA32_FEATURE_CONTROL already locked |
| model_x06ax: energy policy set to 6 |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2900 |
| CPU #3 initialized |
| model_x06ax: frequency set to 2900 |
| CPU #2 initialized |
| model_x06ax: energy policy set to 6 |
| model_x06ax: frequency set to 2900 |
| CPU #1 initialized |
| bsp_do_flight_plan done after 8 msecs. |
| Initializing southbridge SMI... |
| SMI_STS: |
| GPE0_STS: GPIO14 GPIO11 GPIO9 GPIO7 GPIO5 GPIO4 GPIO3 GPIO2 |
| ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 |
| TCO_STS: |
| Locking SMM. |
| CPU_CLUSTER: 0 init finished in 22 msecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:00.0 init |
| Disabling PEG12. |
| Disabling PEG11. |
| Disabling PEG10. |
| Disabling PEG60. |
| Disabling Device 7. |
| Disabling PEG IO clock. |
| Set BIOS_RESET_CPL |
| CPU TDP: 35 Watts |
| PCI: 00:00.0 init finished in 1 msecs |
| POST: 0x75 |
| PCI: 00:02.0 init |
| FMAP: area COREBOOT found @ c10200 (4128256 bytes) |
| CBFS: Locating 'vbt.bin' |
| CBFS: Found @ offset 426c0 size 581 |
| Timestamp - starting LZMA decompress (ignore for x86): 4273650627 |
| Timestamp - finished LZMA decompress (ignore for x86): 4274820171 |
| Found a VBT of 4459 bytes after decompression |
| GMA: Found VBT in CBFS |
| GMA: Found valid VBT in CBFS |
| GT Power Management Init |
| IVB GT2 25W-35W Power Meter Weights |
| GT Power Management Init (post VBIOS) |
| PCI: 00:02.0 init finished in 0 msecs |
| POST: 0x75 |
| PCI: 00:04.0 init |
| PCI: 00:04.0 init finished in 0 msecs |
| POST: 0x75 |
| PCI: 00:14.0 init |
| XHCI: Setting up controller.. done. |
| PCI: 00:14.0 init finished in 0 msecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:19.0 init |
| PCI: 00:19.0 init finished in 0 msecs |
| POST: 0x75 |
| PCI: 00:1a.0 init |
| EHCI: Setting up controller.. done. |
| PCI: 00:1a.0 init finished in 0 msecs |
| POST: 0x75 |
| PCI: 00:1b.0 init |
| Azalia: base = 82a38000 |
| Azalia: codec_mask = 09 |
| Azalia: Initializing codec #3 |
| Azalia: codec viddid: 80862806 |
| Azalia: verb_size: 16 |
| Azalia: verb loaded. |
| Azalia: Initializing codec #0 |
| Azalia: codec viddid: 10ec0269 |
| Azalia: verb_size: 76 |
| Azalia: verb loaded. |
| PCI: 00:1b.0 init finished in 5 msecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1c.0 init |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.0 init finished in 0 msecs |
| POST: 0x75 |
| PCI: 00:1c.1 init |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.1 init finished in 0 msecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1c.2 init |
| Initializing PCH PCIe bridge. |
| PCI: 00:1c.2 init finished in 0 msecs |
| POST: 0x75 |
| PCI: 00:1d.0 init |
| EHCI: Setting up controller.. done. |
| PCI: 00:1d.0 init finished in 0 msecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1f.0 init |
| pch: lpc_init |
| PCH: detected QM77, device id: 0x1e55, rev id 0x4 |
| IOAPIC: Initializing IOAPIC at 0xfec00000 |
| IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| IOAPIC: ID = 0x02 |
| Set power off after power failure. |
| NMI sources enabled. |
| PantherPoint PM init |
| RTC: failed = 0x0 |
| RTC Init |
| Disabling ACPI via APMC: |
| done. |
| pch_spi_init |
| PCI: 00:1f.0 init finished in 0 msecs |
| POST: 0x75 |
| PCI: 00:1f.2 init |
| SATA: Initializing... |
| SATA: Controller in AHCI mode. |
| ABAR: 0x82a3e000 |
| PCI: 00:1f.2 init finished in 0 msecs |
| POST: 0x75 |
| PCI: 00:1f.3 init |
| PCI: 00:1f.3 init finished in 0 msecs |
| POST: 0x75 |
| POST: 0x75 |
| PCI: 00:1f.6 init |
| PCI: 00:1f.6 init finished in 0 msecs |
| POST: 0x75 |
| PCI: 01:00.0 init |
| PCI: 01:00.0 init finished in 0 msecs |
| POST: 0x75 |
| PCI: 02:00.0 init |
| PCI: 02:00.0 init finished in 0 msecs |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| POST: 0x75 |
| PNP: 00ff.2 init |
| PNP: 00ff.2 init finished in 0 msecs |
| POST: 0x75 |
| smbus: PCI: 00:1f.3[0]->I2C: 01:54 init |
| I2C: 01:54 init finished in 0 msecs |
| POST: 0x75 |
| smbus: PCI: 00:1f.3[0]->I2C: 01:55 init |
| I2C: 01:55 init finished in 0 msecs |
| POST: 0x75 |
| smbus: PCI: 00:1f.3[0]->I2C: 01:56 init |
| I2C: 01:56 init finished in 0 msecs |
| POST: 0x75 |
| smbus: PCI: 00:1f.3[0]->I2C: 01:57 init |
| I2C: 01:57 init finished in 0 msecs |
| POST: 0x75 |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5c init |
| Locking EEPROM RFID |
| init EEPROM done |
| I2C: 01:5c init finished in 24 msecs |
| POST: 0x75 |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5d init |
| I2C: 01:5d init finished in 0 msecs |
| POST: 0x75 |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5e init |
| I2C: 01:5e init finished in 0 msecs |
| POST: 0x75 |
| smbus: PCI: 00:1f.3[0]->I2C: 01:5f init |
| I2C: 01:5f init finished in 0 msecs |
| Devices initialized |
| BS: BS_DEV_INIT run times (exec / console): 56 / 0 ms |
| POST: 0x76 |
| Finalize devices... |
| PCI: 00:1f.0 final |
| Devices finalized |
| Timestamp - device setup done: 4368484075 |
| POST: 0x77 |
| Timestamp - cbmem post: 4368488723 |
| POST: 0x79 |
| Timestamp - write tables: 4368492519 |
| POST: 0x9c |
| FMAP: area COREBOOT found @ c10200 (4128256 bytes) |
| CBFS: Locating 'fallback/dsdt.aml' |
| CBFS: Found @ offset 3ed40 size 3926 |
| FMAP: area COREBOOT found @ c10200 (4128256 bytes) |
| CBFS: Locating 'fallback/slic' |
| CBFS: 'fallback/slic' not found. |
| ACPI: Writing ACPI tables at 7ff4b000. |
| ACPI: * FACS |
| ACPI: * DSDT |
| ACPI: * FADT |
| ACPI: added table 1/32, length now 40 |
| ACPI: * SSDT |
| Found 1 CPU(s) with 4 core(s) each. |
| PSS: 2901MHz power 35000 control 0x2400 status 0x2400 |
| PSS: 2900MHz power 35000 control 0x1d00 status 0x1d00 |
| PSS: 2400MHz power 27295 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 21703 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 16527 control 0x1000 status 0x1000 |
| PSS: 1200MHz power 11795 control 0xc00 status 0xc00 |
| PSS: 2901MHz power 35000 control 0x2400 status 0x2400 |
| PSS: 2900MHz power 35000 control 0x1d00 status 0x1d00 |
| PSS: 2400MHz power 27295 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 21703 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 16527 control 0x1000 status 0x1000 |
| PSS: 1200MHz power 11795 control 0xc00 status 0xc00 |
| PSS: 2901MHz power 35000 control 0x2400 status 0x2400 |
| PSS: 2900MHz power 35000 control 0x1d00 status 0x1d00 |
| PSS: 2400MHz power 27295 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 21703 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 16527 control 0x1000 status 0x1000 |
| PSS: 1200MHz power 11795 control 0xc00 status 0xc00 |
| PSS: 2901MHz power 35000 control 0x2400 status 0x2400 |
| PSS: 2900MHz power 35000 control 0x1d00 status 0x1d00 |
| PSS: 2400MHz power 27295 control 0x1800 status 0x1800 |
| PSS: 2000MHz power 21703 control 0x1400 status 0x1400 |
| PSS: 1600MHz power 16527 control 0x1000 status 0x1000 |
| PSS: 1200MHz power 11795 control 0xc00 status 0xc00 |
| Generating ACPI PIRQ entries |
| \_SB.PCI0.LPCB.TPM.TPM: LPC TPM PNP: 0c31.0 |
| ACPI: * H8 |
| H8: BDC detection not implemented. Assuming BDC installed |
| H8: WWAN detection not implemented. Assuming WWAN installed |
| ACPI: added table 2/32, length now 44 |
| ACPI: * MCFG |
| ACPI: added table 3/32, length now 48 |
| ACPI: * TCPA |
| TCPA log created at 0x7ff3a000 |
| ACPI: added table 4/32, length now 52 |
| ACPI: * MADT |
| ACPI: added table 5/32, length now 56 |
| current = 7ff508a0 |
| ACPI: * DMAR |
| ACPI: added table 6/32, length now 60 |
| current = 7ff50970 |
| ACPI: * HPET |
| ACPI: added table 7/32, length now 64 |
| ACPI: done. |
| ACPI tables: 22960 bytes. |
| smbios_write_tables: 7ff39000 |
| Create SMBIOS type 17 |
| SMBIOS tables: 887 bytes. |
| Writing table forward entry at 0x00000500 |
| Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 8fe7 |
| Writing coreboot table at 0x7ff6f000 |
| FMAP: area COREBOOT found @ c10200 (4128256 bytes) |
| CBFS: Locating 'cmos_layout.bin' |
| CBFS: Found @ offset 42dc0 size 78c |
| 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| 1. 0000000000001000-000000000009ffff: RAM |
| 2. 00000000000a0000-00000000000fffff: RESERVED |
| 3. 0000000000100000-000000007ff38fff: RAM |
| 4. 000000007ff39000-000000007ff89fff: CONFIGURATION TABLES |
| 5. 000000007ff8a000-000000007ffcffff: RAMSTAGE |
| 6. 000000007ffd0000-000000007fffffff: CONFIGURATION TABLES |
| 7. 0000000080000000-00000000829fffff: RESERVED |
| 8. 00000000f0000000-00000000f3ffffff: RESERVED |
| 9. 00000000fed40000-00000000fed44fff: RESERVED |
| 10. 00000000fed90000-00000000fed91fff: RESERVED |
| 11. 0000000100000000-000000047b5fffff: RAM |
| FMAP: area COREBOOT found @ c10200 (4128256 bytes) |
| Wrote coreboot table at: 0x7ff6f000, 0xb20 bytes, checksum ef87 |
| coreboot table: 2872 bytes. |
| IMD ROOT 0. 0x7ffff000 0x00001000 |
| IMD SMALL 1. 0x7fffe000 0x00001000 |
| CONSOLE 2. 0x7ffde000 0x00020000 |
| TIME STAMP 3. 0x7ffdd000 0x00000910 |
| MRC DATA 4. 0x7ffdc000 0x00000644 |
| ROMSTG STCK 5. 0x7ffdb000 0x00001000 |
| AFTER CAR 6. 0x7ffd0000 0x0000b000 |
| RAMSTAGE 7. 0x7ff89000 0x00047000 |
| SMM BACKUP 8. 0x7ff79000 0x00010000 |
| 4f444749 9. 0x7ff77000 0x00002000 |
| COREBOOT 10. 0x7ff6f000 0x00008000 |
| ACPI 11. 0x7ff4b000 0x00024000 |
| ACPI GNVS 12. 0x7ff4a000 0x00001000 |
| TCPA TCGLOG13. 0x7ff3a000 0x00010000 |
| SMBIOS 14. 0x7ff39000 0x00000800 |
| IMD small region: |
| IMD ROOT 0. 0x7fffec00 0x00000400 |
| FMAP 1. 0x7fffeb20 0x000000e0 |
| MEM INFO 2. 0x7fffe960 0x000001b9 |
| ROMSTAGE 3. 0x7fffe940 0x00000004 |
| Timestamp - finalize chips: 4442940827 |
| BS: BS_WRITE_TABLES run times (exec / console): 26 / 0 ms |
| POST: 0x7a |
| Timestamp - load payload: 4442948679 |
| FMAP: area COREBOOT found @ c10200 (4128256 bytes) |
| CBFS: Locating 'fallback/payload' |
| CBFS: Found @ offset 76c40 size 1606a |
| Checking segment from ROM address 0xffc86e78 |
| Payload being loaded at below 1MiB without region being marked as RAM usable. |
| Checking segment from ROM address 0xffc86e94 |
| Loading segment from ROM address 0xffc86e78 |
| code (compression=2) |
| New segment dstaddr 0x000dffa0 memsize 0x20060 srcaddr 0xffc86eb0 filesize 0x16032 |
| Loading Segment: addr: 0x000dffa0 memsz: 0x0000000000020060 filesz: 0x0000000000016032 |
| using LZ4 |
| Timestamp - starting LZ4 decompress (ignore for x86): 4443434375 |
| Timestamp - finished LZ4 decompress (ignore for x86): 4574004735 |
| Loading segment from ROM address 0xffc86e94 |
| Entry Point 0x000fd25e |
| BS: BS_PAYLOAD_LOAD run times (exec / console): 45 / 0 ms |
| POST: 0x7b |
| ICH-NM10-PCH: watchdog disabled |
| Jumping to boot code at 0x000fd25e(0x7ff6f000) |
| POST: 0xf8 |
| Timestamp - selfboot jump: 4574113207 |
| SeaBIOS (version rel-1.13.0-41-g2e3de62) |
| BUILD: gcc: (coreboot toolchain v6b5bc77c9b 2020-05-10) 8.3.0 binutils: (GNU Binutils) 2.33.1 |
| Found coreboot cbmem console @ 7ffde000 |
| Found mainboard LENOVO ThinkPad T430s |
| Relocating init from 0x000e16c0 to 0x7feebc60 (size 54016) |
| Found CBFS header at 0xffc10238 |
| multiboot: eax=7ffb9ae0, ebx=7ffb9aa4 |
| Found 17 PCI devices (max PCI bus is 03) |
| Copying SMBIOS entry point from 0x7ff39000 to 0x000f6780 |
| Copying ACPI RSDP from 0x7ff4b000 to 0x000f6750 |
| table(50434146)=0x7ff4ebc0 (via xsdt) |
| Using pmtimer, ioport 0x508 |
| table(41504354)=0x7ff507f0 (via xsdt) |
| Scan for VGA option rom |
| Running option rom at c000:0003 |
| Turning on vga text mode console |
| SeaBIOS (version rel-1.13.0-41-g2e3de62) |
| Machine UUID 89966681-43e8-11cb-86b2-c243510b3449 |
| XHCI init on dev 00:14.0: regs @ 0x82a20000, 8 ports, 32 slots, 32 byte contexts |
| XHCI protocol USB 2.00, 4 ports (offset 1), def 3001 |
| XHCI protocol USB 3.00, 4 ports (offset 5), def 1000 |
| XHCI extcap 0xc1 @ 0x82a28040 |
| XHCI extcap 0xc0 @ 0x82a28070 |
| XHCI extcap 0x1 @ 0x82a28330 |
| EHCI init on dev 00:1a.0 (regs=0x82a3f020) |
| EHCI init on dev 00:1d.0 (regs=0x82a40020) |
| AHCI controller at 00:1f.2, iobase 0x82a3e000, irq 11 |
| Searching bootorder for: /pci@i0cf8/pci-bridge@1c,1/*@0 |
| Searching bootorder for: HALT |
| Found 0 lpt ports |
| Found 0 serial ports |
| Searching bootorder for: /rom@img/memtest |
| Searching bootorder for: /rom@img/tint |
| Searching bootorder for: /rom@img/nvramcui |
| Searching bootorder for: /rom@img/coreinfo |
| Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0 |
| AHCI/0: Set transfer mode to UDMA-6 |
| Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0 |
| AHCI/0: registering: "AHCI/0: KINGSTON SKC400S37512G ATA-9 Hard-Disk (476 GiBytes)" |
| Searching bootorder for: /pci@i0cf8/*@1f,2/drive@1/disk@0 |
| AHCI/1: Set transfer mode to UDMA-6 |
| Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@1/disk@0 |
| AHCI/1: registering: "AHCI/1: ST2000LM015-2E8174 ATA-10 Hard-Disk (1863 GiBytes)" |
| Found sdcard at 0x83400000: SD card SD02G 1938MiB |
| XHCI no devices found |
| Initialized USB HUB (0 ports used) |
| USB keyboard initialized |
| PS2 keyboard initialized |
| Initialized USB HUB (0 ports used) |
| Initialized USB HUB (1 ports used) |
| Initialized USB HUB (0 ports used) |
| Initialized USB HUB (0 ports used) |
| Initialized USB HUB (0 ports used) |
| Initialized USB HUB (0 ports used) |
| Initialized USB HUB (1 ports used) |
| All threads complete. |
| Scan for option roms |
| Running option rom at cf80:0003 |
| pmm call arg1=1 |
| pmm call arg1=0 |
| pmm call arg1=1 |
| pmm call arg1=0 |
| Searching bootorder for: /pci@i0cf8/*@19 |
| |
| Press ESC for boot menu. |
| |
| Turning on vga text mode console |
| SeaBIOS (version rel-1.13.0-41-g2e3de62) |
| Machine UUID 89966681-43e8-11cb-86b2-c243510b3449 |
| Select boot device: |
| |
| 1. AHCI/0: KINGSTON SKC400S37512G ATA-9 Hard-Disk (476 GiBytes) |
| 2. AHCI/1: ST2000LM015-2E8174 ATA-10 Hard-Disk (1863 GiBytes) |
| 3. SD card SD02G 1938MiB |
| 4. iPXE (PCI 00:19.0) |
| 5. Payload [memtest] |
| 6. Payload [tint] |
| 7. Payload [nvramcui] |
| 8. Payload [coreinfo] |
| |
| t. TPM Configuration |
| |
| Searching bootorder for: HALT |
| drive 0x000f66e0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1000215216 |
| drive 0x000f6660: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=3907029168 |
| drive 0x000f66b0: PCHS=0/0/0 translation=lba LCHS=984/64/63 s=3970048 |
| Space available for UMB: d0800-ed000, f5fa0-f6660 |
| Returned 180224 bytes of ZoneHigh |
| e820 map has 9 items: |
| 0: 0000000000000000 - 000000000009fc00 = 1 RAM |
| 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED |
| 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED |
| 3: 0000000000100000 - 000000007ff25000 = 1 RAM |
| 4: 000000007ff25000 - 0000000082a00000 = 2 RESERVED |
| 5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED |
| 6: 00000000fed40000 - 00000000fed45000 = 2 RESERVED |
| 7: 00000000fed90000 - 00000000fed92000 = 2 RESERVED |
| 8: 0000000100000000 - 000000047b600000 = 1 RAM |
| enter handle_19: |
| NULL |
| Booting from ROM... |
| Booting from cf80:0385 |
| enter handle_18: |
| NULL |
| Booting from Hard Disk... |
| Booting from 0000:7c00 |
| |