| *** Pre-CBMEM romstage console overflowed, log truncated! *** |
| 1, tCK 320. |
| [DEBUG] Found compatible clock, CAS pair. |
| [DEBUG] Selected DRAM frequency: 800 MHz |
| [DEBUG] Selected CAS latency : 11T |
| [DEBUG] MPLL busy... done in 40 us |
| [DEBUG] MPLL frequency is set at : 800 MHz |
| [DEBUG] Selected CWL latency : 8T |
| [DEBUG] Selected tRCD : 11T |
| [DEBUG] Selected tRP : 11T |
| [DEBUG] Selected tRAS : 28T |
| [DEBUG] Selected tWR : 12T |
| [DEBUG] Selected tFAW : 24T |
| [DEBUG] Selected tRRD : 5T |
| [DEBUG] Selected tRTP : 6T |
| [DEBUG] Selected tWTR : 6T |
| [DEBUG] Selected tRFC : 208T |
| [DEBUG] Done dimm mapping |
| [DEBUG] Update PCI-E configuration space: |
| [DEBUG] PCI(0, 0, 0)[a0] = 0 |
| [DEBUG] PCI(0, 0, 0)[a4] = 4 |
| [DEBUG] PCI(0, 0, 0)[bc] = 82a00000 |
| [DEBUG] PCI(0, 0, 0)[a8] = 7d600000 |
| [DEBUG] PCI(0, 0, 0)[ac] = 4 |
| [DEBUG] PCI(0, 0, 0)[b8] = 80000000 |
| [DEBUG] PCI(0, 0, 0)[b0] = 80a00000 |
| [DEBUG] PCI(0, 0, 0)[b4] = 80800000 |
| [DEBUG] Done memory map |
| [DEBUG] Done io registers |
| [DEBUG] Done jedec reset |
| [DEBUG] Done MRS commands |
| [WARN ] Logic delay 2 greater than 1: 0 0 |
| [WARN ] Logic delay 2 greater than 1: 0 1 |
| [WARN ] Logic delay 2 greater than 1: 1 0 |
| [DEBUG] t123: 1767, 6000, 7620 |
| [NOTE ] ME: Wrong mode : 2 |
| [NOTE ] ME: FWS2: 0x100a0140 |
| [NOTE ] ME: Bist in progress: 0x0 |
| [NOTE ] ME: ICC Status : 0x0 |
| [NOTE ] ME: Invoke MEBx : 0x0 |
| [NOTE ] ME: CPU replaced : 0x0 |
| [NOTE ] ME: MBP ready : 0x0 |
| [NOTE ] ME: MFS failure : 0x1 |
| [NOTE ] ME: Warm reset req : 0x0 |
| [NOTE ] ME: CPU repl valid : 0x1 |
| [NOTE ] ME: (Reserved) : 0x0 |
| [NOTE ] ME: FW update req : 0x0 |
| [NOTE ] ME: (Reserved) : 0x0 |
| [NOTE ] ME: Current state : 0xa |
| [NOTE ] ME: Current PM event: 0x0 |
| [NOTE ] ME: Progress code : 0x1 |
| [NOTE ] PASSED! Tell ME that DRAM is ready |
| [NOTE ] ME: ME is reporting as disabled, so not waiting for a response. |
| [NOTE ] ME: FWS2: 0x100a0140 |
| [NOTE ] ME: Bist in progress: 0x0 |
| [NOTE ] ME: ICC Status : 0x0 |
| [NOTE ] ME: Invoke MEBx : 0x0 |
| [NOTE ] ME: CPU replaced : 0x0 |
| [NOTE ] ME: MBP ready : 0x0 |
| [NOTE ] ME: MFS failure : 0x1 |
| [NOTE ] ME: Warm reset req : 0x0 |
| [NOTE ] ME: CPU repl valid : 0x1 |
| [NOTE ] ME: (Reserved) : 0x0 |
| [NOTE ] ME: FW update req : 0x0 |
| [NOTE ] ME: (Reserved) : 0x0 |
| [NOTE ] ME: Current state : 0xa |
| [NOTE ] ME: Current PM event: 0x0 |
| [NOTE ] ME: Progress code : 0x1 |
| [NOTE ] ME: Requested BIOS Action: No DID Ack received |
| [DEBUG] ME: FW Partition Table : OK |
| [DEBUG] ME: Bringup Loader Failure : NO |
| [DEBUG] ME: Firmware Init Complete : NO |
| [DEBUG] ME: Manufacturing Mode : YES |
| [DEBUG] ME: Boot Options Present : NO |
| [DEBUG] ME: Update In Progress : NO |
| [DEBUG] ME: Current Working State : Initializing |
| [DEBUG] ME: Current Operation State : Bring up |
| [DEBUG] ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| [DEBUG] ME: Error Code : No Error |
| [DEBUG] ME: Progress Phase : BUP Phase |
| [DEBUG] ME: Power Management Event : Clean Moff->Mx wake |
| [DEBUG] ME: Progress Phase State : Check to see if straps say ME DISABLED |
| [DEBUG] memcfg DDR3 ref clock 133 MHz |
| [DEBUG] memcfg DDR3 clock 1596 MHz |
| [DEBUG] memcfg channel assignment: A: 0, B 1, C 2 |
| [DEBUG] memcfg channel[0] config (00620020): |
| [DEBUG] ECC inactive |
| [DEBUG] enhanced interleave mode on |
| [DEBUG] rank interleave on |
| [DEBUG] DIMMA 8192 MB width x8 dual rank, selected |
| [DEBUG] DIMMB 0 MB width x8 single rank |
| [DEBUG] memcfg channel[1] config (00620020): |
| [DEBUG] ECC inactive |
| [DEBUG] enhanced interleave mode on |
| [DEBUG] rank interleave on |
| [DEBUG] DIMMA 8192 MB width x8 dual rank, selected |
| [DEBUG] DIMMB 0 MB width x8 single rank |
| [DEBUG] CBMEM: |
| [DEBUG] IMD: root @ 0x7ffff000 254 entries. |
| [DEBUG] IMD: root @ 0x7fffec00 62 entries. |
| [DEBUG] External stage cache: |
| [DEBUG] IMD: root @ 0x803ff000 254 entries. |
| [DEBUG] IMD: root @ 0x803fec00 62 entries. |
| [DEBUG] CBMEM entry for DIMM info: 0x7ffda000 |
| [DEBUG] SMM Memory Map |
| [DEBUG] SMRAM : 0x80000000 0x800000 |
| [DEBUG] Subregion 0: 0x80000000 0x300000 |
| [DEBUG] Subregion 1: 0x80300000 0x100000 |
| [DEBUG] Subregion 2: 0x80400000 0x400000 |
| [DEBUG] Normal boot |
| [INFO ] CBFS: Found 'fallback/postcar' @0x48280 size 0x5174 in mcache @0xfeff109c |
| [DEBUG] Loading module at 0x7ffce000 with entry 0x7ffce031. filesize: 0x4da0 memsize: 0xb0d8 |
| [DEBUG] Processing 229 relocs. Offset value of 0x7dfce000 |
| [DEBUG] BS: romstage times (exec / console): total (unknown) / 2 ms |
| |
| |
| [NOTE ] coreboot-4.16-1239-gd5c31acee4 Mon May 30 08:04:13 UTC 2022 postcar starting (log level: 7)... |
| [DEBUG] Normal boot |
| [INFO ] CBFS: Found 'fallback/ramstage' @0x19f40 size 0x1ea38 in mcache @0x7ffdd0dc |
| [DEBUG] Loading module at 0x7ff6c000 with entry 0x7ff6c000. filesize: 0x3d438 memsize: 0x60710 |
| [DEBUG] Processing 4384 relocs. Offset value of 0x7bf6c000 |
| [DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms |
| |
| |
| [NOTE ] coreboot-4.16-1239-gd5c31acee4 Mon May 30 08:04:13 UTC 2022 ramstage starting (log level: 7)... |
| [DEBUG] Normal boot |
| [INFO ] Enumerating buses... |
| [DEBUG] Root Device scanning... |
| [DEBUG] CPU_CLUSTER: 0 enabled |
| [DEBUG] DOMAIN: 0000 enabled |
| [DEBUG] DOMAIN: 0000 scanning... |
| [DEBUG] PCI: pci_scan_bus for bus 00 |
| [DEBUG] PCI: 00:00.0 [8086/0154] enabled |
| [INFO ] PCI: Static device PCI: 00:01.0 not found, disabling it. |
| [DEBUG] PCI: 00:02.0 [8086/0166] enabled |
| [DEBUG] PCI: 00:04.0 [8086/0153] disabled |
| [DEBUG] PCI: 00:14.0 [8086/1e31] enabled |
| [DEBUG] PCI: 00:16.0 [8086/1e3a] enabled |
| [DEBUG] PCI: 00:16.1: Disabling device |
| [DEBUG] PCI: 00:16.2: Disabling device |
| [DEBUG] PCI: 00:16.3: Disabling device |
| [DEBUG] PCI: 00:19.0 [8086/1502] enabled |
| [DEBUG] PCI: 00:1a.0 [8086/1e2d] enabled |
| [DEBUG] PCI: 00:1b.0 [8086/1e20] enabled |
| [INFO ] PCH: PCIe Root Port coalescing is enabled |
| [DEBUG] PCI: 00:1c.0 [8086/1e10] enabled |
| [DEBUG] PCI: 00:1c.1 [8086/1e12] enabled |
| [DEBUG] PCI: 00:1c.2 [8086/1e14] enabled |
| [DEBUG] PCI: 00:1c.3: Disabling device |
| [DEBUG] PCI: 00:1c.3 [8086/1e16] disabled |
| [DEBUG] PCI: 00:1c.4: Disabling device |
| [DEBUG] PCI: 00:1c.4: check set enabled |
| [DEBUG] PCI: 00:1c.5: Disabling device |
| [DEBUG] PCI: 00:1c.6: Disabling device |
| [DEBUG] PCI: 00:1c.7: Disabling device |
| [DEBUG] PCI: 00:1d.0 [8086/1e26] enabled |
| [DEBUG] PCI: 00:1e.0: Disabling device |
| [DEBUG] PCI: 00:1e.0 [8086/2448] disabled |
| [DEBUG] PCI: 00:1f.0 [8086/1e55] enabled |
| [DEBUG] PCI: 00:1f.2 [8086/1e01] enabled |
| [DEBUG] PCI: 00:1f.3 [8086/1e22] enabled |
| [DEBUG] PCI: 00:1f.5: Disabling device |
| [DEBUG] PCI: 00:1f.5 [8086/1e09] disabled No operations |
| [DEBUG] PCI: 00:1f.6: Disabling device |
| [DEBUG] PCI: 00:1f.6 [8086/1e24] disabled No operations |
| [WARN ] PCI: Leftover static devices: |
| [WARN ] PCI: 00:01.0 |
| [WARN ] PCI: 00:16.1 |
| [WARN ] PCI: 00:16.2 |
| [WARN ] PCI: 00:16.3 |
| [WARN ] PCI: 00:1c.4 |
| [WARN ] PCI: 00:1c.5 |
| [WARN ] PCI: 00:1c.6 |
| [WARN ] PCI: 00:1c.7 |
| [WARN ] PCI: Check your devicetree.cb. |
| [DEBUG] PCI: 00:1c.0 scanning... |
| [DEBUG] PCI: 00:1c.0: No LTR support |
| [DEBUG] PCI: pci_scan_bus for bus 01 |
| [DEBUG] PCI: 01:00.0 [1180/e823] enabled |
| [INFO ] Enabling Common Clock Configuration |
| [INFO ] ASPM: Enabled L0s and L1 |
| [INFO ] PCIe: Max_Payload_Size adjusted to 128 |
| [DEBUG] PCI: 01:00.0: No LTR support |
| [DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 0 msecs |
| [DEBUG] PCI: 00:1c.1 scanning... |
| [DEBUG] PCI: 00:1c.1: No LTR support |
| [DEBUG] PCI: pci_scan_bus for bus 02 |
| [DEBUG] PCI: 02:00.0 [168c/002a] enabled |
| [INFO ] Enabling Common Clock Configuration |
| [INFO ] ASPM: Enabled L0s and L1 |
| [INFO ] PCIe: Max_Payload_Size adjusted to 128 |
| [DEBUG] PCI: 02:00.0: No LTR support |
| [DEBUG] scan_bus: bus PCI: 00:1c.1 finished in 0 msecs |
| [DEBUG] PCI: 00:1c.2 scanning... |
| [DEBUG] PCI: 00:1c.2: No LTR support |
| [DEBUG] PCI: pci_scan_bus for bus 03 |
| [DEBUG] scan_bus: bus PCI: 00:1c.2 finished in 0 msecs |
| [DEBUG] PCI: 00:1f.0 scanning... |
| [INFO ] PMH7: ID 05 Revision 00 |
| [DEBUG] PNP: 00ff.1 enabled |
| [INFO ] H8: EC Firmware ID G1HT36WW-3.22, Version 4.01B |
| [DEBUG] No CMOS option 'power_management_beeps'. |
| [DEBUG] No CMOS option 'low_battery_beep'. |
| [INFO ] H8: BDC not installed |
| [INFO ] H8: WWAN not installed |
| [DEBUG] PNP: 00ff.2 enabled |
| [DEBUG] Hybrid graphics: Not installed |
| [DEBUG] PNP: 00ff.f disabled |
| [DEBUG] PNP: 0c31.0 enabled |
| [DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 4 msecs |
| [DEBUG] PCI: 00:1f.3 scanning... |
| [DEBUG] I2C: 01:54 enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:55 enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:56 enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:57 enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5c enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5d enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5e enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->I2C: 01:5f enabled |
| [DEBUG] bus: PCI: 00:1f.3[0]->scan_bus: bus PCI: 00:1f.3 finished in 0 msecs |
| [DEBUG] scan_bus: bus DOMAIN: 0000 finished in 5 msecs |
| [DEBUG] scan_bus: bus Root Device finished in 5 msecs |
| [INFO ] done |
| [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 5 / 0 ms |
| [DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes) |
| [DEBUG] FMAP: area RW_MRC_CACHE found @ 800000 (65536 bytes) |
| [DEBUG] MRC: Checking cached data update for 'RW_MRC_CACHE'. |
| [DEBUG] flash size 0xc00000 bytes |
| [INFO ] SF: Detected 00 0000 with sector size 0x100, total 0xc00000 |
| [NOTE ] MRC: no data in 'RW_MRC_CACHE' |
| [DEBUG] MRC: cache data 'RW_MRC_CACHE' needs update. |
| [DEBUG] SF: Successfully written 2 bytes @ 0x800000 |
| [DEBUG] SF: Successfully written 2 bytes @ 0x800002 |
| [DEBUG] SF: Successfully written 16 bytes @ 0x800050 |
| [DEBUG] SF: Successfully written 1588 bytes @ 0x800060 |
| [DEBUG] MRC: updated 'RW_MRC_CACHE'. |
| [DEBUG] BS: BS_DEV_ENUMERATE exit times (exec / console): 19 / 0 ms |
| [DEBUG] found VGA at PCI: 00:02.0 |
| [DEBUG] Setting up VGA for PCI: 00:02.0 |
| [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| [INFO ] Allocating resources... |
| [INFO ] Reading resources... |
| [DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| [DEBUG] TOUUD 0x47d600000 TOLUD 0x82a00000 TOM 0x400000000 |
| [DEBUG] MEBASE 0x7ffff00000 |
| [DEBUG] IGD decoded, subtracting 32M UMA and 2M GTT |
| [DEBUG] TSEG base 0x80000000 size 8M |
| [INFO ] Available memory below 4GB: 2048M |
| [INFO ] Available memory above 4GB: 14294M |
| [ERROR] PNP: 00ff.1 missing read_resources |
| [ERROR] PNP: 00ff.2 missing read_resources |
| [INFO ] Done reading resources. |
| [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === |
| [DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 01:00.0 10 * [0x0 - 0xff] mem |
| [DEBUG] PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| [DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] PCI: 00:1c.1 io: size: 0 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:1c.1 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 02:00.0 10 * [0x0 - 0xffff] mem |
| [DEBUG] PCI: 00:1c.1 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] PCI: 00:1c.1 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done |
| [DEBUG] PCI: 00:1c.2 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] NONE 18 * [0x0 - 0x1fff] io |
| [DEBUG] PCI: 00:1c.2 io: size: 2000 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:1c.2 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] NONE 10 * [0x0 - 0x7fffff] mem |
| [DEBUG] PCI: 00:1c.2 mem: size: 800000 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:1c.2 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] NONE 14 * [0x0 - 0xfffffff] prefmem |
| [DEBUG] PCI: 00:1c.2 prefmem: size: 10000000 align: 20 gran: 20 limit: ffffffffffffffff done |
| [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === |
| [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| [DEBUG] update_constraints: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.0 10000200 base 000015e0 limit 000015eb io (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.0 10000300 base 00001600 limit 0000167b io (fixed) |
| [DEBUG] update_constraints: PNP: 00ff.1 77 base 000015e0 limit 000015ef io (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed) |
| [INFO ] DOMAIN: 0000: Resource ranges: |
| [INFO ] * Base: 1000, Size: 5e0, Tag: 100 |
| [INFO ] * Base: 15f0, Size: 10, Tag: 100 |
| [INFO ] * Base: 167c, Size: e984, Tag: 100 |
| [DEBUG] PCI: 00:1c.2 1c * [0x2000 - 0x3fff] limit: 3fff io |
| [DEBUG] PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io |
| [DEBUG] PCI: 00:19.0 18 * [0x1040 - 0x105f] limit: 105f io |
| [DEBUG] PCI: 00:1f.2 20 * [0x1060 - 0x107f] limit: 107f io |
| [DEBUG] PCI: 00:1f.2 10 * [0x1080 - 0x1087] limit: 1087 io |
| [DEBUG] PCI: 00:1f.2 18 * [0x1088 - 0x108f] limit: 108f io |
| [DEBUG] PCI: 00:1f.2 14 * [0x1090 - 0x1093] limit: 1093 io |
| [DEBUG] PCI: 00:1f.2 1c * [0x1094 - 0x1097] limit: 1097 io |
| [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done |
| [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff |
| [DEBUG] update_constraints: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 03 base 00000000 limit 0009ffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 04 base 00100000 limit 7fffffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 05 base 100000000 limit 47d5fffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 06 base 80000000 limit 829fffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 07 base 000a0000 limit 000bffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 08 base 000c0000 limit 000fffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.0 10000100 base ff000000 limit ffffffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed) |
| [DEBUG] update_constraints: PNP: 0c31.0 00 base fed40000 limit fed44fff mem (fixed) |
| [INFO ] DOMAIN: 0000: Resource ranges: |
| [INFO ] * Base: 82a00000, Size: 6d600000, Tag: 200 |
| [INFO ] * Base: f4000000, Size: ac00000, Tag: 200 |
| [INFO ] * Base: fec01000, Size: 13f000, Tag: 200 |
| [INFO ] * Base: fed45000, Size: 2bb000, Tag: 200 |
| [INFO ] * Base: 47d600000, Size: b82a00000, Tag: 100200 |
| [DEBUG] PCI: 00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem |
| [DEBUG] PCI: 00:02.0 10 * [0x82c00000 - 0x82ffffff] limit: 82ffffff mem |
| [DEBUG] PCI: 00:1c.2 20 * [0x83000000 - 0x837fffff] limit: 837fffff mem |
| [DEBUG] PCI: 00:1c.0 20 * [0x82a00000 - 0x82afffff] limit: 82afffff mem |
| [DEBUG] PCI: 00:1c.1 20 * [0x82b00000 - 0x82bfffff] limit: 82bfffff mem |
| [DEBUG] PCI: 00:19.0 10 * [0x83800000 - 0x8381ffff] limit: 8381ffff mem |
| [DEBUG] PCI: 00:14.0 10 * [0x83820000 - 0x8382ffff] limit: 8382ffff mem |
| [DEBUG] PCI: 00:1b.0 10 * [0x83830000 - 0x83833fff] limit: 83833fff mem |
| [DEBUG] PCI: 00:19.0 14 * [0x83834000 - 0x83834fff] limit: 83834fff mem |
| [DEBUG] PCI: 00:1f.2 24 * [0x83835000 - 0x838357ff] limit: 838357ff mem |
| [DEBUG] PCI: 00:1a.0 10 * [0x83836000 - 0x838363ff] limit: 838363ff mem |
| [DEBUG] PCI: 00:1d.0 10 * [0x83837000 - 0x838373ff] limit: 838373ff mem |
| [DEBUG] PCI: 00:1f.3 10 * [0x83838000 - 0x838380ff] limit: 838380ff mem |
| [DEBUG] PCI: 00:16.0 10 * [0x83839000 - 0x8383900f] limit: 8383900f mem |
| [DEBUG] PCI: 00:1c.2 24 * [0x47d600000 - 0x48d5fffff] limit: 48d5fffff prefmem |
| [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done |
| [DEBUG] PCI: 00:1c.0 mem: base: 82a00000 size: 100000 align: 20 gran: 20 limit: 82afffff |
| [INFO ] PCI: 00:1c.0: Resource ranges: |
| [INFO ] * Base: 82a00000, Size: 100000, Tag: 200 |
| [DEBUG] PCI: 01:00.0 10 * [0x82a00000 - 0x82a000ff] limit: 82a000ff mem |
| [DEBUG] PCI: 00:1c.0 mem: base: 82a00000 size: 100000 align: 20 gran: 20 limit: 82afffff done |
| [DEBUG] PCI: 00:1c.1 mem: base: 82b00000 size: 100000 align: 20 gran: 20 limit: 82bfffff |
| [INFO ] PCI: 00:1c.1: Resource ranges: |
| [INFO ] * Base: 82b00000, Size: 100000, Tag: 200 |
| [DEBUG] PCI: 02:00.0 10 * [0x82b00000 - 0x82b0ffff] limit: 82b0ffff mem |
| [DEBUG] PCI: 00:1c.1 mem: base: 82b00000 size: 100000 align: 20 gran: 20 limit: 82bfffff done |
| [DEBUG] PCI: 00:1c.2 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff |
| [INFO ] PCI: 00:1c.2: Resource ranges: |
| [INFO ] * Base: 2000, Size: 2000, Tag: 100 |
| [DEBUG] NONE 18 * [0x2000 - 0x3fff] limit: 3fff io |
| [DEBUG] PCI: 00:1c.2 io: base: 2000 size: 2000 align: 12 gran: 12 limit: 3fff done |
| [DEBUG] PCI: 00:1c.2 prefmem: base: 47d600000 size: 10000000 align: 20 gran: 20 limit: 48d5fffff |
| [INFO ] PCI: 00:1c.2: Resource ranges: |
| [INFO ] * Base: 47d600000, Size: 10000000, Tag: 1200 |
| [DEBUG] NONE 14 * [0x47d600000 - 0x48d5fffff] limit: 48d5fffff prefmem |
| [DEBUG] PCI: 00:1c.2 prefmem: base: 47d600000 size: 10000000 align: 20 gran: 20 limit: 48d5fffff done |
| [DEBUG] PCI: 00:1c.2 mem: base: 83000000 size: 800000 align: 20 gran: 20 limit: 837fffff |
| [INFO ] PCI: 00:1c.2: Resource ranges: |
| [INFO ] * Base: 83000000, Size: 800000, Tag: 200 |
| [DEBUG] NONE 10 * [0x83000000 - 0x837fffff] limit: 837fffff mem |
| [DEBUG] PCI: 00:1c.2 mem: base: 83000000 size: 800000 align: 20 gran: 20 limit: 837fffff done |
| [INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete === |
| [DEBUG] PCI: 00:02.0 10 <- [0x0082c00000 - 0x0082ffffff] size 0x00400000 gran 0x16 mem64 |
| [DEBUG] PCI: 00:02.0 18 <- [0x0090000000 - 0x009fffffff] size 0x10000000 gran 0x1c prefmem64 |
| [DEBUG] PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io |
| [DEBUG] PCI: 00:14.0 10 <- [0x0083820000 - 0x008382ffff] size 0x00010000 gran 0x10 mem64 |
| [DEBUG] PCI: 00:16.0 10 <- [0x0083839000 - 0x008383900f] size 0x00000010 gran 0x04 mem64 |
| [DEBUG] PCI: 00:19.0 10 <- [0x0083800000 - 0x008381ffff] size 0x00020000 gran 0x11 mem |
| [DEBUG] PCI: 00:19.0 14 <- [0x0083834000 - 0x0083834fff] size 0x00001000 gran 0x0c mem |
| [DEBUG] PCI: 00:19.0 18 <- [0x0000001040 - 0x000000105f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1a.0 10 <- [0x0083836000 - 0x00838363ff] size 0x00000400 gran 0x0a mem |
| [DEBUG] PCI: 00:1b.0 10 <- [0x0083830000 - 0x0083833fff] size 0x00004000 gran 0x0e mem64 |
| [DEBUG] PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| [DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| [DEBUG] PCI: 00:1c.0 20 <- [0x0082a00000 - 0x0082afffff] size 0x00100000 gran 0x14 bus 01 mem |
| [DEBUG] PCI: 01:00.0 10 <- [0x0082a00000 - 0x0082a000ff] size 0x00000100 gran 0x08 mem |
| [DEBUG] PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io |
| [DEBUG] PCI: 00:1c.1 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| [DEBUG] PCI: 00:1c.1 20 <- [0x0082b00000 - 0x0082bfffff] size 0x00100000 gran 0x14 bus 02 mem |
| [DEBUG] PCI: 02:00.0 10 <- [0x0082b00000 - 0x0082b0ffff] size 0x00010000 gran 0x10 mem64 |
| [DEBUG] PCI: 00:1c.2 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 03 io |
| [DEBUG] PCI: 00:1c.2 24 <- [0x047d600000 - 0x048d5fffff] size 0x10000000 gran 0x14 bus 03 prefmem |
| [DEBUG] PCI: 00:1c.2 20 <- [0x0083000000 - 0x00837fffff] size 0x00800000 gran 0x14 bus 03 mem |
| [DEBUG] PCI: 00:1d.0 10 <- [0x0083837000 - 0x00838373ff] size 0x00000400 gran 0x0a mem |
| [ERROR] PNP: 00ff.1 missing set_resources |
| [ERROR] PNP: 00ff.2 missing set_resources |
| [DEBUG] PCI: 00:1f.2 10 <- [0x0000001080 - 0x0000001087] size 0x00000008 gran 0x03 io |
| [DEBUG] PCI: 00:1f.2 14 <- [0x0000001090 - 0x0000001093] size 0x00000004 gran 0x02 io |
| [DEBUG] PCI: 00:1f.2 18 <- [0x0000001088 - 0x000000108f] size 0x00000008 gran 0x03 io |
| [DEBUG] PCI: 00:1f.2 1c <- [0x0000001094 - 0x0000001097] size 0x00000004 gran 0x02 io |
| [DEBUG] PCI: 00:1f.2 20 <- [0x0000001060 - 0x000000107f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1f.2 24 <- [0x0083835000 - 0x00838357ff] size 0x00000800 gran 0x0b mem |
| [DEBUG] PCI: 00:1f.3 10 <- [0x0083838000 - 0x00838380ff] size 0x00000100 gran 0x08 mem64 |
| [INFO ] Done setting resources. |
| [INFO ] Done allocating resources. |
| [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 2 / 0 ms |
| [INFO ] Enabling resources... |
| [DEBUG] PCI: 00:00.0 subsystem <- 17aa/21f3 |
| [DEBUG] PCI: 00:00.0 cmd <- 06 |
| [DEBUG] PCI: 00:02.0 subsystem <- 17aa/21f3 |
| [DEBUG] PCI: 00:02.0 cmd <- 03 |
| [DEBUG] PCI: 00:14.0 subsystem <- 17aa/21f3 |
| [DEBUG] PCI: 00:14.0 cmd <- 102 |
| [DEBUG] PCI: 00:16.0 subsystem <- 17aa/21f3 |
| [DEBUG] PCI: 00:16.0 cmd <- 02 |
| [DEBUG] PCI: 00:19.0 subsystem <- 17aa/21f3 |
| [DEBUG] PCI: 00:19.0 cmd <- 103 |
| [DEBUG] PCI: 00:1a.0 subsystem <- 17aa/21f3 |
| [DEBUG] PCI: 00:1a.0 cmd <- 102 |
| [DEBUG] PCI: 00:1b.0 subsystem <- 17aa/21f3 |
| [DEBUG] PCI: 00:1b.0 cmd <- 102 |
| [DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1c.0 subsystem <- 17aa/21f3 |
| [DEBUG] PCI: 00:1c.0 cmd <- 106 |
| [DEBUG] PCI: 00:1c.1 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1c.1 subsystem <- 17aa/21f3 |
| [DEBUG] PCI: 00:1c.1 cmd <- 106 |
| [DEBUG] PCI: 00:1c.2 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1c.2 subsystem <- 17aa/21f3 |
| [DEBUG] PCI: 00:1c.2 cmd <- 107 |
| [DEBUG] PCI: 00:1d.0 subsystem <- 17aa/21f3 |
| [DEBUG] PCI: 00:1d.0 cmd <- 102 |
| [DEBUG] PCI: 00:1f.0 subsystem <- 17aa/21f3 |
| [DEBUG] PCI: 00:1f.0 cmd <- 107 |
| [DEBUG] PCI: 00:1f.2 subsystem <- 17aa/21f3 |
| [DEBUG] PCI: 00:1f.2 cmd <- 03 |
| [DEBUG] PCI: 00:1f.3 subsystem <- 17aa/21f3 |
| [DEBUG] PCI: 00:1f.3 cmd <- 103 |
| [DEBUG] PCI: 01:00.0 subsystem <- 17aa/21f3 |
| [DEBUG] PCI: 01:00.0 cmd <- 06 |
| [DEBUG] PCI: 02:00.0 cmd <- 02 |
| [INFO ] done. |
| [INFO ] Found TPM ST33ZP24 by ST Microelectronics |
| [DEBUG] TPM: Startup |
| [DEBUG] TPM: command 0x99 returned 0x0 |
| [DEBUG] TPM: Asserting physical presence |
| [DEBUG] TPM: command 0x4000000a returned 0x0 |
| [DEBUG] TPM: command 0x65 returned 0x0 |
| [DEBUG] TPM: flags disable=0, deactivated=0, nvlocked=1 |
| [INFO ] TPM: setup succeeded |
| [DEBUG] BS: BS_DEV_INIT entry times (exec / console): 48 / 0 ms |
| [INFO ] Initializing devices... |
| [DEBUG] CPU_CLUSTER: 0 init |
| [DEBUG] MTRR: Physical address space: |
| [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 |
| [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 |
| [DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6 |
| [DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 0 |
| [DEBUG] 0x0000000090000000 - 0x000000009fffffff size 0x10000000 type 1 |
| [DEBUG] 0x00000000a0000000 - 0x00000000ffffffff size 0x60000000 type 0 |
| [DEBUG] 0x0000000100000000 - 0x000000047d5fffff size 0x37d600000 type 6 |
| [DEBUG] 0x000000047d600000 - 0x000000048d5fffff size 0x10000000 type 0 |
| [DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000 |
| [DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| [DEBUG] CPU physical address size: 36 bits |
| [DEBUG] MTRR: default type WB/UC MTRR counts: 12/8. |
| [DEBUG] MTRR: UC selected as default type. |
| [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 |
| [DEBUG] MTRR: 1 base 0x0000000090000000 mask 0x0000000ff0000000 type 1 |
| [DEBUG] MTRR: 2 base 0x0000000100000000 mask 0x0000000f00000000 type 6 |
| [DEBUG] MTRR: 3 base 0x0000000200000000 mask 0x0000000e00000000 type 6 |
| [DEBUG] MTRR: 4 base 0x0000000400000000 mask 0x0000000f80000000 type 6 |
| [DEBUG] MTRR: 5 base 0x000000047d600000 mask 0x0000000fffe00000 type 0 |
| [DEBUG] MTRR: 6 base 0x000000047d800000 mask 0x0000000fff800000 type 0 |
| [DEBUG] MTRR: 7 base 0x000000047e000000 mask 0x0000000ffe000000 type 0 |
| |
| [DEBUG] MTRR check |
| [DEBUG] Fixed MTRRs : Enabled |
| [DEBUG] Variable MTRRs: Enabled |
| |
| [DEBUG] CPU has 4 cores, 8 threads enabled. |
| [DEBUG] Setting up SMI for CPU |
| [INFO ] Will perform SMM setup. |
| [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x13700 size 0x6800 in mcache @0x7ffdd0ac |
| [DEBUG] microcode: sig=0x306a9 pf=0x10 revision=0x21 |
| [INFO ] CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| [INFO ] LAPIC 0x0 in XAPIC mode. |
| [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 |
| [DEBUG] Processing 18 relocs. Offset value of 0x00030000 |
| [DEBUG] Attempting to start 7 APs |
| [DEBUG] Waiting for 10ms after sending INIT. |
| [DEBUG] Waiting for SIPI to complete... |
| [DEBUG] done. |
| [DEBUG] Waiting for SIPI to complete... |
| [INFO ] LAPIC 0x1 in XAPIC mode. |
| [DEBUG] done. |
| [INFO ] AP: slot 1 apic_id 1, MCU rev: 0x00000021 |
| [INFO ] LAPIC 0x5 in XAPIC mode. |
| [INFO ] AP: slot 2 apic_id 5, MCU rev: 0x00000021 |
| [INFO ] LAPIC 0x4 in XAPIC mode. |
| [INFO ] AP: slot 3 apic_id 4, MCU rev: 0x00000021 |
| [INFO ] LAPIC 0x2 in XAPIC mode. |
| [INFO ] AP: slot 5 apic_id 2, MCU rev: 0x00000021 |
| [INFO ] LAPIC 0x6 in XAPIC mode. |
| [INFO ] LAPIC 0x7 in XAPIC mode. |
| [INFO ] AP: slot 4 apic_id 6, MCU rev: 0x00000021 |
| [INFO ] AP: slot 6 apic_id 7, MCU rev: 0x00000021 |
| [INFO ] LAPIC 0x3 in XAPIC mode. |
| [INFO ] AP: slot 7 apic_id 3, MCU rev: 0x00000021 |
| [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e8 memsize: 0x1e8 |
| [DEBUG] Processing 11 relocs. Offset value of 0x00038000 |
| [DEBUG] smm_module_setup_stub: stack_top = 0x80002000 |
| [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 |
| [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c |
| [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000 |
| [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7ff8d489 |
| [DEBUG] Installing permanent SMM handler to 0x80000000 |
| [DEBUG] fx_save [0x802ff000-0x80300000[ |
| [DEBUG] smihandler [0x802fd000-0x802feff0[ |
| [DEBUG] -------------NEW CODE SEGMENT -------------- |
| [DEBUG] CPU 0x0 |
| [DEBUG] Stub [0x802f5000-0x802f51e8[ |
| [DEBUG] Save state [0x802fcc00-0x802fd000[ |
| [DEBUG] CPU 0x1 |
| [DEBUG] Stub [0x802f4c00-0x802f4de8[ |
| [DEBUG] Save state [0x802fc800-0x802fcc00[ |
| [DEBUG] CPU 0x2 |
| [DEBUG] Stub [0x802f4800-0x802f49e8[ |
| [DEBUG] Save state [0x802fc400-0x802fc800[ |
| [DEBUG] CPU 0x3 |
| [DEBUG] Stub [0x802f4400-0x802f45e8[ |
| [DEBUG] Save state [0x802fc000-0x802fc400[ |
| [DEBUG] CPU 0x4 |
| [DEBUG] Stub [0x802f4000-0x802f41e8[ |
| [DEBUG] Save state [0x802fbc00-0x802fc000[ |
| [DEBUG] CPU 0x5 |
| [DEBUG] Stub [0x802f3c00-0x802f3de8[ |
| [DEBUG] Save state [0x802fb800-0x802fbc00[ |
| [DEBUG] CPU 0x6 |
| [DEBUG] Stub [0x802f3800-0x802f39e8[ |
| [DEBUG] Save state [0x802fb400-0x802fb800[ |
| [DEBUG] CPU 0x7 |
| [DEBUG] Stub [0x802f3400-0x802f35e8[ |
| [DEBUG] Save state [0x802fb000-0x802fb400[ |
| [DEBUG] cpu stacks [0x80000000-0x80002000[ |
| [DEBUG] Loading module at 0x802fd000 with entry 0x802fd7e5. filesize: 0x1fa8 memsize: 0x1ff0 |
| [DEBUG] Processing 93 relocs. Offset value of 0x802fd000 |
| [DEBUG] Loading module at 0x802f5000 with entry 0x802f5000. filesize: 0x1e8 memsize: 0x1e8 |
| [DEBUG] Processing 11 relocs. Offset value of 0x802f5000 |
| [DEBUG] smm_module_setup_stub: stack_top = 0x80002000 |
| [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 |
| [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c |
| [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000 |
| [INFO ] smm_place_entry_code: smbase 802eb400, stack_top 80002000 |
| [DEBUG] SMM Module: placing smm entry code at 802f4c00, cpu # 0x1 |
| [DEBUG] smm_place_entry_code: copying from 802f5000 to 802f4c00 0x1e8 bytes |
| [DEBUG] SMM Module: placing smm entry code at 802f4800, cpu # 0x2 |
| [DEBUG] smm_place_entry_code: copying from 802f5000 to 802f4800 0x1e8 bytes |
| [DEBUG] SMM Module: placing smm entry code at 802f4400, cpu # 0x3 |
| [DEBUG] smm_place_entry_code: copying from 802f5000 to 802f4400 0x1e8 bytes |
| [DEBUG] SMM Module: placing smm entry code at 802f4000, cpu # 0x4 |
| [DEBUG] smm_place_entry_code: copying from 802f5000 to 802f4000 0x1e8 bytes |
| [DEBUG] SMM Module: placing smm entry code at 802f3c00, cpu # 0x5 |
| [DEBUG] smm_place_entry_code: copying from 802f5000 to 802f3c00 0x1e8 bytes |
| [DEBUG] SMM Module: placing smm entry code at 802f3800, cpu # 0x6 |
| [DEBUG] smm_place_entry_code: copying from 802f5000 to 802f3800 0x1e8 bytes |
| [DEBUG] SMM Module: placing smm entry code at 802f3400, cpu # 0x7 |
| [DEBUG] smm_place_entry_code: copying from 802f5000 to 802f3400 0x1e8 bytes |
| [DEBUG] SMM Module: stub loaded at 802f5000. Will call 0x802fd7e5 |
| [DEBUG] Initializing southbridge SMI... |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ed000, cpu = 0 |
| [DEBUG] In relocation handler: cpu 0 |
| [DEBUG] New SMBASE=0x802ed000 IEDBASE=0x80400000 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] microcode: Update skipped, already up-to-date |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ecc00, cpu = 1 |
| [DEBUG] In relocation handler: cpu 1 |
| [DEBUG] New SMBASE=0x802ecc00 IEDBASE=0x80400000 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] microcode: Update skipped, already up-to-date |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ec800, cpu = 2 |
| [DEBUG] In relocation handler: cpu 2 |
| [DEBUG] New SMBASE=0x802ec800 IEDBASE=0x80400000 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] microcode: Update skipped, already up-to-date |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ec400, cpu = 3 |
| [DEBUG] In relocation handler: cpu 3 |
| [DEBUG] New SMBASE=0x802ec400 IEDBASE=0x80400000 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] microcode: Update skipped, already up-to-date |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ec000, cpu = 4 |
| [DEBUG] In relocation handler: cpu 4 |
| [DEBUG] New SMBASE=0x802ec000 IEDBASE=0x80400000 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] microcode: Update skipped, already up-to-date |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ebc00, cpu = 5 |
| [DEBUG] In relocation handler: cpu 5 |
| [DEBUG] New SMBASE=0x802ebc00 IEDBASE=0x80400000 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] microcode: Update skipped, already up-to-date |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802eb400, cpu = 7 |
| [DEBUG] In relocation handler: cpu 7 |
| [DEBUG] New SMBASE=0x802eb400 IEDBASE=0x80400000 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] microcode: Update skipped, already up-to-date |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802eb800, cpu = 6 |
| [DEBUG] In relocation handler: cpu 6 |
| [DEBUG] New SMBASE=0x802eb800 IEDBASE=0x80400000 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] microcode: Update skipped, already up-to-date |
| [INFO ] Initializing CPU #0 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [INFO ] CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| [INFO ] CPU: platform id 4 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT NOT supported |
| [INFO ] CPU: VT supported |
| [DEBUG] VMX status: enabled |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] model_x06ax: frequency set to 2200 |
| [INFO ] Turbo is available but hidden |
| [INFO ] Turbo is available and visible |
| [INFO ] CPU #0 initialized |
| [INFO ] Initializing CPU #1 |
| [INFO ] Initializing CPU #3 |
| [INFO ] Initializing CPU #2 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [INFO ] Initializing CPU #6 |
| [INFO ] Initializing CPU #4 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [INFO ] CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| [INFO ] Initializing CPU #7 |
| [INFO ] Initializing CPU #5 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [INFO ] CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| [INFO ] CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| [INFO ] CPU: platform id 4 |
| [INFO ] CPU: platform id 4 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT NOT supported |
| [INFO ] CPU: VT supported |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT NOT supported |
| [INFO ] CPU: VT supported |
| [DEBUG] VMX status: enabled |
| [DEBUG] VMX status: enabled |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [INFO ] CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| [INFO ] CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| [INFO ] CPU: platform id 4 |
| [INFO ] CPU: platform id 4 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT NOT supported |
| [INFO ] CPU: VT supported |
| [INFO ] CPU: AES supported |
| [DEBUG] VMX status: enabled |
| [INFO ] CPU: TXT NOT supported |
| [INFO ] CPU: VT supported |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] VMX status: enabled |
| [INFO ] CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| [INFO ] CPU: platform id 4 |
| [INFO ] CPU: platform id 4 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT NOT supported |
| [INFO ] CPU: VT supported |
| [INFO ] CPU: AES supported |
| [DEBUG] VMX status: enabled |
| [INFO ] CPU: TXT NOT supported |
| [INFO ] CPU: VT supported |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] VMX status: enabled |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [INFO ] CPU: Intel(R) Core(TM) i7-3632QM CPU @ 2.20GHz. |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] cpu: energy policy set to 6 |
| [INFO ] CPU: platform id 4 |
| [DEBUG] cpu: energy policy set to 6 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [DEBUG] model_x06ax: frequency set to 2200 |
| [DEBUG] model_x06ax: frequency set to 2200 |
| [INFO ] CPU #2 initialized |
| [INFO ] CPU #3 initialized |
| [DEBUG] model_x06ax: frequency set to 2200 |
| [INFO ] CPU #5 initialized |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] model_x06ax: frequency set to 2200 |
| [INFO ] CPU #7 initialized |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT NOT supported |
| [INFO ] CPU: VT supported |
| [DEBUG] model_x06ax: frequency set to 2200 |
| [INFO ] CPU #6 initialized |
| [DEBUG] VMX status: enabled |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] model_x06ax: frequency set to 2200 |
| [INFO ] CPU #4 initialized |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] model_x06ax: frequency set to 2200 |
| [INFO ] CPU #1 initialized |
| [INFO ] bsp_do_flight_plan done after 29 msecs. |
| [DEBUG] Initializing southbridge SMI... |
| [DEBUG] SMI_STS: |
| [DEBUG] GPE0_STS: GPIO14 GPIO11 GPIO9 GPIO7 GPIO5 GPIO4 GPIO3 GPIO0 |
| [DEBUG] ALT_GP_SMI_STS: GPI14 GPI11 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI1 GPI0 |
| [DEBUG] TCO_STS: |
| [DEBUG] Locking SMM. |
| [DEBUG] CPU_CLUSTER: 0 init finished in 43 msecs |
| [DEBUG] PCI: 00:00.0 init |
| [DEBUG] Disabling PEG12. |
| [DEBUG] Disabling PEG11. |
| [DEBUG] Disabling PEG10. |
| [DEBUG] Disabling Device 4. |
| [DEBUG] Disabling PEG60. |
| [DEBUG] Disabling Device 7. |
| [DEBUG] Disabling PEG IO clock. |
| [DEBUG] Set BIOS_RESET_CPL |
| [DEBUG] CPU TDP: 35 Watts |
| [DEBUG] PCI: 00:00.0 init finished in 1 msecs |
| [DEBUG] PCI: 00:02.0 init |
| [INFO ] CBFS: Found 'vbt.bin' @0x47300 size 0x581 in mcache @0x7ffdd21c |
| [INFO ] Found a VBT of 4459 bytes after decompression |
| [INFO ] GMA: Found VBT in CBFS |
| [INFO ] GMA: Found valid VBT in CBFS |
| [DEBUG] GT Power Management Init |
| [DEBUG] IVB GT2 25W-35W Power Meter Weights |
| [DEBUG] GT Power Management Init (post VBIOS) |
| |
| [0.654966] CONFIG => |
| [0.654966] (Primary => |
| [0.654967] (Port => HDMI2 , |
| [0.654967] Framebuffer => |
| [0.654968] (Width => 1024, |
| [0.654968] Height => 768, |
| [0.654969] Start_X => 0, |
| [0.654969] Start_Y => 0, |
| [0.654970] Stride => 1024, |
| [0.654970] V_Stride => 768, |
| [0.654971] Tiling => Linear , |
| [0.654971] Rotation => No_Rotation, |
| [0.654972] Offset => 0x00000000, |
| [0.654972] BPC => 8), |
| [0.654973] Mode => |
| [0.654973] (Dotclock => 148500000, |
| [0.654974] H_Visible => 1920, |
| [0.654974] H_Sync_Begin => 2008, |
| [0.654975] H_Sync_End => 2052, |
| [0.654975] H_Total => 2200, |
| [0.654976] V_Visible => 1080, |
| [0.654976] V_Sync_Begin => 1084, |
| [0.654977] V_Sync_End => 1089, |
| [0.654977] V_Total => 1125, |
| [0.654978] H_Sync_Active_High => True, |
| [0.654978] V_Sync_Active_High => True, |
| [0.654979] BPC => 5)), |
| [0.654979] Secondary => |
| [0.654980] (Port => HDMI3 , |
| [0.654980] Framebuffer => |
| [0.654981] (Width => 1024, |
| [0.654981] Height => 768, |
| [0.654982] Start_X => 0, |
| [0.654982] Start_Y => 0, |
| [0.654983] Stride => 1024, |
| [0.654983] V_Stride => 768, |
| [0.654984] Tiling => Linear , |
| [0.654984] Rotation => No_Rotation, |
| [0.654985] Offset => 0x00000000, |
| [0.654985] BPC => 8), |
| [0.654986] Mode => |
| [0.654986] (Dotclock => 148500000, |
| [0.654987] H_Visible => 1920, |
| [0.654987] H_Sync_Begin => 2008, |
| [0.654988] H_Sync_End => 2052, |
| [0.654988] H_Total => 2200, |
| [0.654989] V_Visible => 1080, |
| [0.654989] V_Sync_Begin => 1084, |
| [0.654990] V_Sync_End => 1089, |
| [0.654990] V_Total => 1125, |
| [0.654991] H_Sync_Active_High => True, |
| [0.654991] V_Sync_Active_High => True, |
| [0.654992] BPC => 5)), |
| [0.654992] Tertiary => |
| [0.654993] (Port => LVDS , |
| [0.654993] Framebuffer => |
| [0.654994] (Width => 1024, |
| [0.654994] Height => 768, |
| [0.654995] Start_X => 0, |
| [0.654995] Start_Y => 0, |
| [0.654996] Stride => 1024, |
| [0.654996] V_Stride => 768, |
| [0.654997] Tiling => Linear , |
| [0.654997] Rotation => No_Rotation, |
| [0.654998] Offset => 0x00000000, |
| [0.654998] BPC => 8), |
| [0.654999] Mode => |
| [0.654999] (Dotclock => 98210000, |
| [0.655000] H_Visible => 1600, |
| [0.655000] H_Sync_Begin => 1648, |
| [0.655001] H_Sync_End => 1680, |
| [0.655001] H_Total => 1760, |
| [0.655002] V_Visible => 900, |
| [0.655002] V_Sync_Begin => 902, |
| [0.655003] V_Sync_End => 907, |
| [0.655003] V_Total => 930, |
| [0.655004] H_Sync_Active_High => False, |
| [0.655004] V_Sync_Active_High => False, |
| [0.655005] BPC => 5))); |
| [INFO ] framebuffer_info: bytes_per_line: 4096, bits_per_pixel: 32 |
| [INFO ] x_res x y_res: 1024 x 768, size: 3145728 at 0x90000000 |
| [DEBUG] PCI: 00:02.0 init finished in 538 msecs |
| [DEBUG] PCI: 00:14.0 init |
| [DEBUG] XHCI: Setting up controller.. done. |
| [DEBUG] PCI: 00:14.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:16.0 init |
| [DEBUG] ME: FW Partition Table : OK |
| [DEBUG] ME: Bringup Loader Failure : NO |
| [DEBUG] ME: Firmware Init Complete : NO |
| [DEBUG] ME: Manufacturing Mode : YES |
| [DEBUG] ME: Boot Options Present : NO |
| [DEBUG] ME: Update In Progress : NO |
| [DEBUG] ME: Current Working State : Initializing |
| [DEBUG] ME: Current Operation State : Bring up |
| [DEBUG] ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| [DEBUG] ME: Error Code : No Error |
| [DEBUG] ME: Progress Phase : BUP Phase |
| [DEBUG] ME: Power Management Event : Clean Moff->Mx wake |
| [DEBUG] ME: Progress Phase State : Check to see if straps say ME DISABLED |
| [CRIT ] intel_me_path: mbp is not ready! |
| [NOTE ] ME: BIOS path: Error |
| [DEBUG] ME: me_state=0, me_state_prev=0 |
| [DEBUG] PCI: 00:16.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:19.0 init |
| [DEBUG] PCI: 00:19.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1a.0 init |
| [DEBUG] EHCI: Setting up controller.. done. |
| [DEBUG] PCI: 00:1a.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1b.0 init |
| [DEBUG] Azalia: base = 0x83830000 |
| [DEBUG] Azalia: codec_mask = 09 |
| [DEBUG] azalia_audio: Initializing codec #3 |
| [DEBUG] azalia_audio: codec viddid: 80862806 |
| [DEBUG] azalia_audio: verb_size: 16 |
| [DEBUG] azalia_audio: verb loaded. |
| [DEBUG] azalia_audio: Initializing codec #0 |
| [DEBUG] azalia_audio: codec viddid: 10ec0269 |
| [DEBUG] azalia_audio: verb_size: 44 |
| [DEBUG] azalia_audio: verb loaded. |
| [DEBUG] PCI: 00:1b.0 init finished in 4 msecs |
| [DEBUG] PCI: 00:1c.0 init |
| [DEBUG] Initializing PCH PCIe bridge. |
| [DEBUG] PCI: 00:1c.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1c.1 init |
| [DEBUG] Initializing PCH PCIe bridge. |
| [DEBUG] PCI: 00:1c.1 init finished in 0 msecs |
| [DEBUG] PCI: 00:1c.2 init |
| [DEBUG] Initializing PCH PCIe bridge. |
| [DEBUG] PCI: 00:1c.2 init finished in 0 msecs |
| [DEBUG] PCI: 00:1d.0 init |
| [DEBUG] EHCI: Setting up controller.. done. |
| [DEBUG] PCI: 00:1d.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1f.0 init |
| [DEBUG] pch: lpc_init |
| [INFO ] PCH: detected QM77, device id: 0x1e55, rev id 0x4 |
| [DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000 |
| [DEBUG] IOAPIC: ID = 0x02 |
| [DEBUG] IOAPIC: 24 interrupts |
| [DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000 |
| [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| [INFO ] Set power off after power failure. |
| [INFO ] NMI sources enabled. |
| [DEBUG] PantherPoint PM init |
| [DEBUG] RTC: failed = 0x0 |
| [DEBUG] RTC Init |
| [DEBUG] apm_control: Disabling ACPI. |
| [DEBUG] APMC done. |
| [DEBUG] pch_spi_init |
| [DEBUG] PCI: 00:1f.0 init finished in 0 msecs |
| [DEBUG] PCI: 00:1f.2 init |
| [DEBUG] SATA: Initializing... |
| [DEBUG] SATA: Controller in AHCI mode. |
| [DEBUG] ABAR: 0x83835000 |
| [DEBUG] PCI: 00:1f.2 init finished in 0 msecs |
| [DEBUG] PCI: 00:1f.3 init |
| [DEBUG] PCI: 00:1f.3 init finished in 0 msecs |
| [DEBUG] PCI: 01:00.0 init |
| [DEBUG] PCI: 01:00.0 init finished in 0 msecs |
| [DEBUG] PCI: 02:00.0 init |
| [DEBUG] PCI: 02:00.0 init finished in 0 msecs |
| [DEBUG] PNP: 00ff.2 init |
| [DEBUG] PNP: 00ff.2 init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:54 init |
| [DEBUG] I2C: 01:54 init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:55 init |
| [DEBUG] I2C: 01:55 init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:56 init |
| [DEBUG] I2C: 01:56 init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:57 init |
| [DEBUG] I2C: 01:57 init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5c init |
| [DEBUG] Locking EEPROM RFID |
| [DEBUG] init EEPROM done |
| [DEBUG] I2C: 01:5c init finished in 24 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5d init |
| [DEBUG] I2C: 01:5d init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5e init |
| [DEBUG] I2C: 01:5e init finished in 0 msecs |
| [DEBUG] smbus: PCI: 00:1f.3[0]->I2C: 01:5f init |
| [DEBUG] I2C: 01:5f init finished in 0 msecs |
| [INFO ] Devices initialized |
| [DEBUG] BS: BS_DEV_INIT run times (exec / console): 612 / 1 ms |
| [INFO ] Finalize devices... |
| [DEBUG] PCI: 00:1f.0 final |
| [DEBUG] apm_control: Finalizing SMM. |
| [DEBUG] APMC done. |
| [INFO ] Devices finalized |
| [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x43a00 size 0x38d0 in mcache @0x7ffdd1f0 |
| [WARN ] CBFS: 'fallback/slic' not found. |
| [INFO ] ACPI: Writing ACPI tables at 7ff2b000. |
| [DEBUG] ACPI: * FACS |
| [DEBUG] ACPI: * DSDT |
| [DEBUG] ACPI: * FADT |
| [DEBUG] ACPI: added table 1/32, length now 40 |
| [DEBUG] ACPI: * SSDT |
| [DEBUG] Generating ACPI PIRQ entries |
| [DEBUG] Found 1 CPU(s) with 8 core(s) each. |
| [DEBUG] PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| [DEBUG] PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| [DEBUG] PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| [DEBUG] PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| [DEBUG] PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| [DEBUG] PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| [DEBUG] PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| [DEBUG] PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| [DEBUG] PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| [DEBUG] PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| [DEBUG] PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| [DEBUG] PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| [DEBUG] PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| [DEBUG] PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| [DEBUG] PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| [DEBUG] PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| [DEBUG] PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| [DEBUG] PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| [DEBUG] PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| [DEBUG] PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| [DEBUG] PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| [DEBUG] PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| [DEBUG] PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| [DEBUG] PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| [DEBUG] PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| [DEBUG] PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| [DEBUG] PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| [DEBUG] PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| [DEBUG] PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| [DEBUG] PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| [DEBUG] PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| [DEBUG] PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| [DEBUG] PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| [DEBUG] PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| [DEBUG] PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| [DEBUG] PSS: 2201MHz power 35000 control 0x2000 status 0x2000 |
| [DEBUG] PSS: 2200MHz power 35000 control 0x1600 status 0x1600 |
| [DEBUG] PSS: 2000MHz power 31083 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1800MHz power 27313 control 0x1200 status 0x1200 |
| [DEBUG] PSS: 1600MHz power 23714 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 1400MHz power 20278 control 0xe00 status 0xe00 |
| [DEBUG] PSS: 1200MHz power 16957 control 0xc00 status 0xc00 |
| [DEBUG] PCI space above 4GB MMIO is at 0x47d600001, len = 0xb829fffff |
| [INFO ] ACPI: * H8 |
| [INFO ] H8: BDC not installed |
| [INFO ] H8: WWAN not installed |
| [INFO ] \_SB_.PCI0.TPM: LPC TPM PNP: 0c31.0 |
| [DEBUG] ACPI: added table 2/32, length now 44 |
| [DEBUG] ACPI: * MCFG |
| [DEBUG] ACPI: added table 3/32, length now 48 |
| [DEBUG] ACPI: * TCPA |
| [DEBUG] TCPA log created at 0x7ff1b000 |
| [DEBUG] ACPI: added table 4/32, length now 52 |
| [DEBUG] ACPI: * MADT |
| [DEBUG] ACPI: added table 5/32, length now 56 |
| [DEBUG] current = 7ff316c0 |
| [DEBUG] ACPI: * HPET |
| [DEBUG] ACPI: added table 6/32, length now 60 |
| [INFO ] ACPI: done. |
| [DEBUG] ACPI tables: 26368 bytes. |
| [DEBUG] smbios_write_tables: 7ff13000 |
| [INFO ] Create SMBIOS type 16 |
| [INFO ] Create SMBIOS type 17 |
| [INFO ] Create SMBIOS type 20 |
| [DEBUG] SMBIOS tables: 1125 bytes. |
| [DEBUG] Writing table forward entry at 0x00000500 |
| [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 8fe9 |
| [DEBUG] Writing coreboot table at 0x7ff4f000 |
| [INFO ] CBFS: Found 'cmos_layout.bin' @0x47a00 size 0x83c in mcache @0x7ffdd274 |
| [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| [DEBUG] 1. 0000000000001000-000000000009ffff: RAM |
| [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED |
| [DEBUG] 3. 0000000000100000-000000007ff12fff: RAM |
| [DEBUG] 4. 000000007ff13000-000000007ff6bfff: CONFIGURATION TABLES |
| [DEBUG] 5. 000000007ff6c000-000000007ffccfff: RAMSTAGE |
| [DEBUG] 6. 000000007ffcd000-000000007fffffff: CONFIGURATION TABLES |
| [DEBUG] 7. 0000000080000000-00000000829fffff: RESERVED |
| [DEBUG] 8. 00000000f0000000-00000000f3ffffff: RESERVED |
| [DEBUG] 9. 00000000fed40000-00000000fed44fff: RESERVED |
| [DEBUG] 10. 0000000100000000-000000047d5fffff: RAM |
| [INFO ] Setting up bootsplash in 1024x768@32 |
| [INFO ] CBFS: Found 'bootsplash.jpg' @0x3ffc0 size 0x39f8 in mcache @0x7ffdd1c8 |
| [DEBUG] Bootsplash image resolution: 1024x768 |
| [INFO ] Bootsplash loaded |
| [DEBUG] Wrote coreboot table at: 0x7ff4f000, 0xc38 bytes, checksum 75f9 |
| [DEBUG] coreboot table: 3152 bytes. |
| [DEBUG] IMD ROOT 0. 0x7ffff000 0x00001000 |
| [DEBUG] IMD SMALL 1. 0x7fffe000 0x00001000 |
| [DEBUG] CONSOLE 2. 0x7ffde000 0x00020000 |
| [DEBUG] RO MCACHE 3. 0x7ffdd000 0x00000424 |
| [DEBUG] TIME STAMP 4. 0x7ffdc000 0x00000910 |
| [DEBUG] MRC DATA 5. 0x7ffdb000 0x00000644 |
| [DEBUG] MEM INFO 6. 0x7ffda000 0x00000768 |
| [DEBUG] AFTER CAR 7. 0x7ffcd000 0x0000d000 |
| [DEBUG] RAMSTAGE 8. 0x7ff6b000 0x00062000 |
| [DEBUG] SMM BACKUP 9. 0x7ff5b000 0x00010000 |
| [DEBUG] IGD OPREGION10. 0x7ff57000 0x0000316b |
| [DEBUG] COREBOOT 11. 0x7ff4f000 0x00008000 |
| [DEBUG] ACPI 12. 0x7ff2b000 0x00024000 |
| [DEBUG] TCPA TCGLOG13. 0x7ff1b000 0x00010000 |
| [DEBUG] SMBIOS 14. 0x7ff13000 0x00008000 |
| [DEBUG] IMD small region: |
| [DEBUG] IMD ROOT 0. 0x7fffec00 0x00000400 |
| [DEBUG] FMAP 1. 0x7fffeb20 0x000000e0 |
| [DEBUG] ROMSTAGE 2. 0x7fffeb00 0x00000004 |
| [DEBUG] ROMSTG STCK 3. 0x7fffea40 0x000000a8 |
| [DEBUG] ACPI GNVS 4. 0x7fffe940 0x00000100 |
| [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 45 / 0 ms |
| [INFO ] CBFS: Found 'fallback/payload' @0x64340 size 0x11877 in mcache @0x7ffdd330 |
| [DEBUG] Checking segment from ROM address 0xffc7456c |
| [DEBUG] Payload being loaded at below 1MiB without region being marked as RAM usable. |
| [DEBUG] Checking segment from ROM address 0xffc74588 |
| [DEBUG] Loading segment from ROM address 0xffc7456c |
| [DEBUG] code (compression=1) |
| [DEBUG] New segment dstaddr 0x000dede0 memsize 0x21220 srcaddr 0xffc745a4 filesize 0x1183f |
| [DEBUG] Loading Segment: addr: 0x000dede0 memsz: 0x0000000000021220 filesz: 0x000000000001183f |
| [DEBUG] using LZMA |
| [DEBUG] Loading segment from ROM address 0xffc74588 |
| [DEBUG] Entry Point 0x000fd25b |
| [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 34 / 0 ms |
| [DEBUG] ICH-NM10-PCH: watchdog disabled |
| [DEBUG] Jumping to boot code at 0x000fd25b(0x7ff4f000) |
| SeaBIOS (version rel-1.16.0-0-gd239552) |
| BUILD: gcc: (coreboot toolchain v2021-09-23_b0d87f753c) 11.2.0 binutils: (GNU Binutils) 2.37 |
| Found coreboot cbmem console @ 7ffde000 |
| Found mainboard LENOVO ThinkPad T430 |
| Relocating init from 0x000e0540 to 0x7fec5ac0 (size 54432) |
| Found CBFS header at 0xffc1022c |
| multiboot: eax=7ffa88e8, ebx=7ffa8864 |
| Found 16 PCI devices (max PCI bus is 03) |
| Copying SMBIOS from 0x7ff13000 to 0x000f67c0 |
| Copying SMBIOS 3.0 from 0x7ff13020 to 0x000f67a0 |
| Copying ACPI RSDP from 0x7ff2b000 to 0x000f6770 |
| table(50434146)=0x7ff2eb70 (via xsdt) |
| Using pmtimer, ioport 0x508 |
| table(41504354)=0x7ff315f0 (via xsdt) |
| Scan for VGA option rom |
| Running option rom at c000:0003 |
| pmm call arg1=0 |
| Turning on vga text mode console |
| SeaBIOS (version rel-1.16.0-0-gd239552) |
| Machine UUID 80890e81-529d-11cb-8756-8537233cd54b |
| PCI: XHCI at 00:14.0 (mmio 0x83820000) |
| XHCI init: regs @ 0x83820000, 8 ports, 32 slots, 32 byte contexts |
| XHCI protocol USB 2.00, 4 ports (offset 1), def 3001 |
| XHCI protocol USB 3.00, 4 ports (offset 5), def 1000 |
| XHCI extcap 0xc1 @ 0x83828040 |
| XHCI extcap 0xc0 @ 0x83828070 |
| XHCI extcap 0x1 @ 0x83828330 |
| EHCI init on dev 00:1a.0 (regs=0x83836020) |
| EHCI init on dev 00:1d.0 (regs=0x83837020) |
| AHCI controller at 00:1f.2, iobase 0x83835000, irq 11 |
| Searching bootorder for: /pci@i0cf8/pci-bridge@1c/*@0 |
| Searching bootorder for: HALT |
| Found 0 lpt ports |
| Found 0 serial ports |
| Searching bootorder for: /rom@img/nvramcui |
| Searching bootorder for: /rom@img/coreinfo |
| Searching bootorder for: /pci@i0cf8/*@1f,2/drive@2/disk@0 |
| AHCI/2: Set transfer mode to UDMA-6 |
| Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@2/disk@0 |
| AHCI/2: registering: "AHCI/2: Dogfish SSD 1TB ATA-10 Hard-Disk (931 GiBytes)" |
| Discarding ps2 data aa (status=11) |
| Discarding ps2 data e0 (status=11) |
| Discarding ps2 data 0f (status=11) |
| Discarding ps2 data e0 (status=11) |
| Discarding ps2 data f0 (status=11) |
| Discarding ps2 data 0f (status=11) |
| XHCI no devices found |
| USB keyboard wMaxPacketSize=63; aborting |
| Initialized USB HUB (0 ports used) |
| Initialized USB HUB (0 ports used) |
| Initialized USB HUB (0 ports used) |
| WARNING - Timeout at ps2_recvbyte:182! |
| PS2 keyboard initialized |
| WARNING - Timeout at ehci_wait_td:517! |
| ehci pipe=0x7fec1300 cur=7feb8dc0 tok=80080d80 next=7feb8e00 td=0x7feb8dc0 status=80080d80 |
| Initialized USB HUB (0 ports used) |
| All threads complete. |
| Scan for option roms |
| |
| Press ESC for boot menu. |
| |
| Turning on vga text mode console |
| SeaBIOS (version rel-1.16.0-0-gd239552) |
| Machine UUID 80890e81-529d-11cb-8756-8537233cd54b |
| Searching bootorder for: HALT |
| drive 0x000f6700: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1953525168 |
| Space available for UMB: c7000-ec000, f5fe0-f6700 |
| Returned 188416 bytes of ZoneHigh |
| e820 map has 8 items: |
| 0: 0000000000000000 - 000000000009fc00 = 1 RAM |
| 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED |
| 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED |
| 3: 0000000000100000 - 000000007ff01000 = 1 RAM |
| 4: 000000007ff01000 - 0000000082a00000 = 2 RESERVED |
| 5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED |
| 6: 00000000fed40000 - 00000000fed45000 = 2 RESERVED |
| 7: 0000000100000000 - 000000047d600000 = 1 RAM |
| enter handle_19: |
| NULL |
| Booting from Hard Disk... |
| Booting from 0000:7c00 |