blob: bcd1fe3d89c05a53e212898fe341bfae2653dd9a [file] [log] [blame]
coreboot-4.11-116-gc32f631731-MrChromebox-4.11.1 Sun Dec 1 16:34:02 UTC 2019 bootblock starting (log level: 7)...
FMAP: Found "FLASH" version 1.1 at 0x600000.
FMAP: base = 0xff800000 size = 0x800000 #areas = 5
FMAP: area COREBOOT found @ 600200 (2096640 bytes)
CBFS: 'COREBOOT Locator' located CBFS at [600200:800000)
CBFS: Locating 'fallback/romstage'
CBFS: Found @ offset 80 size 75a4
Accumulated console time in bootblock 1 ms
coreboot-4.11-116-gc32f631731-MrChromebox-4.11.1 Sun Dec 1 16:34:02 UTC 2019 romstage starting (log level: 7)...
Disabling Watchdog reboot... done.
SMBus controller enabled.
SB: Resume from S3 detected.
Setting up static northbridge registers... done.
Initializing IGD...
Back from haswell_early_initialization()
Resume from S3 detected.
CPU id(40651) ucode:00000025 Intel(R) Celeron(R) 2955U @ 1.40GHz
AES NOT supported, TXT NOT supported, VT supported
PCH type: LP Mainstream, device id: 9c45, rev id 4
SPD index 0
FMAP: area COREBOOT found @ 600200 (2096640 bytes)
CBFS: 'COREBOOT Locator' located CBFS at [600200:800000)
CBFS: Locating 'spd.bin'
CBFS: Found @ offset fc0c0 size 800
Starting UEFI PEI System Agent
FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
prepare_mrc_cache: at ffdb7fb0, size fd4
FMAP: area COREBOOT found @ 600200 (2096640 bytes)
CBFS: Locating 'mrc.bin'
CBFS: Found @ offset 19fdc0 size 2e6e4
System Agent: Starting up...
System Agent: S3 resume detected
System Agent: Initializing PCH
install_ppi: overwrite GUID {ed097352-9041-445a-80b6-b29d509e8845}
install_ppi: overwrite GUID {908c7f8b-5c48-47fb-8357-f5fd4e235276}
System Agent: Initializing PCH (SMBUS)
System Agent: Initializing PCH (USB)
System Agent: Initializing PCH (SA Init)
System Agent: Initializing PCH (Me UMA)
System Agent: Initializing Memory
Copy SPD for Channel 0 Dimm 0
Copy SPD for Channel 1 Dimm 0
System Agent: Done.
Sanity checking heap.
System Agent Version 1.6.1 Build 2
memcfg DDR3 clock 1600 MHz
memcfg channel assignment: A: 0, B 1, C 2
memcfg channel[0] config (00780008):
ECC inactive
enhanced interleave mode on
rank interleave on
DIMMA 2048 MB width x16 single rank, selected
DIMMB 0 MB width x16 single rank
memcfg channel[1] config (00780008):
ECC inactive
enhanced interleave mode on
rank interleave on
DIMMA 2048 MB width x16 single rank, selected
DIMMB 0 MB width x16 single rank
ME: FW Partition Table : OK
ME: Bringup Loader Failure : NO
ME: Firmware Init Complete : NO
ME: Manufacturing Mode : NO
ME: Boot Options Present : NO
ME: Update In Progress : NO
ME: Current Working State : Normal
ME: Current Operation State : Bring up
ME: Current Operation Mode : Normal
ME: Error Code : No Error
ME: Progress Phase : BUP Phase
ME: Power Management Event : Clean Moff->Mx wake
ME: Progress Phase State : 0x2e
SMM Memory Map
SMRAM : 0x7f800000 0x800000
Subregion 0: 0x7f800000 0x300000
Subregion 1: 0x7fb00000 0x100000
Subregion 2: 0x7fc00000 0x400000
MTRR Range: Start=7f000000 End=80000000 (Size 1000000)
MTRR Range: Start=ff800000 End=0 (Size 800000)
Accumulated console time in romstage 2 ms
coreboot-4.11-116-gc32f631731-MrChromebox-4.11.1 Sun Dec 1 16:34:02 UTC 2019 postcar starting (log level: 7)...
Jumping to image.
coreboot-4.11-116-gc32f631731-MrChromebox-4.11.1 Sun Dec 1 16:34:02 UTC 2019 ramstage starting (log level: 7)...
S3 Resume.
BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
Enumerating buses...
CPU_CLUSTER: 0 enabled
DOMAIN: 0000 enabled
PCI: pci_scan_bus for bus 00
PCI: 00:00.0 [8086/0a04] enabled
PCI: 00:02.0 [8086/0a06] enabled
PCI: 00:03.0 [8086/0a0c] enabled
PCI: 00:04.0 [8086/0a03] enabled
PCI: 00:13.0: Disabling device
PCI: 00:13.0 [8086/9c36] disabled No operations
PCI: 00:14.0 [8086/9c31] enabled
PCI: 00:15.0 [8086/9c60] enabled
PCI: 00:15.1 [8086/9c61] enabled
PCI: 00:15.2 [8086/9c62] enabled
PCI: 00:15.3: Disabling device
IOBP: set 0xce00aac7 to 0x00000100
PCI: 00:15.4: Disabling device
IOBP: set 0xce00ab07 to 0x00000100
PCI: 00:15.5: Disabling device
IOBP: set 0xce00ab47 to 0x00000100
PCI: 00:15.6: Disabling device
IOBP: set 0xce00ab87 to 0x00000100
PCI: 00:16.0 [8086/9c3a] enabled
PCI: 00:16.1: Disabling device
PCI: 00:16.1 [8086/9c3b] disabled No operations
PCI: 00:16.2: Disabling device
PCI: 00:16.3: Disabling device
PCI: 00:17.0: Disabling device
IOBP: set 0xce00ae07 to 0x00000100
PCI: 00:19.0: Disabling device
PCI: 00:1b.0 [8086/9c20] enabled
PCIe Root Port 1 ASPM is enabled
IOBP: set 0xe9002440 to 0x05050e00
PCI: 00:1c.0 [8086/9c10] enabled
PCI: 00:1c.1 [8086/9c12] disabled
PCI: 00:1c.2 [8086/9c14] disabled
PCI: 00:1c.3 [8086/9c16] disabled
PCI: 00:1c.4 [8086/9c18] disabled
PCI: 00:1c.1: Disabling device
PCI: 00:1c.2: Disabling device
PCI: 00:1c.3: Disabling device
PCI: 00:1c.4: Disabling device
PCI: 00:1c.5: Disabling device
PCI: 00:1c.5 [8086/9c1a] disabled
PCI: Static device PCI: 00:1d.0 not found, disabling it.
PCI: 00:1e.0: Disabling device
PCI: 00:1f.0 [8086/9c45] enabled
PCI: 00:1f.2 [8086/9c03] enabled
PCI: 00:1f.3 [8086/9c22] enabled
PCI: 00:1f.6 [8086/9c24] enabled
PCI: Leftover static devices:
PCI: 00:15.3
PCI: 00:15.4
PCI: 00:15.5
PCI: 00:15.6
PCI: 00:16.2
PCI: 00:16.3
PCI: 00:17.0
PCI: 00:19.0
PCI: 00:1d.0
PCI: 00:1e.0
PCI: Check your devicetree.cb.
PCI: pci_scan_bus for bus 01
PCI: 01:00.0 [168c/0034] enabled
Enabling Common Clock Configuration
ASPM: Enabled L0s and L1
Failed to enable LTR for dev = PCI: 01:00.0
scan_bus: scanning of bus PCI: 00:1c.0 took 178 usecs
PNP: 0c31.0 enabled
PNP: 00ff.1 enabled
PNP: 00ff.0 enabled
scan_bus: scanning of bus PCI: 00:1f.0 took 9 usecs
scan_bus: scanning of bus PCI: 00:1f.3 took 2 usecs
scan_bus: scanning of bus DOMAIN: 0000 took 937 usecs
scan_bus: scanning of bus Root Device took 944 usecs
done
FMAP: area RW_MRC_CACHE found @ 5b0000 (65536 bytes)
MRC: Checking cached data update for 'RW_MRC_CACHE'.
Manufacturer: ef
SF: Detected W25Q64_V with sector size 0x1000, total 0x800000
BS: BS_DEV_ENUMERATE times (ms): entry 0 run 1 exit 2
found VGA at PCI: 00:02.0
Setting up VGA for PCI: 00:02.0
Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
Allocating resources...
Reading resources...
mc_add_fixed_mmio_resources: Adding PCIEXBAR @ 60 0xf0000000-0xf3ffffff.
mc_add_fixed_mmio_resources: Adding MCHBAR @ 48 0xfed10000-0xfed17fff.
mc_add_fixed_mmio_resources: Adding DMIBAR @ 68 0xfed18000-0xfed18fff.
mc_add_fixed_mmio_resources: Adding EPBAR @ 40 0xfed19000-0xfed19fff.
mc_add_fixed_mmio_resources: Adding GDXCBAR @ 5420 0xfed84000-0xfed84fff.
MC MAP: TOM: 0x100000000
MC MAP: TOUUD: 0x178e00000
MC MAP: MESEG_BASE: 0xff000000
MC MAP: MESEG_LIMIT: 0x7fff0fffff
MC MAP: REMAP_BASE: 0x100000000
MC MAP: REMAP_LIMIT: 0x178dfffff
MC MAP: TOLUD: 0x86200000
MC MAP: BGSM: 0x80000000
MC MAP: BDSM: 0x80200000
MC MAP: TESGMB: 0x7f800000
MC MAP: GGC: 0x219
PNP: 00ff.1 missing read_resources
Done reading resources.
Setting resources...
PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64
PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64
PCI: 00:02.0 20 <- [0x0000001800 - 0x000000183f] size 0x00000040 gran 0x06 io
PCI: 00:03.0 10 <- [0x00e0518000 - 0x00e051bfff] size 0x00004000 gran 0x0e mem64
PCI: 00:04.0 10 <- [0x00e0510000 - 0x00e0517fff] size 0x00008000 gran 0x0f mem64
PCI: 00:14.0 10 <- [0x00e0500000 - 0x00e050ffff] size 0x00010000 gran 0x10 mem64
PCI: 00:15.0 10 <- [0x00e0520000 - 0x00e0520fff] size 0x00001000 gran 0x0c mem
PCI: 00:15.0 14 <- [0x00e0521000 - 0x00e0521fff] size 0x00001000 gran 0x0c mem
PCI: 00:15.1 10 <- [0x00e0522000 - 0x00e0522fff] size 0x00001000 gran 0x0c mem
PCI: 00:15.1 14 <- [0x00e0523000 - 0x00e0523fff] size 0x00001000 gran 0x0c mem
PCI: 00:15.2 10 <- [0x00e0524000 - 0x00e0524fff] size 0x00001000 gran 0x0c mem
PCI: 00:15.2 14 <- [0x00e0525000 - 0x00e0525fff] size 0x00001000 gran 0x0c mem
PCI: 00:16.0 10 <- [0x00e0529000 - 0x00e052901f] size 0x00000020 gran 0x05 mem64
PCI: 00:1b.0 10 <- [0x00e051c000 - 0x00e051ffff] size 0x00004000 gran 0x0e mem64
PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem
PCI: 00:1c.0 20 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus 01 mem
PCI: 01:00.0 10 <- [0x00e0400000 - 0x00e047ffff] size 0x00080000 gran 0x13 mem64
PCI: 01:00.0 30 <- [0x00e0480000 - 0x00e048ffff] size 0x00010000 gran 0x10 romem
PCI: 00:1f.2 10 <- [0x0000001860 - 0x0000001867] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 14 <- [0x0000001870 - 0x0000001873] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 18 <- [0x0000001868 - 0x000000186f] size 0x00000008 gran 0x03 io
PCI: 00:1f.2 1c <- [0x0000001874 - 0x0000001877] size 0x00000004 gran 0x02 io
PCI: 00:1f.2 20 <- [0x0000001840 - 0x000000185f] size 0x00000020 gran 0x05 io
PCI: 00:1f.2 24 <- [0x00e0527000 - 0x00e05277ff] size 0x00000800 gran 0x0b mem
PCI: 00:1f.3 10 <- [0x00e0528000 - 0x00e05280ff] size 0x00000100 gran 0x08 mem64
PCI: 00:1f.6 10 <- [0x00e0526000 - 0x00e0526fff] size 0x00001000 gran 0x0c mem64
Done setting resources.
Done allocating resources.
BS: BS_DEV_RESOURCES times (ms): entry 0 run 1 exit 0
Enabling resources...
PCI: 00:00.0 subsystem <- 8086/0a04
PCI: 00:00.0 cmd <- 06
PCI: 00:02.0 subsystem <- 8086/0a06
PCI: 00:02.0 cmd <- 03
PCI: 00:03.0 subsystem <- 8086/0a0c
PCI: 00:03.0 cmd <- 02
PCI: 00:04.0 cmd <- 02
PCI: 00:14.0 subsystem <- 8086/9c31
PCI: 00:14.0 cmd <- 102
PCI: 00:15.0 subsystem <- 8086/9c60
PCI: 00:15.0 cmd <- 106
PCI: 00:15.1 subsystem <- 8086/9c61
PCI: 00:15.1 cmd <- 102
PCI: 00:15.2 subsystem <- 8086/9c62
PCI: 00:15.2 cmd <- 102
PCI: 00:16.0 subsystem <- 8086/9c3a
PCI: 00:16.0 cmd <- 02
PCI: 00:1b.0 subsystem <- 8086/9c20
PCI: 00:1b.0 cmd <- 102
PCI: 00:1c.0 bridge ctrl <- 0013
PCI: 00:1c.0 subsystem <- 8086/9c10
PCI: 00:1c.0 cmd <- 06
PCI: 00:1f.0 subsystem <- 8086/9c45
PCI: 00:1f.0 cmd <- 107
PCI: 00:1f.2 subsystem <- 8086/9c03
PCI: 00:1f.2 cmd <- 103
PCI: 00:1f.3 subsystem <- 8086/9c22
PCI: 00:1f.3 cmd <- 103
PCI: 00:1f.6 subsystem <- 8086/9c24
PCI: 00:1f.6 cmd <- 102
PCI: 01:00.0 cmd <- 02
done.
BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
Found TPM SLB9635 TT 1.2 by Infineon
TPM: Handle S3 resume.
TPM: Resume
TPM: command 0x99 returned 0x0
TPM: setup succeeded
Initializing devices...
Root Device init ...
mainboard_ec_init
Chrome EC: Set SMI mask to 0x0000000000000000
EC returned error result code 1
Chrome EC: UHEPI not supported
Chrome EC: Set SCI mask to 0x00000000000009fb
Chrome EC: Set WAKE mask to 0x0000000000000000
Root Device init finished in 3999 usecs
CPU_CLUSTER: 0 init ...
MTRR: Physical address space:
0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
0x00000000000c0000 - 0x0000000080000000 size 0x7ff40000 type 6
0x0000000080000000 - 0x00000000d0000000 size 0x50000000 type 0
0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
0x0000000100000000 - 0x0000000178e00000 size 0x78e00000 type 6
MTRR: Fixed MSR 0x250 0x0606060606060606
MTRR: Fixed MSR 0x258 0x0606060606060606
MTRR: Fixed MSR 0x259 0x0000000000000000
MTRR: Fixed MSR 0x268 0x0606060606060606
MTRR: Fixed MSR 0x269 0x0606060606060606
MTRR: Fixed MSR 0x26a 0x0606060606060606
MTRR: Fixed MSR 0x26b 0x0606060606060606
MTRR: Fixed MSR 0x26c 0x0606060606060606
MTRR: Fixed MSR 0x26d 0x0606060606060606
MTRR: Fixed MSR 0x26e 0x0606060606060606
MTRR: Fixed MSR 0x26f 0x0606060606060606
CPU physical address size: 39 bits
MTRR: default type WB/UC MTRR counts: 4/3.
MTRR: UC selected as default type.
MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
MTRR: 1 base 0x00000000d0000000 mask 0x0000007ff0000000 type 1
MTRR: 2 base 0x0000000100000000 mask 0x0000007f80000000 type 6
MTRR check
Fixed MTRRs : Enabled
Variable MTRRs: Enabled
Initializing VR config.
PCODE: 24MHz BLCK calibration response: 0
PCODE: 24MHz BLCK calibration value: 0x85000000
PCH Power: PCODE Levels 0x3f1c50c2 0x004cd2c9
CPU has 2 cores, 2 threads enabled.
Setting up SMI for CPU
Will perform SMM setup.
FMAP: area COREBOOT found @ 600200 (2096640 bytes)
CBFS: 'COREBOOT Locator' located CBFS at [600200:800000)
CBFS: Locating 'cpu_microcode_blob.bin'
CBFS: Found @ offset 76c0 size 5400
microcode: sig=0x40651 pf=0x40 revision=0x25
CPU: Intel(R) Celeron(R) 2955U @ 1.40GHz.
Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170
Processing 16 relocs. Offset value of 0x00030000
Attempting to start 1 APs
Waiting for 10ms after sending INIT.
Waiting for 1st SIPI to complete...done.
Waiting for 2nd SIPI to complete...done.
AP: slot 1 apic_id 2.
Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
Processing 13 relocs. Offset value of 0x00038000
SMM Module: stub loaded at 00038000. Will call 7f7a0069(00000000)
Installing SMM handler to 0x7f800000
Loading module at 7f810000 with entry 7f8109aa. filesize: 0x5e50 memsize: 0x9f38
Processing 440 relocs. Offset value of 0x7f810000
Loading module at 7f808000 with entry 7f808000. filesize: 0x1a8 memsize: 0x1a8
Processing 13 relocs. Offset value of 0x7f808000
SMM Module: placing jmp sequence at 7f807c00 rel16 0x03fd
SMM Module: stub loaded at 7f808000. Will call 7f8109aa(00000000)
Initializing Southbridge SMI...
SMI_STS: PM1
WAK PCIEXPWAK New SMBASE 0x7f800000
In relocation handler: cpu 0
New SMBASE=0x7f800000 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
New SMBASE 0x7f7ffc00
In relocation handler: cpu 1
New SMBASE=0x7f7ffc00 IEDBASE=0x7fc00000
Writing SMRR. base = 0x7f800006, mask=0xff800800
Relocation complete.
microcode: Update skipped, already up-to-date
Initializing CPU #0
CPU: vendor Intel device 40651
CPU: family 06, model 45, stepping 01
Setting up local APIC...
apic_id: 0x00 done.
VMX status: enabled
IA32_FEATURE_CONTROL status: locked
haswell: energy policy set to 6
haswell: frequency set to 1400
Turbo is unavailable
CPU #0 initialized
Initializing CPU #1
CPU: vendor Intel device 40651
CPU: family 06, model 45, stepping 01
Setting up local APIC...
apic_id: 0x02 done.
VMX status: enabled
IA32_FEATURE_CONTROL status: locked
haswell: energy policy set to 6
haswell: frequency set to 1400
CPU #1 initialized
bsp_do_flight_plan done after 1 msecs.
Enabling SMIs.
Locking SMM.
CPU_CLUSTER: 0 init finished in 14194 usecs
PCI: 00:00.0 init ...
Disabling PEG12.
Disabling PEG11.
Disabling PEG10.
Disabling "device 7".
Set BIOS_RESET_CPL
CPU TDP: 15 Watts
PCI: 00:00.0 init finished in 1012 usecs
PCI: 00:02.0 init ...
GT Power Management Init
GT Power Management Init (post VBIOS)
PCI: 00:02.0 init finished in 132 usecs
PCI: 00:03.0 init ...
Mini-HD: base = e0518000
HDA: Initializing codec #0
HDA: codec viddid: 80862807
HDA: verb loaded.
PCI: 00:03.0 init finished in 1355 usecs
PCI: 00:04.0 init ...
PCI: 00:04.0 init finished in 0 usecs
PCI: 00:14.0 init ...
IOBP: set 0xe5004001 to 0x000000ce
PCI: 00:14.0 init finished in 1049 usecs
PCI: 00:15.0 init ...
Initializing Serial IO device
IOBP: set 0xcb000154 to 0x0000131f
IOBP: set 0xcb000180 to 0x0000003f
IOBP: set 0xcb000240 to 0x0034000a
PCI: 00:15.0 init finished in 89 usecs
PCI: 00:15.1 init ...
Initializing Serial IO device
IOBP: set 0xcb000248 to 0x0034000e
PCI: 00:15.1 init finished in 35 usecs
PCI: 00:15.2 init ...
Initializing Serial IO device
IOBP: set 0xcb000250 to 0x0034000e
PCI: 00:15.2 init finished in 35 usecs
PCI: 00:16.0 init ...
ME: FW Partition Table : OK
ME: Bringup Loader Failure : NO
ME: Firmware Init Complete : NO
ME: Manufacturing Mode : NO
ME: Boot Options Present : NO
ME: Update In Progress : NO
ME: Current Working State : Normal
ME: Current Operation State : M0 with UMA
ME: Current Operation Mode : Normal
ME: Error Code : No Error
ME: Progress Phase : Policy Module
ME: Power Management Event : Clean Moff->Mx wake
ME: Progress Phase State : Entery into Policy Module
intel_me_path: mbp is not ready!
ME: BIOS path: Error
ME: MBP not ready
PCI: 00:16.0 init finished in 15 usecs
PCI: 00:1b.0 init ...
Azalia: base = e051c000
Azalia: codec_mask = 01
HDA: Initializing codec #0
HDA: codec viddid: 10ec0283
HDA: verb loaded.
PCI: 00:1b.0 init finished in 3636 usecs
PCI: 00:1c.0 init ...
Initializing PCH PCIe bridge.
PCI: 00:1c.0 init finished in 7 usecs
PCI: 00:1f.0 init ...
pch: lpc_init
IOAPIC: Initializing IOAPIC at 0xfec00000
IOAPIC: Bootstrap Processor Local APIC = 0x00
IOAPIC: ID = 0x02
Set power off after power failure.
NMI sources disabled.
LynxPoint LP PM init
IOBP: set 0xed00015c to 0x1bc33700
IOBP: set 0xed000118 to 0x00c00000
IOBP: set 0xed000120 to 0x00245560
IOBP: set 0xca000000 to 0x00000009
IOBP: set 0xcf000000 to 0x00007007
IOBP: set 0xce00c000 to 0x00000000
RTC: failed = 0x0
PCI: 00:1f.0 init finished in 1268 usecs
PCI: 00:1f.2 init ...
SATA: Initializing...
SATA: Controller in AHCI mode.
ABAR: e0527000
PCI: 00:1f.2 init finished in 24 usecs
PCI: 00:1f.3 init ...
PCI: 00:1f.3 init finished in 5 usecs
PCI: 00:1f.6 init ...
PCI: 00:1f.6 init finished in 0 usecs
PCI: 01:00.0 init ...
PCI: 01:00.0 init finished in 0 usecs
PNP: 00ff.0 init ...
Google Chrome EC: Initializing
Google Chrome EC: version:
ro: falco_v1.5.112-8fedda8
rw: falco_v1.5.142-9c22831
running image: 2
Google Chrome EC: version:
ro: falco_v1.5.112-8fedda8
rw: falco_v1.5.142-9c22831
running image: 2
EC returned error result code 1
PNP: 00ff.0 init finished in 4677 usecs
Devices initialized
BS: BS_DEV_INIT times (ms): entry 8 run 31 exit 0
Finalize devices...
PCI: 00:1f.0 final
Devices finalized
BS: BS_POST_DEVICE times (ms): entry 0 run 1159 exit 0
Trying to find the wakeup vector...
Looking on 000f0000 for valid checksum
Checksum 1 passed
Checksum 2 passed all OK
RSDP found at 000f0000
RSDT found at 7f74a030 ends at 7f74a070
FADT found at 7f74e560
FACS found at 7f74a240
OS waking vector is 0009a1d0
BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
Restore GNVS pointer to 7f786000