| *** Pre-CBMEM romstage console overflowed, log truncated! *** |
| gent_early_init() |
| [INFO ] POST: 0x38 |
| [INFO ] POST: 0x39 |
| [INFO ] POST: 0x3a |
| [INFO ] Intel ME early init |
| [INFO ] Intel ME firmware is ready |
| [DEBUG] ME: Requested 0MB UMA |
| [DEBUG] Starting native Platform init |
| [DEBUG] DMI: Running at X4 @ 5000MT/s |
| [DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes) |
| [DEBUG] Trying stored timings. |
| [DEBUG] Starting Ivy Bridge RAM training (fast boot). |
| [DEBUG] 100MHz reference clock support: yes |
| [DEBUG] PLL_REF100_CFG value: 0x2 |
| [DEBUG] Trying CAS 11, tCK 320. |
| [DEBUG] Trying CAS 10, tCK 365. |
| [DEBUG] Trying CAS 9, tCK 384. |
| [DEBUG] Found compatible clock, CAS pair. |
| [DEBUG] Selected DRAM frequency: 666 MHz |
| [DEBUG] Selected CAS latency : 9T |
| [DEBUG] MPLL busy... done in 10 us |
| [DEBUG] MPLL frequency is set at : 666 MHz |
| [DEBUG] Done dimm mapping |
| [DEBUG] Update PCI-E configuration space: |
| [DEBUG] PCI(0, 0, 0)[a0] = 0 |
| [DEBUG] PCI(0, 0, 0)[a4] = 1 |
| [DEBUG] PCI(0, 0, 0)[bc] = 82a00000 |
| [DEBUG] PCI(0, 0, 0)[a8] = 7d600000 |
| [DEBUG] PCI(0, 0, 0)[ac] = 1 |
| [DEBUG] PCI(0, 0, 0)[b8] = 80000000 |
| [DEBUG] PCI(0, 0, 0)[b0] = 80a00000 |
| [DEBUG] PCI(0, 0, 0)[b4] = 80800000 |
| [DEBUG] Done memory map |
| [DEBUG] Done io registers |
| [DEBUG] t123: 1912, 6000, 7620 |
| [NOTE ] ME: Wrong mode : 2 |
| [NOTE ] ME: FWS2: 0x100a0140 |
| [NOTE ] ME: Bist in progress: 0x0 |
| [NOTE ] ME: ICC Status : 0x0 |
| [NOTE ] ME: Invoke MEBx : 0x0 |
| [NOTE ] ME: CPU replaced : 0x0 |
| [NOTE ] ME: MBP ready : 0x0 |
| [NOTE ] ME: MFS failure : 0x1 |
| [NOTE ] ME: Warm reset req : 0x0 |
| [NOTE ] ME: CPU repl valid : 0x1 |
| [NOTE ] ME: (Reserved) : 0x0 |
| [NOTE ] ME: FW update req : 0x0 |
| [NOTE ] ME: (Reserved) : 0x0 |
| [NOTE ] ME: Current state : 0xa |
| [NOTE ] ME: Current PM event: 0x0 |
| [NOTE ] ME: Progress code : 0x1 |
| [NOTE ] PASSED! Tell ME that DRAM is ready |
| [NOTE ] ME: ME is reporting as disabled, so not waiting for a response. |
| [NOTE ] ME: FWS2: 0x100a0140 |
| [NOTE ] ME: Bist in progress: 0x0 |
| [NOTE ] ME: ICC Status : 0x0 |
| [NOTE ] ME: Invoke MEBx : 0x0 |
| [NOTE ] ME: CPU replaced : 0x0 |
| [NOTE ] ME: MBP ready : 0x0 |
| [NOTE ] ME: MFS failure : 0x1 |
| [NOTE ] ME: Warm reset req : 0x0 |
| [NOTE ] ME: CPU repl valid : 0x1 |
| [NOTE ] ME: (Reserved) : 0x0 |
| [NOTE ] ME: FW update req : 0x0 |
| [NOTE ] ME: (Reserved) : 0x0 |
| [NOTE ] ME: Current state : 0xa |
| [NOTE ] ME: Current PM event: 0x0 |
| [NOTE ] ME: Progress code : 0x1 |
| [NOTE ] ME: Requested BIOS Action: No DID Ack received |
| [DEBUG] ME: FW Partition Table : OK |
| [DEBUG] ME: Bringup Loader Failure : NO |
| [DEBUG] ME: Firmware Init Complete : NO |
| [DEBUG] ME: Manufacturing Mode : YES |
| [DEBUG] ME: Boot Options Present : NO |
| [DEBUG] ME: Update In Progress : NO |
| [DEBUG] ME: Current Working State : Initializing |
| [DEBUG] ME: Current Operation State : Bring up |
| [DEBUG] ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| [DEBUG] ME: Error Code : No Error |
| [DEBUG] ME: Progress Phase : BUP Phase |
| [DEBUG] ME: Power Management Event : Clean Moff->Mx wake |
| [DEBUG] ME: Progress Phase State : Check to see if straps say ME DISABLED |
| [DEBUG] memcfg DDR3 ref clock 133 MHz |
| [DEBUG] memcfg DDR3 clock 1330 MHz |
| [DEBUG] memcfg channel assignment: A: 0, B 1, C 2 |
| [DEBUG] memcfg channel[0] config (00620010): |
| [DEBUG] ECC inactive |
| [DEBUG] enhanced interleave mode on |
| [DEBUG] rank interleave on |
| [DEBUG] DIMMA 4096 MB width x8 dual rank, selected |
| [DEBUG] DIMMB 0 MB width x8 single rank |
| [DEBUG] memcfg channel[1] config (00000000): |
| [DEBUG] ECC inactive |
| [DEBUG] enhanced interleave mode off |
| [DEBUG] rank interleave off |
| [DEBUG] DIMMA 0 MB width x8 single rank, selected |
| [DEBUG] DIMMB 0 MB width x8 single rank |
| [DEBUG] CBMEM: |
| [DEBUG] IMD: root @ 0x7ffff000 254 entries. |
| [DEBUG] IMD: root @ 0x7fffec00 62 entries. |
| [DEBUG] External stage cache: |
| [DEBUG] IMD: root @ 0x803ff000 254 entries. |
| [DEBUG] IMD: root @ 0x803fec00 62 entries. |
| [DEBUG] CBMEM entry for DIMM info: 0x7ffdb000 |
| [INFO ] POST: 0x3b |
| [INFO ] POST: 0x3c |
| [INFO ] POST: 0x3d |
| [INFO ] POST: 0x3f |
| [DEBUG] SMM Memory Map |
| [DEBUG] SMRAM : 0x80000000 0x800000 |
| [DEBUG] Subregion 0: 0x80000000 0x300000 |
| [DEBUG] Subregion 1: 0x80300000 0x100000 |
| [DEBUG] Subregion 2: 0x80400000 0x400000 |
| [DEBUG] Normal boot |
| [INFO ] CBFS: Found 'fallback/postcar' @0x60700 size 0x42ec in mcache @0xfeff1030 |
| [DEBUG] Loading module at 0x7ffd4000 with entry 0x7ffd4031. filesize: 0x3f20 memsize: 0x63d0 |
| [DEBUG] Processing 227 relocs. Offset value of 0x7dfd4000 |
| [DEBUG] BS: romstage times (exec / console): total (unknown) / 3 ms |
| |
| |
| [NOTE ] coreboot-4.12-15826-g6b8c06dc39 Sat Nov 5 12:14:19 UTC 2022 postcar starting (log level: 7)... |
| [DEBUG] Normal boot |
| [INFO ] CBFS: Found 'fallback/ramstage' @0x19b40 size 0x339bc in mcache @0x7ffdd0dc |
| [DEBUG] Loading module at 0x7ff82000 with entry 0x7ff82000. filesize: 0x30378 memsize: 0x50030 |
| [DEBUG] Processing 3457 relocs. Offset value of 0x7bf82000 |
| [DEBUG] BS: postcar times (exec / console): total (unknown) / 0 ms |
| |
| |
| [NOTE ] coreboot-4.12-15826-g6b8c06dc39 Sat Nov 5 12:14:19 UTC 2022 ramstage starting (log level: 7)... |
| [INFO ] POST: 0x39 |
| [INFO ] POST: 0x6f |
| [DEBUG] Normal boot |
| [INFO ] POST: 0x70 |
| [INFO ] POST: 0x71 |
| [INFO ] POST: 0x72 |
| [INFO ] Enumerating buses... |
| [DEBUG] Root Device scanning... |
| [DEBUG] CPU_CLUSTER: 0 enabled |
| [DEBUG] DOMAIN: 0000 enabled |
| [DEBUG] DOMAIN: 0000 scanning... |
| [DEBUG] PCI: pci_scan_bus for bus 00 |
| [INFO ] POST: 0x24 |
| [DEBUG] PCI: 00:00.0 [8086/0150] enabled |
| [DEBUG] PCI: 00:01.0 [8086/0151] enabled |
| [DEBUG] PCI: 00:02.0 [8086/0162] enabled |
| [DEBUG] PCI: 00:14.0 [8086/1e31] enabled |
| [DEBUG] PCI: 00:16.0 [8086/1e3a] enabled |
| [DEBUG] PCI: 00:16.1: Disabling device |
| [DEBUG] PCI: 00:16.2: Disabling device |
| [DEBUG] PCI: 00:16.3: Disabling device |
| [DEBUG] PCI: 00:19.0: Disabling device |
| [DEBUG] PCI: 00:1a.0 [8086/1e2d] enabled |
| [DEBUG] PCI: 00:1b.0 [8086/1e20] enabled |
| [DEBUG] PCI: 00:1c.0 [8086/1e10] enabled |
| [DEBUG] PCI: 00:1c.1: Disabling device |
| [DEBUG] PCI: 00:1c.2: Disabling device |
| [DEBUG] PCI: 00:1c.3: Disabling device |
| [DEBUG] PCI: 00:1c.4 [8086/1e18] enabled |
| [DEBUG] PCI: 00:1c.5: Disabling device |
| [DEBUG] PCI: 00:1c.5 [8086/1e1a] disabled |
| [DEBUG] PCI: 00:1c.6: Disabling device |
| [DEBUG] PCI: 00:1c.6 [8086/1e1c] disabled |
| [DEBUG] PCI: 00:1c.7: Disabling device |
| [DEBUG] PCI: 00:1d.0 [8086/1e26] enabled |
| [DEBUG] PCI: 00:1e.0 [8086/244e] enabled |
| [DEBUG] PCI: 00:1f.0 [8086/1e49] enabled |
| [DEBUG] PCI: 00:1f.2 [8086/1e00] enabled |
| [DEBUG] PCI: 00:1f.3 [8086/1e22] enabled |
| [DEBUG] PCI: 00:1f.4: Disabling device |
| [DEBUG] PCI: 00:1f.5: Disabling device |
| [DEBUG] PCI: 00:1f.5 [8086/1e08] disabled No operations |
| [DEBUG] PCI: 00:1f.6 [8086/1e24] enabled |
| [INFO ] POST: 0x25 |
| [WARN ] PCI: Leftover static devices: |
| [WARN ] PCI: 00:16.1 |
| [WARN ] PCI: 00:16.2 |
| [WARN ] PCI: 00:16.3 |
| [WARN ] PCI: 00:19.0 |
| [WARN ] PCI: 00:1c.1 |
| [WARN ] PCI: 00:1c.2 |
| [WARN ] PCI: 00:1c.3 |
| [WARN ] PCI: 00:1c.7 |
| [WARN ] PCI: 00:1f.4 |
| [WARN ] PCI: Check your devicetree.cb. |
| [DEBUG] PCI: 00:01.0 scanning... |
| [DEBUG] PCI: pci_scan_bus for bus 01 |
| [INFO ] POST: 0x24 |
| [INFO ] POST: 0x25 |
| [INFO ] POST: 0x55 |
| [DEBUG] scan_bus: bus PCI: 00:01.0 finished in 0 msecs |
| [DEBUG] PCI: 00:1c.0 scanning... |
| [DEBUG] PCI: pci_scan_bus for bus 02 |
| [INFO ] POST: 0x24 |
| [INFO ] POST: 0x25 |
| [INFO ] POST: 0x55 |
| [DEBUG] scan_bus: bus PCI: 00:1c.0 finished in 0 msecs |
| [DEBUG] PCI: 00:1c.4 scanning... |
| [DEBUG] PCI: pci_scan_bus for bus 03 |
| [INFO ] POST: 0x24 |
| [DEBUG] PCI: 03:00.0 [10ec/8168] enabled |
| [INFO ] POST: 0x25 |
| [INFO ] POST: 0x55 |
| [INFO ] Enabling Common Clock Configuration |
| [INFO ] ASPM: Enabled L1 |
| [INFO ] PCIe: Max_Payload_Size adjusted to 128 |
| [DEBUG] PCI: 03:00.0: No LTR support |
| [DEBUG] scan_bus: bus PCI: 00:1c.4 finished in 0 msecs |
| [DEBUG] PCI: 00:1e.0 scanning... |
| [DEBUG] PCI: pci_scan_bus for bus 04 |
| [INFO ] POST: 0x24 |
| [INFO ] POST: 0x25 |
| [INFO ] POST: 0x55 |
| [DEBUG] scan_bus: bus PCI: 00:1e.0 finished in 0 msecs |
| [DEBUG] PCI: 00:1f.0 scanning... |
| [DEBUG] PNP: 002e.0 disabled |
| [DEBUG] PNP: 002e.1 enabled |
| [DEBUG] PNP: 002e.2 enabled |
| [DEBUG] PNP: 002e.3 enabled |
| [DEBUG] PNP: 002e.4 enabled |
| [DEBUG] PNP: 002e.5 enabled |
| [DEBUG] PNP: 002e.6 enabled |
| [DEBUG] PNP: 002e.7 disabled |
| [DEBUG] PNP: 002e.a disabled |
| [DEBUG] PNP: 0c31.0 enabled |
| [DEBUG] scan_bus: bus PCI: 00:1f.0 finished in 0 msecs |
| [DEBUG] PCI: 00:1f.3 scanning... |
| [DEBUG] scan_bus: bus PCI: 00:1f.3 finished in 0 msecs |
| [INFO ] POST: 0x55 |
| [DEBUG] scan_bus: bus DOMAIN: 0000 finished in 0 msecs |
| [DEBUG] scan_bus: bus Root Device finished in 0 msecs |
| [INFO ] done |
| [DEBUG] BS: BS_DEV_ENUMERATE run times (exec / console): 1 / 0 ms |
| [DEBUG] FMAP: area RW_MRC_CACHE found @ 700000 (65536 bytes) |
| [INFO ] MRC: No data in cbmem for 'RW_MRC_CACHE'. |
| [INFO ] POST: 0x73 |
| [DEBUG] found VGA at PCI: 00:02.0 |
| [DEBUG] Setting up VGA for PCI: 00:02.0 |
| [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 |
| [DEBUG] Setting PCI_BRIDGE_CTL_VGA for bridge Root Device |
| [INFO ] Allocating resources... |
| [INFO ] Reading resources... |
| [DEBUG] Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. |
| [DEBUG] TOUUD 0x17d600000 TOLUD 0x82a00000 TOM 0x100000000 |
| [DEBUG] MEBASE 0x7ffff00000 |
| [DEBUG] IGD decoded, subtracting 32M UMA and 2M GTT |
| [DEBUG] TSEG base 0x80000000 size 8M |
| [INFO ] Available memory below 4GB: 2048M |
| [INFO ] Available memory above 4GB: 2006M |
| [ERROR] PNP: 0c31.0 missing read_resources |
| [INFO ] Done reading resources. |
| [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === |
| [DEBUG] PCI: 00:1c.4 io: size: 0 align: 12 gran: 12 limit: ffff |
| [DEBUG] PCI: 03:00.0 10 * [0x0 - 0xff] io |
| [DEBUG] PCI: 00:1c.4 io: size: 1000 align: 12 gran: 12 limit: ffff done |
| [DEBUG] PCI: 00:1c.4 mem: size: 0 align: 20 gran: 20 limit: ffffffff |
| [DEBUG] PCI: 00:1c.4 mem: size: 0 align: 20 gran: 20 limit: ffffffff done |
| [DEBUG] PCI: 00:1c.4 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff |
| [DEBUG] PCI: 03:00.0 20 * [0x0 - 0x3fff] prefmem |
| [DEBUG] PCI: 03:00.0 18 * [0x4000 - 0x4fff] prefmem |
| [DEBUG] PCI: 00:1c.4 prefmem: size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done |
| [INFO ] === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === |
| [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff |
| [DEBUG] update_constraints: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed) |
| [DEBUG] update_constraints: PNP: 002e.1 60 base 000003f8 limit 000003ff io (fixed) |
| [DEBUG] update_constraints: PNP: 002e.2 60 base 000002f8 limit 000002ff io (fixed) |
| [DEBUG] update_constraints: PNP: 002e.3 60 base 00000378 limit 0000037b io (fixed) |
| [DEBUG] update_constraints: PNP: 002e.4 60 base 00000a30 limit 00000a37 io (fixed) |
| [DEBUG] update_constraints: PNP: 002e.4 62 base 00000a20 limit 00000a27 io (fixed) |
| [DEBUG] update_constraints: PNP: 002e.5 60 base 00000060 limit 00000060 io (fixed) |
| [DEBUG] update_constraints: PNP: 002e.5 62 base 00000064 limit 00000064 io (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.3 20 base 00000400 limit 0000041f io (fixed) |
| [INFO ] DOMAIN: 0000: Resource ranges: |
| [INFO ] * Base: 1000, Size: f000, Tag: 100 |
| [DEBUG] PCI: 00:1c.4 1c * [0x1000 - 0x1fff] limit: 1fff io |
| [DEBUG] PCI: 00:02.0 20 * [0x2000 - 0x203f] limit: 203f io |
| [DEBUG] PCI: 00:1f.2 20 * [0x2040 - 0x205f] limit: 205f io |
| [DEBUG] PCI: 00:1f.2 10 * [0x2060 - 0x2067] limit: 2067 io |
| [DEBUG] PCI: 00:1f.2 18 * [0x2068 - 0x206f] limit: 206f io |
| [DEBUG] PCI: 00:1f.2 14 * [0x2070 - 0x2073] limit: 2073 io |
| [DEBUG] PCI: 00:1f.2 1c * [0x2074 - 0x2077] limit: 2077 io |
| [DEBUG] DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done |
| [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff |
| [DEBUG] update_constraints: PCI: 00:00.0 60 base f0000000 limit f3ffffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 03 base 00000000 limit 0009ffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 04 base 00100000 limit 7fffffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 05 base 100000000 limit 17d5fffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 06 base 80000000 limit 829fffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 07 base 000a0000 limit 000bffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:00.0 08 base 000c0000 limit 000fffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.0 10000100 base ff000000 limit ffffffff mem (fixed) |
| [DEBUG] update_constraints: PCI: 00:1f.0 03 base fec00000 limit fec00fff mem (fixed) |
| [INFO ] DOMAIN: 0000: Resource ranges: |
| [INFO ] * Base: 82a00000, Size: 6d600000, Tag: 200 |
| [INFO ] * Base: f4000000, Size: ac00000, Tag: 200 |
| [INFO ] * Base: fec01000, Size: 3ff000, Tag: 200 |
| [INFO ] * Base: 17d600000, Size: e82a00000, Tag: 100200 |
| [DEBUG] PCI: 00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem |
| [DEBUG] PCI: 00:02.0 10 * [0x82c00000 - 0x82ffffff] limit: 82ffffff mem |
| [DEBUG] PCI: 00:1c.4 24 * [0x82a00000 - 0x82afffff] limit: 82afffff prefmem |
| [DEBUG] PCI: 00:14.0 10 * [0x82b00000 - 0x82b0ffff] limit: 82b0ffff mem |
| [DEBUG] PCI: 00:1b.0 10 * [0x82b10000 - 0x82b13fff] limit: 82b13fff mem |
| [DEBUG] PCI: 00:1f.6 10 * [0x82b14000 - 0x82b14fff] limit: 82b14fff mem |
| [DEBUG] PCI: 00:1f.2 24 * [0x82b15000 - 0x82b157ff] limit: 82b157ff mem |
| [DEBUG] PCI: 00:1a.0 10 * [0x82b16000 - 0x82b163ff] limit: 82b163ff mem |
| [DEBUG] PCI: 00:1d.0 10 * [0x82b17000 - 0x82b173ff] limit: 82b173ff mem |
| [DEBUG] PCI: 00:1f.3 10 * [0x82b18000 - 0x82b180ff] limit: 82b180ff mem |
| [DEBUG] PCI: 00:16.0 10 * [0x82b19000 - 0x82b1900f] limit: 82b1900f mem |
| [DEBUG] DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: fffffffff done |
| [DEBUG] PCI: 00:1c.4 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff |
| [INFO ] PCI: 00:1c.4: Resource ranges: |
| [INFO ] * Base: 1000, Size: 1000, Tag: 100 |
| [DEBUG] PCI: 03:00.0 10 * [0x1000 - 0x10ff] limit: 10ff io |
| [DEBUG] PCI: 00:1c.4 io: base: 1000 size: 1000 align: 12 gran: 12 limit: 1fff done |
| [DEBUG] PCI: 00:1c.4 prefmem: base: 82a00000 size: 100000 align: 20 gran: 20 limit: 82afffff |
| [INFO ] PCI: 00:1c.4: Resource ranges: |
| [INFO ] * Base: 82a00000, Size: 100000, Tag: 1200 |
| [DEBUG] PCI: 03:00.0 20 * [0x82a00000 - 0x82a03fff] limit: 82a03fff prefmem |
| [DEBUG] PCI: 03:00.0 18 * [0x82a04000 - 0x82a04fff] limit: 82a04fff prefmem |
| [DEBUG] PCI: 00:1c.4 prefmem: base: 82a00000 size: 100000 align: 20 gran: 20 limit: 82afffff done |
| [INFO ] === Resource allocator: DOMAIN: 0000 - resource allocation complete === |
| [DEBUG] PCI: 00:01.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 01 io |
| [DEBUG] PCI: 00:01.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem |
| [DEBUG] PCI: 00:01.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 01 mem |
| [DEBUG] PCI: 00:02.0 10 <- [0x0000000082c00000 - 0x0000000082ffffff] size 0x00400000 gran 0x16 mem64 |
| [DEBUG] PCI: 00:02.0 18 <- [0x0000000090000000 - 0x000000009fffffff] size 0x10000000 gran 0x1c prefmem64 |
| [DEBUG] PCI: 00:02.0 20 <- [0x0000000000002000 - 0x000000000000203f] size 0x00000040 gran 0x06 io |
| [DEBUG] PCI: 00:14.0 10 <- [0x0000000082b00000 - 0x0000000082b0ffff] size 0x00010000 gran 0x10 mem64 |
| [DEBUG] PCI: 00:16.0 10 <- [0x0000000082b19000 - 0x0000000082b1900f] size 0x00000010 gran 0x04 mem64 |
| [DEBUG] PCI: 00:1a.0 10 <- [0x0000000082b16000 - 0x0000000082b163ff] size 0x00000400 gran 0x0a mem |
| [DEBUG] PCI: 00:1b.0 10 <- [0x0000000082b10000 - 0x0000000082b13fff] size 0x00004000 gran 0x0e mem64 |
| [DEBUG] PCI: 00:1c.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 02 io |
| [DEBUG] PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 02 prefmem |
| [DEBUG] PCI: 00:1c.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 02 mem |
| [DEBUG] PCI: 00:1c.4 1c <- [0x0000000000001000 - 0x0000000000001fff] size 0x00001000 gran 0x0c bus 03 io |
| [DEBUG] PCI: 00:1c.4 24 <- [0x0000000082a00000 - 0x0000000082afffff] size 0x00100000 gran 0x14 bus 03 prefmem |
| [DEBUG] PCI: 00:1c.4 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 03 mem |
| [DEBUG] PCI: 03:00.0 10 <- [0x0000000000001000 - 0x00000000000010ff] size 0x00000100 gran 0x08 io |
| [DEBUG] PCI: 03:00.0 18 <- [0x0000000082a04000 - 0x0000000082a04fff] size 0x00001000 gran 0x0c prefmem64 |
| [DEBUG] PCI: 03:00.0 20 <- [0x0000000082a00000 - 0x0000000082a03fff] size 0x00004000 gran 0x0e prefmem64 |
| [DEBUG] PCI: 00:1d.0 10 <- [0x0000000082b17000 - 0x0000000082b173ff] size 0x00000400 gran 0x0a mem |
| [DEBUG] PCI: 00:1e.0 1c <- [0x000000000000ffff - 0x000000000000fffe] size 0x00000000 gran 0x0c bus 04 io |
| [DEBUG] PCI: 00:1e.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 04 prefmem |
| [DEBUG] PCI: 00:1e.0 20 <- [0x00000000ffffffff - 0x00000000fffffffe] size 0x00000000 gran 0x14 bus 04 mem |
| [DEBUG] PNP: 002e.1 60 <- [0x00000000000003f8 - 0x00000000000003ff] size 0x00000008 gran 0x03 io |
| [DEBUG] PNP: 002e.1 70 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 002e.2 60 <- [0x00000000000002f8 - 0x00000000000002ff] size 0x00000008 gran 0x03 io |
| [DEBUG] PNP: 002e.2 70 <- [0x0000000000000003 - 0x0000000000000003] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 002e.3 60 <- [0x0000000000000378 - 0x000000000000037b] size 0x00000004 gran 0x02 io |
| [DEBUG] PNP: 002e.3 70 <- [0x0000000000000007 - 0x0000000000000007] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 002e.3 74 <- [0x0000000000000004 - 0x0000000000000004] size 0x00000001 gran 0x00 drq |
| [DEBUG] PNP: 002e.4 60 <- [0x0000000000000a30 - 0x0000000000000a37] size 0x00000008 gran 0x03 io |
| [DEBUG] PNP: 002e.4 70 <- [0x0000000000000009 - 0x0000000000000009] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 002e.4 62 <- [0x0000000000000a20 - 0x0000000000000a27] size 0x00000008 gran 0x03 io |
| [DEBUG] PNP: 002e.5 60 <- [0x0000000000000060 - 0x0000000000000060] size 0x00000001 gran 0x00 io |
| [DEBUG] PNP: 002e.5 70 <- [0x0000000000000001 - 0x0000000000000001] size 0x00000001 gran 0x00 irq |
| [DEBUG] PNP: 002e.5 62 <- [0x0000000000000064 - 0x0000000000000064] size 0x00000001 gran 0x00 io |
| [DEBUG] PNP: 002e.6 70 <- [0x000000000000000c - 0x000000000000000c] size 0x00000001 gran 0x00 irq |
| [DEBUG] PCI: 00:1f.2 10 <- [0x0000000000002060 - 0x0000000000002067] size 0x00000008 gran 0x03 io |
| [DEBUG] PCI: 00:1f.2 14 <- [0x0000000000002070 - 0x0000000000002073] size 0x00000004 gran 0x02 io |
| [DEBUG] PCI: 00:1f.2 18 <- [0x0000000000002068 - 0x000000000000206f] size 0x00000008 gran 0x03 io |
| [DEBUG] PCI: 00:1f.2 1c <- [0x0000000000002074 - 0x0000000000002077] size 0x00000004 gran 0x02 io |
| [DEBUG] PCI: 00:1f.2 20 <- [0x0000000000002040 - 0x000000000000205f] size 0x00000020 gran 0x05 io |
| [DEBUG] PCI: 00:1f.2 24 <- [0x0000000082b15000 - 0x0000000082b157ff] size 0x00000800 gran 0x0b mem |
| [DEBUG] PCI: 00:1f.3 10 <- [0x0000000082b18000 - 0x0000000082b180ff] size 0x00000100 gran 0x08 mem64 |
| [DEBUG] PCI: 00:1f.6 10 <- [0x0000000082b14000 - 0x0000000082b14fff] size 0x00001000 gran 0x0c mem64 |
| [INFO ] Done setting resources. |
| [INFO ] Done allocating resources. |
| [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 2 / 0 ms |
| [INFO ] POST: 0x74 |
| [INFO ] Enabling resources... |
| [DEBUG] PCI: 00:00.0 subsystem <- 1458/5000 |
| [DEBUG] PCI: 00:00.0 cmd <- 06 |
| [DEBUG] PCI: 00:01.0 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:01.0 subsystem <- 1458/5000 |
| [DEBUG] PCI: 00:01.0 cmd <- 00 |
| [DEBUG] PCI: 00:02.0 subsystem <- 1458/d000 |
| [DEBUG] PCI: 00:02.0 cmd <- 03 |
| [DEBUG] PCI: 00:14.0 subsystem <- 1458/5007 |
| [DEBUG] PCI: 00:14.0 cmd <- 102 |
| [DEBUG] PCI: 00:16.0 subsystem <- 1458/5000 |
| [DEBUG] PCI: 00:16.0 cmd <- 02 |
| [DEBUG] PCI: 00:1a.0 subsystem <- 1458/5006 |
| [DEBUG] PCI: 00:1a.0 cmd <- 102 |
| [DEBUG] PCI: 00:1b.0 subsystem <- 1458/a002 |
| [DEBUG] PCI: 00:1b.0 cmd <- 102 |
| [DEBUG] PCI: 00:1c.0 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1c.0 subsystem <- 1458/5000 |
| [DEBUG] PCI: 00:1c.0 cmd <- 100 |
| [DEBUG] PCI: 00:1c.4 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1c.4 subsystem <- 1458/5000 |
| [DEBUG] PCI: 00:1c.4 cmd <- 107 |
| [DEBUG] PCI: 00:1d.0 subsystem <- 1458/5006 |
| [DEBUG] PCI: 00:1d.0 cmd <- 102 |
| [DEBUG] PCI: 00:1e.0 bridge ctrl <- 0013 |
| [DEBUG] PCI: 00:1e.0 subsystem <- 1458/5000 |
| [DEBUG] PCI: 00:1e.0 cmd <- 100 |
| [DEBUG] PCI: 00:1f.0 subsystem <- 1458/5001 |
| [DEBUG] PCI: 00:1f.0 cmd <- 107 |
| [DEBUG] PCI: 00:1f.2 subsystem <- 1458/b005 |
| [DEBUG] PCI: 00:1f.2 cmd <- 03 |
| [DEBUG] PCI: 00:1f.3 subsystem <- 1458/5001 |
| [DEBUG] PCI: 00:1f.3 cmd <- 103 |
| [DEBUG] PCI: 00:1f.6 cmd <- 02 |
| [DEBUG] PCI: 03:00.0 subsystem <- 1458/e000 |
| [DEBUG] PCI: 03:00.0 cmd <- 103 |
| [INFO ] done. |
| [INFO ] POST: 0x75 |
| [INFO ] Initializing devices... |
| [INFO ] POST: 0x75 |
| [DEBUG] CPU_CLUSTER: 0 init |
| [DEBUG] MTRR: Physical address space: |
| [DEBUG] 0x0000000000000000 - 0x000000000009ffff size 0x000a0000 type 6 |
| [DEBUG] 0x00000000000a0000 - 0x00000000000bffff size 0x00020000 type 0 |
| [DEBUG] 0x00000000000c0000 - 0x000000007fffffff size 0x7ff40000 type 6 |
| [DEBUG] 0x0000000080000000 - 0x000000008fffffff size 0x10000000 type 0 |
| [DEBUG] 0x0000000090000000 - 0x000000009fffffff size 0x10000000 type 1 |
| [DEBUG] 0x00000000a0000000 - 0x00000000ffffffff size 0x60000000 type 0 |
| [DEBUG] 0x0000000100000000 - 0x000000017d5fffff size 0x7d600000 type 6 |
| [DEBUG] MTRR: Fixed MSR 0x250 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x258 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x259 0x0000000000000000 |
| [DEBUG] MTRR: Fixed MSR 0x268 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x269 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26a 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26b 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26c 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26d 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26e 0x0606060606060606 |
| [DEBUG] MTRR: Fixed MSR 0x26f 0x0606060606060606 |
| [DEBUG] CPU physical address size: 36 bits |
| [DEBUG] MTRR: default type WB/UC MTRR counts: 4/3. |
| [DEBUG] MTRR: UC selected as default type. |
| [DEBUG] MTRR: 0 base 0x0000000000000000 mask 0x0000000f80000000 type 6 |
| [DEBUG] MTRR: 1 base 0x0000000090000000 mask 0x0000000ff0000000 type 1 |
| [DEBUG] MTRR: 2 base 0x0000000100000000 mask 0x0000000f80000000 type 6 |
| |
| [DEBUG] MTRR check |
| [DEBUG] Fixed MTRRs : Enabled |
| [DEBUG] Variable MTRRs: Enabled |
| |
| [INFO ] POST: 0x93 |
| [DEBUG] CPU has 4 cores, 8 threads enabled. |
| [DEBUG] Setting up SMI for CPU |
| [INFO ] Will perform SMM setup. |
| [INFO ] CBFS: Found 'cpu_microcode_blob.bin' @0x13300 size 0x6800 in mcache @0x7ffdd0ac |
| [DEBUG] microcode: sig=0x306a9 pf=0x2 revision=0x21 |
| [INFO ] CPU: Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz. |
| [INFO ] LAPIC 0x0 in XAPIC mode. |
| [DEBUG] Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178 |
| [DEBUG] Processing 18 relocs. Offset value of 0x00030000 |
| [DEBUG] Attempting to start 7 APs |
| [DEBUG] Waiting for 10ms after sending INIT. |
| [DEBUG] Waiting for SIPI to complete... |
| [DEBUG] done. |
| [DEBUG] Waiting for SIPI to complete... |
| [DEBUG] done. |
| [INFO ] LAPIC 0x1 in XAPIC mode. |
| [INFO ] AP: slot 1 apic_id 1, MCU rev: 0x00000021 |
| [INFO ] LAPIC 0x5 in XAPIC mode. |
| [INFO ] AP: slot 2 apic_id 5, MCU rev: 0x00000021 |
| [INFO ] LAPIC 0x4 in XAPIC mode. |
| [INFO ] LAPIC 0x2 in XAPIC mode. |
| [INFO ] AP: slot 3 apic_id 4, MCU rev: 0x00000021 |
| [INFO ] AP: slot 7 apic_id 2, MCU rev: 0x00000021 |
| [INFO ] LAPIC 0x3 in XAPIC mode. |
| [INFO ] LAPIC 0x6 in XAPIC mode. |
| [INFO ] LAPIC 0x7 in XAPIC mode. |
| [INFO ] AP: slot 5 apic_id 6, MCU rev: 0x00000021 |
| [INFO ] AP: slot 4 apic_id 7, MCU rev: 0x00000021 |
| [INFO ] AP: slot 6 apic_id 3, MCU rev: 0x00000021 |
| [DEBUG] Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1e8 memsize: 0x1e8 |
| [DEBUG] Processing 11 relocs. Offset value of 0x00038000 |
| [DEBUG] smm_module_setup_stub: stack_top = 0x80002000 |
| [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 |
| [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c |
| [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x10000 |
| [DEBUG] SMM Module: stub loaded at 38000. Will call 0x7ff99865 |
| [DEBUG] Installing permanent SMM handler to 0x80000000 |
| [DEBUG] FX_SAVE [0x802ff000-0x80300000] |
| [DEBUG] HANDLER [0x802fd000-0x802fed30] |
| |
| [DEBUG] CPU 0 |
| [DEBUG] ss0 [0x802fcc00-0x802fd000] |
| [DEBUG] stub0 [0x802f5000-0x802f51e8] |
| |
| [DEBUG] CPU 1 |
| [DEBUG] ss1 [0x802fc800-0x802fcc00] |
| [DEBUG] stub1 [0x802f4c00-0x802f4de8] |
| |
| [DEBUG] CPU 2 |
| [DEBUG] ss2 [0x802fc400-0x802fc800] |
| [DEBUG] stub2 [0x802f4800-0x802f49e8] |
| |
| [DEBUG] CPU 3 |
| [DEBUG] ss3 [0x802fc000-0x802fc400] |
| [DEBUG] stub3 [0x802f4400-0x802f45e8] |
| |
| [DEBUG] CPU 4 |
| [DEBUG] ss4 [0x802fbc00-0x802fc000] |
| [DEBUG] stub4 [0x802f4000-0x802f41e8] |
| |
| [DEBUG] CPU 5 |
| [DEBUG] ss5 [0x802fb800-0x802fbc00] |
| [DEBUG] stub5 [0x802f3c00-0x802f3de8] |
| |
| [DEBUG] CPU 6 |
| [DEBUG] ss6 [0x802fb400-0x802fb800] |
| [DEBUG] stub6 [0x802f3800-0x802f39e8] |
| |
| [DEBUG] CPU 7 |
| [DEBUG] ss7 [0x802fb000-0x802fb400] |
| [DEBUG] stub7 [0x802f3400-0x802f35e8] |
| |
| [DEBUG] stacks [0x80000000-0x80002000] |
| [DEBUG] Loading module at 0x802fd000 with entry 0x802fd772. filesize: 0x1ce8 memsize: 0x1d30 |
| [DEBUG] Processing 83 relocs. Offset value of 0x802fd000 |
| [DEBUG] Loading module at 0x802f5000 with entry 0x802f5000. filesize: 0x1e8 memsize: 0x1e8 |
| [DEBUG] Processing 11 relocs. Offset value of 0x802f5000 |
| [DEBUG] smm_module_setup_stub: stack_top = 0x80002000 |
| [DEBUG] smm_module_setup_stub: per cpu stack_size = 0x400 |
| [DEBUG] smm_module_setup_stub: runtime.start32_offset = 0x4c |
| [DEBUG] smm_module_setup_stub: runtime.smm_size = 0x300000 |
| [DEBUG] SMM Module: placing smm entry code at 802f4c00, cpu # 0x1 |
| [DEBUG] SMM Module: placing smm entry code at 802f4800, cpu # 0x2 |
| [DEBUG] SMM Module: placing smm entry code at 802f4400, cpu # 0x3 |
| [DEBUG] SMM Module: placing smm entry code at 802f4000, cpu # 0x4 |
| [DEBUG] SMM Module: placing smm entry code at 802f3c00, cpu # 0x5 |
| [DEBUG] SMM Module: placing smm entry code at 802f3800, cpu # 0x6 |
| [DEBUG] SMM Module: placing smm entry code at 802f3400, cpu # 0x7 |
| [DEBUG] SMM Module: stub loaded at 802f5000. Will call 0x802fd772 |
| [DEBUG] Initializing southbridge SMI... |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ed000, cpu = 0 |
| [DEBUG] In relocation handler: cpu 0 |
| [DEBUG] New SMBASE=0x802ed000 IEDBASE=0x80400000 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ecc00, cpu = 1 |
| [DEBUG] In relocation handler: cpu 1 |
| [INFO ] microcode: Update skipped, already up-to-date |
| [DEBUG] New SMBASE=0x802ecc00 IEDBASE=0x80400000 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] microcode: Update skipped, already up-to-date |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ec800, cpu = 2 |
| [DEBUG] In relocation handler: cpu 2 |
| [DEBUG] New SMBASE=0x802ec800 IEDBASE=0x80400000 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ec400, cpu = 3 |
| [INFO ] microcode: Update skipped, already up-to-date |
| [DEBUG] In relocation handler: cpu 3 |
| [DEBUG] New SMBASE=0x802ec400 IEDBASE=0x80400000 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] microcode: Update skipped, already up-to-date |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802eb400, cpu = 7 |
| [DEBUG] In relocation handler: cpu 7 |
| [DEBUG] New SMBASE=0x802eb400 IEDBASE=0x80400000 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802eb800, cpu = 6 |
| [INFO ] microcode: Update skipped, already up-to-date |
| [DEBUG] In relocation handler: cpu 6 |
| [DEBUG] New SMBASE=0x802eb800 IEDBASE=0x80400000 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] microcode: Update skipped, already up-to-date |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ec000, cpu = 4 |
| [DEBUG] In relocation handler: cpu 4 |
| [DEBUG] New SMBASE=0x802ec000 IEDBASE=0x80400000 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x802ebc00, cpu = 5 |
| [INFO ] microcode: Update skipped, already up-to-date |
| [DEBUG] In relocation handler: cpu 5 |
| [DEBUG] New SMBASE=0x802ebc00 IEDBASE=0x80400000 |
| [DEBUG] Writing SMRR. base = 0x80000006, mask=0xff800800 |
| [DEBUG] Relocation complete. |
| [INFO ] microcode: Update skipped, already up-to-date |
| [INFO ] Initializing CPU #0 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [INFO ] CPU: Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz. |
| [INFO ] CPU: platform id 1 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT NOT supported |
| [INFO ] CPU: VT supported |
| [DEBUG] VMX status: enabled |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] model_x06ax: frequency set to 3500 |
| [INFO ] Turbo is available but hidden |
| [INFO ] Turbo is available and visible |
| [INFO ] CPU #0 initialized |
| [INFO ] Initializing CPU #1 |
| [INFO ] Initializing CPU #7 |
| [INFO ] Initializing CPU #6 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [INFO ] Initializing CPU #5 |
| [INFO ] Initializing CPU #4 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [INFO ] CPU: Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz. |
| [INFO ] CPU: Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz. |
| [INFO ] CPU: platform id 1 |
| [INFO ] CPU: platform id 1 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT NOT supported |
| [INFO ] CPU: VT supported |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT NOT supported |
| [INFO ] CPU: VT supported |
| [DEBUG] VMX status: enabled |
| [DEBUG] VMX status: enabled |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [INFO ] Initializing CPU #3 |
| [INFO ] Initializing CPU #2 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [DEBUG] CPU: vendor Intel device 306a9 |
| [DEBUG] CPU: family 06, model 3a, stepping 09 |
| [INFO ] CPU: Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz. |
| [INFO ] CPU: Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz. |
| [INFO ] CPU: platform id 1 |
| [INFO ] CPU: platform id 1 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT NOT supported |
| [INFO ] CPU: VT supported |
| [INFO ] CPU: AES supported |
| [DEBUG] VMX status: enabled |
| [INFO ] CPU: TXT NOT supported |
| [INFO ] CPU: VT supported |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] VMX status: enabled |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] cpu: energy policy set to 6 |
| [INFO ] CPU: Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz. |
| [INFO ] CPU: Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz. |
| [INFO ] CPU: platform id 1 |
| [INFO ] CPU: platform id 1 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT NOT supported |
| [INFO ] CPU: VT supported |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT NOT supported |
| [INFO ] CPU: VT supported |
| [DEBUG] VMX status: enabled |
| [DEBUG] VMX status: enabled |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] model_x06ax: frequency set to 3500 |
| [INFO ] CPU #7 initialized |
| [DEBUG] model_x06ax: frequency set to 3500 |
| [INFO ] CPU #6 initialized |
| [DEBUG] model_x06ax: frequency set to 3500 |
| [INFO ] CPU #5 initialized |
| [INFO ] CPU: Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz. |
| [INFO ] CPU: platform id 1 |
| [DEBUG] cpu: energy policy set to 6 |
| [INFO ] CPU: cpuid(1) 0x306a9 |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] cpu: energy policy set to 6 |
| [INFO ] CPU: AES supported |
| [INFO ] CPU: TXT NOT supported |
| [INFO ] CPU: VT supported |
| [DEBUG] model_x06ax: frequency set to 3500 |
| [DEBUG] model_x06ax: frequency set to 3500 |
| [INFO ] CPU #3 initialized |
| [INFO ] CPU #2 initialized |
| [DEBUG] VMX status: enabled |
| [DEBUG] model_x06ax: frequency set to 3500 |
| [INFO ] CPU #4 initialized |
| [DEBUG] IA32_FEATURE_CONTROL status: locked |
| [DEBUG] cpu: energy policy set to 6 |
| [DEBUG] model_x06ax: frequency set to 3500 |
| [INFO ] CPU #1 initialized |
| [INFO ] bsp_do_flight_plan done after 30 msecs. |
| [DEBUG] Initializing southbridge SMI... |
| [DEBUG] SMI_STS: |
| [DEBUG] GPE0_STS: GPIO14 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO1 GPIO0 |
| [DEBUG] ALT_GP_SMI_STS: GPI14 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 |
| [DEBUG] TCO_STS: |
| [DEBUG] Locking SMM. |
| [DEBUG] CPU_CLUSTER: 0 init finished in 44 msecs |
| [INFO ] POST: 0x75 |
| [INFO ] POST: 0x75 |
| [INFO ] POST: 0x75 |
| [INFO ] POST: 0x75 |
| [INFO ] POST: 0x75 |
| [INFO ] POST: 0x75 |
| [INFO ] POST: 0x75 |
| [INFO ] POST: 0x75 |
| [INFO ] POST: 0x75 |
| [INFO ] POST: 0x75 |
| [INFO ] POST: 0x75 |
| [DEBUG] PCI: 00:00.0 init |
| [DEBUG] Disabling PEG12. |
| [DEBUG] Disabling PEG11. |
| [DEBUG] Disabling Device 4. |
| [DEBUG] Disabling PEG60. |
| [DEBUG] Disabling Device 7. |
| [DEBUG] Set BIOS_RESET_CPL |
| [DEBUG] CPU TDP: 77 Watts |
| [DEBUG] PCI: 00:00.0 init finished in 1 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PCI: 00:01.0 init |
| [DEBUG] PCI: 00:01.0 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PCI: 00:02.0 init |
| [WARN ] CBFS: 'vbt.bin' not found. |
| [INFO ] CBFS: Found 'pci8086,0162.rom' @0x506c0 size 0x10000 in mcache @0x7ffdd204 |
| [DEBUG] In CBFS, ROM address for PCI: 00:02.0 = 0xfff608ec |
| [INFO ] GMA: Found VBIOS in CBFS |
| [DEBUG] GMA: locate_vbt_vbios: aa55 8086 0 0 3 |
| [INFO ] GMA: Found valid VBT in VBIOS |
| [DEBUG] GT Power Management Init |
| [DEBUG] IVB GT2 35W Power Meter Weights |
| [INFO ] CBFS: Found 'pci8086,0162.rom' @0x506c0 size 0x10000 in mcache @0x7ffdd204 |
| [DEBUG] In CBFS, ROM address for PCI: 00:02.0 = 0xfff608ec |
| [DEBUG] Copying VGA ROM Image from 0xfff608ec to 0xc0000, 0xe400 bytes |
| [ERROR] Null dereference at eip: 0x7ff91f03 |
| [ERROR] Null dereference at eip: 0x7ff91f1d |
| [DEBUG] Calling Option ROM... |
| [DEBUG] intel_vga_int15_handler: AX=5f51 BX=0205 CX=0000 DX=a0da |
| [DEBUG] intel_vga_int15_handler: AX=5f35 BX=0205 CX=0002 DX=a0da |
| [DEBUG] ... Option ROM returned. |
| [DEBUG] VGA Option ROM was run |
| [DEBUG] GT Power Management Init (post VBIOS) |
| [DEBUG] PCI: 00:02.0 init finished in 43 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PCI: 00:14.0 init |
| [DEBUG] XHCI: Setting up controller.. done. |
| [DEBUG] PCI: 00:14.0 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PCI: 00:16.0 init |
| [DEBUG] ME: FW Partition Table : OK |
| [DEBUG] ME: Bringup Loader Failure : NO |
| [DEBUG] ME: Firmware Init Complete : NO |
| [DEBUG] ME: Manufacturing Mode : YES |
| [DEBUG] ME: Boot Options Present : NO |
| [DEBUG] ME: Update In Progress : NO |
| [DEBUG] ME: Current Working State : Initializing |
| [DEBUG] ME: Current Operation State : Bring up |
| [DEBUG] ME: Current Operation Mode : Debug or Disabled by AltDisableBit |
| [DEBUG] ME: Error Code : No Error |
| [DEBUG] ME: Progress Phase : BUP Phase |
| [DEBUG] ME: Power Management Event : Clean Moff->Mx wake |
| [DEBUG] ME: Progress Phase State : Check to see if straps say ME DISABLED |
| [CRIT ] intel_me_path: mbp is not ready! |
| [NOTE ] ME: BIOS path: Error |
| [DEBUG] No CMOS option 'me_state'. |
| [DEBUG] No CMOS option 'me_state_prev'. |
| [DEBUG] ME: me_state=0, me_state_prev=0 |
| [DEBUG] PCI: 00:16.0 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PCI: 00:1a.0 init |
| [DEBUG] EHCI: Setting up controller.. done. |
| [DEBUG] PCI: 00:1a.0 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PCI: 00:1b.0 init |
| [DEBUG] Azalia: base = 0x82b10000 |
| [DEBUG] Azalia: codec_mask = 0c |
| [DEBUG] azalia_audio: Initializing codec #3 |
| [DEBUG] azalia_audio: codec viddid: 80862806 |
| [DEBUG] azalia_audio: No verb! |
| [DEBUG] azalia_audio: Initializing codec #2 |
| [DEBUG] azalia_audio: codec viddid: 10ec0887 |
| [DEBUG] azalia_audio: No verb! |
| [DEBUG] PCI: 00:1b.0 init finished in 2 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PCI: 00:1c.0 init |
| [DEBUG] Initializing PCH PCIe bridge. |
| [DEBUG] PCI: 00:1c.0 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PCI: 00:1c.4 init |
| [DEBUG] Initializing PCH PCIe bridge. |
| [DEBUG] PCI: 00:1c.4 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [INFO ] POST: 0x75 |
| [INFO ] POST: 0x75 |
| [DEBUG] PCI: 00:1d.0 init |
| [DEBUG] EHCI: Setting up controller.. done. |
| [DEBUG] PCI: 00:1d.0 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PCI: 00:1e.0 init |
| [DEBUG] PCI init. |
| [DEBUG] PCI: 00:1e.0 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PCI: 00:1f.0 init |
| [DEBUG] pch: lpc_init |
| [INFO ] PCH: detected B75, device id: 0x1e49, rev id 0x4 |
| [DEBUG] IOAPIC: Initializing IOAPIC at 0xfec00000 |
| [DEBUG] IOAPIC: ID = 0x02 |
| [DEBUG] IOAPIC: 24 interrupts |
| [DEBUG] IOAPIC: Clearing IOAPIC at 0xfec00000 |
| [DEBUG] IOAPIC: Bootstrap Processor Local APIC = 0x00 |
| [INFO ] Set power on after power failure. |
| [INFO ] NMI sources enabled. |
| [DEBUG] PantherPoint PM init |
| [DEBUG] RTC: failed = 0x0 |
| [DEBUG] RTC Init |
| [DEBUG] apm_control: Disabling ACPI. |
| [DEBUG] APMC done. |
| [DEBUG] pch_spi_init |
| [DEBUG] PCI: 00:1f.0 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PCI: 00:1f.2 init |
| [DEBUG] SATA: Initializing... |
| [DEBUG] SATA: Controller in AHCI mode. |
| [DEBUG] ABAR: 0x82b15000 |
| [DEBUG] PCI: 00:1f.2 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PCI: 00:1f.3 init |
| [DEBUG] PCI: 00:1f.3 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [INFO ] POST: 0x75 |
| [DEBUG] PCI: 00:1f.6 init |
| [DEBUG] PCI: 00:1f.6 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PCI: 03:00.0 init |
| [DEBUG] PCI: 03:00.0 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [INFO ] POST: 0x75 |
| [DEBUG] PNP: 002e.1 init |
| [DEBUG] PNP: 002e.1 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PNP: 002e.2 init |
| [DEBUG] PNP: 002e.2 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PNP: 002e.3 init |
| [DEBUG] PNP: 002e.3 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PNP: 002e.4 init |
| [WARN ] Unsupported thermal mode 0x0 on TMPIN1 |
| [WARN ] Unsupported thermal mode 0x0 on TMPIN2 |
| [WARN ] Unsupported thermal mode 0x0 on TMPIN3 |
| [DEBUG] PNP: 002e.4 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PNP: 002e.5 init |
| [DEBUG] PNP: 002e.5 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [DEBUG] PNP: 002e.6 init |
| [DEBUG] PNP: 002e.6 init finished in 0 msecs |
| [INFO ] POST: 0x75 |
| [INFO ] POST: 0x75 |
| [INFO ] POST: 0x75 |
| [INFO ] Devices initialized |
| [DEBUG] BS: BS_DEV_INIT run times (exec / console): 91 / 1 ms |
| [INFO ] POST: 0x76 |
| [INFO ] Finalize devices... |
| [DEBUG] PCI: 00:1f.0 final |
| [INFO ] Manufacturer: c2 |
| [INFO ] SF: Detected c2 2017 with sector size 0x1000, total 0x800000 |
| [DEBUG] apm_control: Finalizing SMM. |
| [DEBUG] APMC done. |
| [INFO ] Devices finalized |
| [INFO ] POST: 0x77 |
| [INFO ] POST: 0x79 |
| [INFO ] POST: 0x9c |
| [INFO ] CBFS: Found 'fallback/dsdt.aml' @0x4de00 size 0x2337 in mcache @0x7ffdd188 |
| [WARN ] CBFS: 'fallback/slic' not found. |
| [INFO ] ACPI: Writing ACPI tables at 7ff42000. |
| [DEBUG] ACPI: * FACS |
| [DEBUG] ACPI: * DSDT |
| [DEBUG] ACPI: * FADT |
| [DEBUG] ACPI: added table 1/32, length now 40 |
| [DEBUG] ACPI: * SSDT |
| [DEBUG] Found 1 CPU(s) with 8 core(s) each. |
| [DEBUG] PSS: 3501MHz power 77000 control 0x2700 status 0x2700 |
| [DEBUG] PSS: 3500MHz power 77000 control 0x2300 status 0x2300 |
| [DEBUG] PSS: 2800MHz power 56733 control 0x1c00 status 0x1c00 |
| [DEBUG] PSS: 2400MHz power 46310 control 0x1800 status 0x1800 |
| [DEBUG] PSS: 2000MHz power 36756 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1600MHz power 27975 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 3501MHz power 77000 control 0x2700 status 0x2700 |
| [DEBUG] PSS: 3500MHz power 77000 control 0x2300 status 0x2300 |
| [DEBUG] PSS: 2800MHz power 56733 control 0x1c00 status 0x1c00 |
| [DEBUG] PSS: 2400MHz power 46310 control 0x1800 status 0x1800 |
| [DEBUG] PSS: 2000MHz power 36756 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1600MHz power 27975 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 3501MHz power 77000 control 0x2700 status 0x2700 |
| [DEBUG] PSS: 3500MHz power 77000 control 0x2300 status 0x2300 |
| [DEBUG] PSS: 2800MHz power 56733 control 0x1c00 status 0x1c00 |
| [DEBUG] PSS: 2400MHz power 46310 control 0x1800 status 0x1800 |
| [DEBUG] PSS: 2000MHz power 36756 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1600MHz power 27975 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 3501MHz power 77000 control 0x2700 status 0x2700 |
| [DEBUG] PSS: 3500MHz power 77000 control 0x2300 status 0x2300 |
| [DEBUG] PSS: 2800MHz power 56733 control 0x1c00 status 0x1c00 |
| [DEBUG] PSS: 2400MHz power 46310 control 0x1800 status 0x1800 |
| [DEBUG] PSS: 2000MHz power 36756 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1600MHz power 27975 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 3501MHz power 77000 control 0x2700 status 0x2700 |
| [DEBUG] PSS: 3500MHz power 77000 control 0x2300 status 0x2300 |
| [DEBUG] PSS: 2800MHz power 56733 control 0x1c00 status 0x1c00 |
| [DEBUG] PSS: 2400MHz power 46310 control 0x1800 status 0x1800 |
| [DEBUG] PSS: 2000MHz power 36756 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1600MHz power 27975 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 3501MHz power 77000 control 0x2700 status 0x2700 |
| [DEBUG] PSS: 3500MHz power 77000 control 0x2300 status 0x2300 |
| [DEBUG] PSS: 2800MHz power 56733 control 0x1c00 status 0x1c00 |
| [DEBUG] PSS: 2400MHz power 46310 control 0x1800 status 0x1800 |
| [DEBUG] PSS: 2000MHz power 36756 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1600MHz power 27975 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 3501MHz power 77000 control 0x2700 status 0x2700 |
| [DEBUG] PSS: 3500MHz power 77000 control 0x2300 status 0x2300 |
| [DEBUG] PSS: 2800MHz power 56733 control 0x1c00 status 0x1c00 |
| [DEBUG] PSS: 2400MHz power 46310 control 0x1800 status 0x1800 |
| [DEBUG] PSS: 2000MHz power 36756 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1600MHz power 27975 control 0x1000 status 0x1000 |
| [DEBUG] PSS: 3501MHz power 77000 control 0x2700 status 0x2700 |
| [DEBUG] PSS: 3500MHz power 77000 control 0x2300 status 0x2300 |
| [DEBUG] PSS: 2800MHz power 56733 control 0x1c00 status 0x1c00 |
| [DEBUG] PSS: 2400MHz power 46310 control 0x1800 status 0x1800 |
| [DEBUG] PSS: 2000MHz power 36756 control 0x1400 status 0x1400 |
| [DEBUG] PSS: 1600MHz power 27975 control 0x1000 status 0x1000 |
| [DEBUG] PCI space above 4GB MMIO is at 0x17d600000, len = 0xe82a00000 |
| [DEBUG] Generating ACPI PIRQ entries |
| [DEBUG] ACPI: added table 2/32, length now 44 |
| [DEBUG] ACPI: * MCFG |
| [DEBUG] ACPI: added table 3/32, length now 48 |
| [DEBUG] ACPI: * MADT |
| [DEBUG] ACPI: added table 4/32, length now 52 |
| [DEBUG] current = 7ff46880 |
| [DEBUG] ACPI: * HPET |
| [DEBUG] ACPI: added table 5/32, length now 56 |
| [INFO ] ACPI: done. |
| [DEBUG] ACPI tables: 18624 bytes. |
| [DEBUG] smbios_write_tables: 7ff3a000 |
| [DEBUG] SMBIOS firmware version is set to coreboot_version: '4.12-15826-g6b8c06dc39' |
| [INFO ] Create SMBIOS type 16 |
| [INFO ] Create SMBIOS type 17 |
| [INFO ] Create SMBIOS type 20 |
| [DEBUG] SMBIOS tables: 843 bytes. |
| [DEBUG] Writing table forward entry at 0x00000500 |
| [DEBUG] Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 1fe8 |
| [DEBUG] Writing coreboot table at 0x7ff66000 |
| [INFO ] CBFS: Found 'cmos_layout.bin' @0x502c0 size 0x3c8 in mcache @0x7ffdd1dc |
| [DEBUG] 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES |
| [DEBUG] 1. 0000000000001000-000000000009ffff: RAM |
| [DEBUG] 2. 00000000000a0000-00000000000fffff: RESERVED |
| [DEBUG] 3. 0000000000100000-000000007ff39fff: RAM |
| [DEBUG] 4. 000000007ff3a000-000000007ff81fff: CONFIGURATION TABLES |
| [DEBUG] 5. 000000007ff82000-000000007ffd2fff: RAMSTAGE |
| [DEBUG] 6. 000000007ffd3000-000000007fffffff: CONFIGURATION TABLES |
| [DEBUG] 7. 0000000080000000-00000000829fffff: RESERVED |
| [DEBUG] 8. 00000000f0000000-00000000f3ffffff: RESERVED |
| [DEBUG] 9. 0000000100000000-000000017d5fffff: RAM |
| [DEBUG] Wrote coreboot table at: 0x7ff66000, 0x758 bytes, checksum d999 |
| [DEBUG] coreboot table: 1904 bytes. |
| [DEBUG] IMD ROOT 0. 0x7ffff000 0x00001000 |
| [DEBUG] IMD SMALL 1. 0x7fffe000 0x00001000 |
| [DEBUG] CONSOLE 2. 0x7ffde000 0x00020000 |
| [DEBUG] RO MCACHE 3. 0x7ffdd000 0x000003b4 |
| [DEBUG] TIME STAMP 4. 0x7ffdc000 0x00000910 |
| [DEBUG] MEM INFO 5. 0x7ffdb000 0x00000768 |
| [DEBUG] AFTER CAR 6. 0x7ffd3000 0x00008000 |
| [DEBUG] RAMSTAGE 7. 0x7ff81000 0x00052000 |
| [DEBUG] SMM BACKUP 8. 0x7ff71000 0x00010000 |
| [DEBUG] IGD OPREGION 9. 0x7ff6e000 0x00002f3e |
| [DEBUG] COREBOOT 10. 0x7ff66000 0x00008000 |
| [DEBUG] ACPI 11. 0x7ff42000 0x00024000 |
| [DEBUG] SMBIOS 12. 0x7ff3a000 0x00008000 |
| [DEBUG] IMD small region: |
| [DEBUG] IMD ROOT 0. 0x7fffec00 0x00000400 |
| [DEBUG] FMAP 1. 0x7fffeb20 0x000000e0 |
| [DEBUG] ROMSTAGE 2. 0x7fffeb00 0x00000004 |
| [DEBUG] ROMSTG STCK 3. 0x7fffea40 0x000000a8 |
| [DEBUG] ACPI GNVS 4. 0x7fffe940 0x00000100 |
| [DEBUG] BS: BS_WRITE_TABLES run times (exec / console): 3 / 0 ms |
| [INFO ] POST: 0x7a |
| [INFO ] CBFS: Found 'fallback/payload' @0x64a40 size 0x1187f in mcache @0x7ffdd274 |
| [DEBUG] Checking segment from ROM address 0xfff74c6c |
| [DEBUG] Payload being loaded at below 1MiB without region being marked as RAM usable. |
| [DEBUG] Checking segment from ROM address 0xfff74c88 |
| [DEBUG] Loading segment from ROM address 0xfff74c6c |
| [DEBUG] code (compression=1) |
| [DEBUG] New segment dstaddr 0x000dede0 memsize 0x21220 srcaddr 0xfff74ca4 filesize 0x11847 |
| [DEBUG] Loading Segment: addr: 0x000dede0 memsz: 0x0000000000021220 filesz: 0x0000000000011847 |
| [DEBUG] using LZMA |
| [DEBUG] Loading segment from ROM address 0xfff74c88 |
| [DEBUG] Entry Point 0x000fd25b |
| [DEBUG] BS: BS_PAYLOAD_LOAD run times (exec / console): 21 / 0 ms |
| [INFO ] POST: 0x7b |
| [DEBUG] ICH-NM10-PCH: watchdog disabled |
| [DEBUG] Jumping to boot code at 0x000fd25b(0x7ff66000) |
| [INFO ] POST: 0xf8 |
| SeaBIOS (version rel-1.16.0-0-gd239552) |
| BUILD: gcc: (coreboot toolchain v2022-09-18_c8870b1334) 11.2.0 binutils: (GNU Binutils) 2.37 |
| Found coreboot cbmem console @ 7ffde000 |
| Found mainboard GIGABYTE GA-B75M-D3H |
| Relocating init from 0x000e0540 to 0x7feecac0 (size 54432) |
| Found CBFS header at 0xfff1022c |
| multiboot: eax=7ffb1b78, ebx=7ffb1b44 |
| boot order: |
| 1: /pci@i0cf8/*@1f,2/drive@0/disk@0 |
| 2: HALT |
| Found 16 PCI devices (max PCI bus is 04) |
| Copying SMBIOS from 0x7ff3a000 to 0x000f67c0 |
| Copying SMBIOS 3.0 from 0x7ff3a020 to 0x000f67a0 |
| Copying ACPI RSDP from 0x7ff42000 to 0x000f6770 |
| table(50434146)=0x7ff445d0 (via xsdt) |
| Using pmtimer, ioport 0x508 |
| Scan for VGA option rom |
| Running option rom at c000:0003 |
| Turning on vga text mode console |
| SeaBIOS (version rel-1.16.0-0-gd239552) |
| PCI: XHCI at 00:14.0 (mmio 0x82b00000) |
| XHCI init: regs @ 0x82b00000, 8 ports, 32 slots, 32 byte contexts |
| XHCI protocol USB 2.00, 4 ports (offset 1), def 3001 |
| XHCI protocol USB 3.00, 4 ports (offset 5), def 1000 |
| XHCI extcap 0xc1 @ 0x82b08040 |
| XHCI extcap 0xc0 @ 0x82b08070 |
| XHCI extcap 0x1 @ 0x82b08330 |
| EHCI init on dev 00:1a.0 (regs=0x82b16020) |
| EHCI init on dev 00:1d.0 (regs=0x82b17020) |
| AHCI controller at 00:1f.2, iobase 0x82b15000, irq 11 |
| Searching bootorder for: HALT |
| Found 1 lpt ports |
| Found 2 serial ports |
| Got ps2 nak (status=51) |
| XHCI no devices found |
| USB keyboard initialized |
| Initialized USB HUB (1 ports used) |
| Initialized USB HUB (0 ports used) |
| Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0 |
| AHCI/0: Set transfer mode to UDMA-5 |
| Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0 |
| AHCI/0: registering: "AHCI/0: FUJITSU MHV2200BT PL ATA-7 Hard-Disk (186 GiBytes)" |
| All threads complete. |
| Scan for option roms |
| |
| Press ESC for boot menu. |
| |
| Searching bootorder for: HALT |
| drive 0x000f6700: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=390721968 |
| Space available for UMB: ce800-ec000, f5fe0-f6700 |
| Returned 188416 bytes of ZoneHigh |
| e820 map has 7 items: |
| 0: 0000000000000000 - 000000000009fc00 = 1 RAM |
| 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED |
| 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED |
| 3: 0000000000100000 - 000000007ff28000 = 1 RAM |
| 4: 000000007ff28000 - 0000000082a00000 = 2 RESERVED |
| 5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED |
| 6: 0000000100000000 - 000000017d600000 = 1 RAM |
| enter handle_19: |
| NULL |
| Booting from Hard Disk... |
| Booting from 0000:7c00 |