gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/board_tests.tar.gz b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/board_tests.tar.gz
new file mode 100644
index 0000000..0e08d68
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/board_tests.tar.gz
Binary files differ
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/cbfs.txt b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/cbfs.txt
new file mode 100644
index 0000000..84c2448
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/cbfs.txt
@@ -0,0 +1,18 @@
+Name Offset Type Size
+cbfs master header 0x0 cbfs header 32
+cpu_microcode_blob.bin 0x80 microcode 22528
+config 0x5900 raw 386
+revision 0x5ac0 raw 569
+cmos.default 0x5d40 cmos_default 256
+cmos_layout.bin 0x5e80 cmos_layout 1452
+fallback/dsdt.aml 0x6480 raw 9756
+payload_config 0x8b00 raw 1563
+payload_revision 0x9180 raw 233
+(empty) 0x92c0 null 27800
+fallback/romstage 0xff80 stage 69732
+fallback/payload 0x21080 payload 60784
+(empty) 0x2fe40 null 344
+mrc.cache 0x2ffc0 mrc_cache 65536
+fallback/ramstage 0x40000 stage 67755
+(empty) 0x50900 null 716248
+bootblock 0xff700 bootblock 1952
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/config.short.txt b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/config.short.txt
new file mode 100644
index 0000000..fbfae5d
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/config.short.txt
@@ -0,0 +1,11 @@
+# This image was built using coreboot 4.2-619-gd890b45
+CONFIG_VENDOR_GIGABYTE=y
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_HAVE_ME_BIN=y
+# CONFIG_POST_DEVICE is not set
+CONFIG_BOARD_GIGABYTE_GA_B75M_D3H=y
+CONFIG_ENABLE_VMX=y
+CONFIG_IFD_BIN_PATH="src/mainboard/$(MAINBOARDDIR)/descriptor.bin"
+CONFIG_ME_BIN_PATH="src/mainboard/$(MAINBOARDDIR)/me.bin"
+CONFIG_CONSOLE_POST=y
+# CONFIG_POST_IO is not set
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/config.txt b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/config.txt
new file mode 100644
index 0000000..04fbd3d
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/config.txt
@@ -0,0 +1,549 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# coreboot configuration
+#
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+# CONFIG_MULTIPLE_CBFS_INSTANCES is not set
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_ANY_TOOLCHAIN is not set
+# CONFIG_CCACHE is not set
+# CONFIG_FMD_GENPARSER is not set
+# CONFIG_SCONFIG_GENPARSER is not set
+# CONFIG_USE_OPTION_TABLE is not set
+# CONFIG_UNCOMPRESSED_RAMSTAGE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_EARLY_CBMEM_INIT=y
+# CONFIG_COLLECT_TIMESTAMPS is not set
+CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION=y
+# CONFIG_USE_BLOBS is not set
+# CONFIG_COVERAGE is not set
+CONFIG_RELOCATABLE_MODULES=y
+# CONFIG_RELOCATABLE_RAMSTAGE is not set
+CONFIG_FLASHMAP_OFFSET=0x0
+CONFIG_BOOTBLOCK_SIMPLE=y
+# CONFIG_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_CUSTOM=y
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_GENERIC_GPIO_LIB is not set
+# CONFIG_BOARD_ID_AUTO is not set
+# CONFIG_BOARD_ID_MANUAL is not set
+# CONFIG_RAM_CODE_SUPPORT is not set
+# CONFIG_BOOTSPLASH_IMAGE is not set
+CONFIG_ACPI_SATA_GENERATOR=y
+
+#
+# Mainboard
+#
+# CONFIG_VENDOR_A_TREND is not set
+# CONFIG_VENDOR_AAEON is not set
+# CONFIG_VENDOR_ABIT is not set
+# CONFIG_VENDOR_ADLINK is not set
+# CONFIG_VENDOR_ADVANSUS is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_APPLE is not set
+# CONFIG_VENDOR_ARTECGROUP is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_AVALUE is not set
+# CONFIG_VENDOR_AZZA is not set
+# CONFIG_VENDOR_BACHMANN is not set
+# CONFIG_VENDOR_BAP is not set
+# CONFIG_VENDOR_BCOM is not set
+# CONFIG_VENDOR_BIFFEROS is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BROADCOM is not set
+# CONFIG_VENDOR_COMPAQ is not set
+# CONFIG_VENDOR_CUBIETECH is not set
+# CONFIG_VENDOR_DIGITALLOGIC is not set
+# CONFIG_VENDOR_DMP is not set
+# CONFIG_VENDOR_ECS is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_ESD is not set
+# CONFIG_VENDOR_GETAC is not set
+CONFIG_VENDOR_GIGABYTE=y
+# CONFIG_VENDOR_GIZMOSPHERE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_IWAVE is not set
+# CONFIG_VENDOR_IWILL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LANNER is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LINUTOP is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MITAC is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_NEC is not set
+# CONFIG_VENDOR_NOKIA is not set
+# CONFIG_VENDOR_NVIDIA is not set
+# CONFIG_VENDOR_PACKARDBELL is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_RCA is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SOYO is not set
+# CONFIG_VENDOR_SUNW is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TECHNEXION is not set
+# CONFIG_VENDOR_THOMSON is not set
+# CONFIG_VENDOR_TI is not set
+# CONFIG_VENDOR_TRAVERSE is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+# CONFIG_VENDOR_WINENT is not set
+# CONFIG_VENDOR_WYSE is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="gigabyte/ga-b75m-d3h"
+CONFIG_MAINBOARD_PART_NUMBER="GA-B75M-D3H"
+CONFIG_MAINBOARD_VENDOR="GIGABYTE"
+CONFIG_MAX_CPUS=8
+CONFIG_VGA_BIOS_ID="8086,0162"
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+# CONFIG_VGA_BIOS is not set
+# CONFIG_UDELAY_IO is not set
+CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
+CONFIG_DCACHE_RAM_BASE=0xfefe0000
+CONFIG_DCACHE_RAM_SIZE=0x20000
+CONFIG_VGA_BIOS_FILE="pci8086,0162.rom"
+CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="GIGABYTE"
+CONFIG_HAVE_IFD_BIN=y
+CONFIG_HAVE_ME_BIN=y
+CONFIG_DRAM_RESET_GATE_GPIO=25
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_UART_FOR_CONSOLE=0
+CONFIG_ID_SECTION_OFFSET=0x80
+CONFIG_RAMTOP=0x200000
+CONFIG_CACHE_ROM_SIZE_OVERRIDE=0
+CONFIG_CBFS_SIZE=0x100000
+# CONFIG_POST_DEVICE is not set
+# CONFIG_BOARD_GIGABYTE_GA_6BXC is not set
+# CONFIG_BOARD_GIGABYTE_GA_6BXE is not set
+CONFIG_BOARD_GIGABYTE_GA_B75M_D3H=y
+# CONFIG_BOARD_GIGABYTE_GA_B75M_D3V is not set
+# CONFIG_BOARD_GIGABYTE_GA_2761GXDK is not set
+# CONFIG_BOARD_GIGABYTE_M57SLI is not set
+# CONFIG_BOARD_GIGABYTE_MA785GM is not set
+# CONFIG_BOARD_GIGABYTE_MA785GMT is not set
+# CONFIG_BOARD_GIGABYTE_MA78GM is not set
+CONFIG_USBDEBUG_HCD_INDEX=2
+CONFIG_IFD_BIOS_SECTION="0x00600000:0x007fffff"
+CONFIG_IFD_ME_SECTION="0x00001000:0x004fffff"
+CONFIG_BOOT_MEDIA_SPI_BUS=0
+CONFIG_TTYS0_LCS=3
+CONFIG_PAYLOAD_CONFIGFILE=""
+# CONFIG_HAVE_GBE_BIN is not set
+CONFIG_SEABIOS_PS2_TIMEOUT=0
+CONFIG_CPU_ADDR_BITS=36
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+# CONFIG_USBDEBUG is not set
+CONFIG_MAINBOARD_VERSION="1.0"
+# CONFIG_DRIVERS_PS2_KEYBOARD is not set
+CONFIG_BOARD_ROMSIZE_KB_8192=y
+# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_8192=y
+# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=8192
+CONFIG_ROM_SIZE=0x800000
+CONFIG_FMDFILE=""
+# CONFIG_SYSTEM_TYPE_LAPTOP is not set
+
+#
+# Chipset
+#
+
+#
+# SoC
+#
+# CONFIG_SOC_BROADCOM_CYGNUS is not set
+CONFIG_BOOTBLOCK_CPU_INIT="cpu/intel/model_206ax/bootblock.c"
+CONFIG_CPU_SPECIFIC_OPTIONS=y
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x4000
+# CONFIG_BUILD_WITH_FAKE_IFD is not set
+CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/sandybridge/bootblock.c"
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/bd82x6x/bootblock.c"
+CONFIG_CACHE_MRC_SIZE_KB=512
+CONFIG_TTYS0_BASE=0x3f8
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_SERIRQ_CONTINUOUS_MODE=y
+CONFIG_HEAP_SIZE=0x4000
+# CONFIG_SOC_MARVELL_BG4CD is not set
+# CONFIG_SOC_MEDIATEK_MT8173 is not set
+# CONFIG_SOC_NVIDIA_TEGRA124 is not set
+# CONFIG_SOC_NVIDIA_TEGRA132 is not set
+# CONFIG_SOC_NVIDIA_TEGRA210 is not set
+# CONFIG_SOC_QC_IPQ806X is not set
+# CONFIG_SOC_ROCKCHIP_RK3288 is not set
+# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set
+# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set
+# CONFIG_SOC_UCB_RISCV is not set
+
+#
+# CPU
+#
+# CONFIG_CPU_ALLWINNER_A10 is not set
+CONFIG_SOCKET_SPECIFIC_OPTIONS=y
+CONFIG_XIP_ROM_SIZE=0x10000
+CONFIG_NUM_IPI_STARTS=2
+# CONFIG_CPU_AMD_AGESA is not set
+# CONFIG_CPU_AMD_PI is not set
+# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set
+CONFIG_CPU_INTEL_MODEL_306AX=y
+CONFIG_ENABLE_VMX=y
+CONFIG_SSE2=y
+CONFIG_CPU_INTEL_SOCKET_LGA1155=y
+# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set
+# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set
+# CONFIG_CPU_TI_AM335X is not set
+# CONFIG_PARALLEL_CPU_INIT is not set
+CONFIG_UDELAY_LAPIC=y
+CONFIG_LAPIC_MONOTONIC_TIMER=y
+CONFIG_UDELAY_TSC=y
+# CONFIG_TSC_CONSTANT_RATE is not set
+# CONFIG_TSC_MONOTONIC_TIMER is not set
+# CONFIG_UDELAY_TIMER2 is not set
+# CONFIG_TSC_CALIBRATE_WITH_IO is not set
+# CONFIG_TSC_SYNC_LFENCE is not set
+CONFIG_TSC_SYNC_MFENCE=y
+CONFIG_LOGICAL_CPUS=y
+CONFIG_SMM_TSEG=y
+CONFIG_SMM_MODULE_HEAP_SIZE=0x4000
+# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set
+# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set
+# CONFIG_X86_AMD_FIXED_MTRRS is not set
+# CONFIG_PLATFORM_USES_FSP1_0 is not set
+# CONFIG_PARALLEL_MP is not set
+# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set
+# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set
+CONFIG_CACHE_AS_RAM=y
+CONFIG_SMP=y
+CONFIG_AP_SIPI_VECTOR=0xfffff000
+CONFIG_MMX=y
+CONFIG_SSE=y
+CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
+# CONFIG_USES_MICROCODE_HEADER_FILES is not set
+CONFIG_CPU_MICROCODE_CBFS_GENERATE=y
+# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
+# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
+# CONFIG_CPU_MICROCODE_MULTIPLE_FILES is not set
+
+#
+# Northbridge
+#
+# CONFIG_NORTHBRIDGE_AMD_AGESA is not set
+# CONFIG_AMD_NB_CIMX is not set
+# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set
+CONFIG_VIDEO_MB=0
+# CONFIG_NORTHBRIDGE_AMD_PI is not set
+CONFIG_RAMBASE=0x100000
+CONFIG_MRC_CACHE_SIZE=0x10000
+CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE=y
+# CONFIG_IVYBRIDGE_LVDS is not set
+# CONFIG_SANDYBRIDGE_LVDS is not set
+CONFIG_HPET_ADDRESS=0xfed00000
+CONFIG_HPET_MIN_TICKS=0x80
+CONFIG_MAX_PIRQ_LINKS=4
+
+#
+# Southbridge
+#
+# CONFIG_AMD_SB_CIMX is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
+CONFIG_SOUTHBRIDGE_INTEL_C216=y
+CONFIG_SOUTH_BRIDGE_OPTIONS=y
+CONFIG_LOCK_SPI_ON_RESUME_NONE=y
+# CONFIG_LOCK_SPI_ON_RESUME_RO is not set
+# CONFIG_LOCK_SPI_ON_RESUME_NO_ACCESS is not set
+CONFIG_SOUTHBRIDGE_INTEL_COMMON=y
+CONFIG_IFD_BIN_PATH="src/mainboard/$(MAINBOARDDIR)/descriptor.bin"
+CONFIG_ME_BIN_PATH="src/mainboard/$(MAINBOARDDIR)/me.bin"
+# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
+
+#
+# Super I/O
+#
+CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE=y
+CONFIG_SUPERIO_ITE_IT8728F=y
+
+#
+# Embedded Controllers
+#
+CONFIG_HAVE_INTEL_FIRMWARE=y
+
+#
+# Intel Firmware
+#
+# CONFIG_EM100 is not set
+# CONFIG_MAINBOARD_HAS_CHROMEOS is not set
+# CONFIG_UEFI_2_4_BINDING is not set
+# CONFIG_ARCH_ARM is not set
+# CONFIG_ARCH_BOOTBLOCK_ARM is not set
+# CONFIG_ARCH_VERSTAGE_ARM is not set
+# CONFIG_ARCH_ROMSTAGE_ARM is not set
+# CONFIG_ARCH_RAMSTAGE_ARM is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV4 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set
+# CONFIG_ARM_LPAE is not set
+# CONFIG_ARCH_ARM64 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set
+# CONFIG_ARCH_VERSTAGE_ARM64 is not set
+# CONFIG_ARCH_ROMSTAGE_ARM64 is not set
+# CONFIG_ARCH_RAMSTAGE_ARM64 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set
+# CONFIG_ARM64_A53_ERRATUM_843419 is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_BOOTBLOCK_MIPS is not set
+# CONFIG_ARCH_VERSTAGE_MIPS is not set
+# CONFIG_ARCH_ROMSTAGE_MIPS is not set
+# CONFIG_ARCH_RAMSTAGE_MIPS is not set
+# CONFIG_ARCH_RISCV is not set
+# CONFIG_ARCH_BOOTBLOCK_RISCV is not set
+# CONFIG_ARCH_VERSTAGE_RISCV is not set
+# CONFIG_ARCH_ROMSTAGE_RISCV is not set
+# CONFIG_ARCH_RAMSTAGE_RISCV is not set
+CONFIG_ARCH_X86=y
+CONFIG_ARCH_BOOTBLOCK_X86_32=y
+CONFIG_ARCH_VERSTAGE_X86_32=y
+CONFIG_ARCH_ROMSTAGE_X86_32=y
+CONFIG_ARCH_RAMSTAGE_X86_32=y
+# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set
+# CONFIG_ARCH_VERSTAGE_X86_64 is not set
+# CONFIG_ARCH_ROMSTAGE_X86_64 is not set
+# CONFIG_ARCH_RAMSTAGE_X86_64 is not set
+# CONFIG_AP_IN_SIPI_WAIT is not set
+# CONFIG_SIPI_VECTOR_IN_ROM is not set
+# CONFIG_ROMCC is not set
+# CONFIG_LATE_CBMEM_INIT is not set
+CONFIG_PC80_SYSTEM=y
+CONFIG_HAVE_CMOS_DEFAULT=y
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
+# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
+# CONFIG_COMPILE_IN_DSDT is not set
+
+#
+# Devices
+#
+# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set
+CONFIG_NATIVE_VGA_INIT_USE_EDID=y
+# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set
+# CONFIG_VGA_ROM_RUN is not set
+# CONFIG_ON_DEVICE_ROM_RUN is not set
+# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
+# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set
+# CONFIG_SPD_CACHE is not set
+CONFIG_PCI=y
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+# CONFIG_AZALIA_PLUGIN_SUPPORT is not set
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_ASPM=y
+# CONFIG_PCIEXP_CLK_PM is not set
+# CONFIG_EARLY_PCI_BRIDGE is not set
+# CONFIG_PCIEXP_L1_SUB_STATE is not set
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+# CONFIG_PXE_ROM is not set
+# CONFIG_SOFTWARE_I2C is not set
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_AS3722_RTC is not set
+CONFIG_DEVICE_SPECIFIC_OPTIONS=y
+# CONFIG_ELOG is not set
+# CONFIG_GIC is not set
+# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set
+# CONFIG_DRIVERS_I2C_RTD2132 is not set
+# CONFIG_INTEL_DP is not set
+# CONFIG_INTEL_DDI is not set
+CONFIG_INTEL_EDID=y
+CONFIG_INTEL_INT15=y
+CONFIG_INTEL_GMA_ACPI=y
+# CONFIG_DRIVER_INTEL_I210 is not set
+# CONFIG_IPMI_KCS is not set
+# CONFIG_DRIVERS_LENOVO_WACOM is not set
+# CONFIG_DRIVER_MAXIM_MAX77686 is not set
+# CONFIG_DRIVER_PARADE_PS8625 is not set
+CONFIG_DRIVERS_MC146818=y
+# CONFIG_MAINBOARD_HAS_LPC_TPM is not set
+# CONFIG_DRIVERS_RICOH_RCE822 is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_ATOMIC_SEQUENCING=y
+CONFIG_SPI_FLASH_MEMORY_MAPPED=y
+# CONFIG_SPI_FLASH_SMM is not set
+# CONFIG_SPI_FLASH_NO_FAST_READ is not set
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SPI_FLASH_AMIC=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set
+# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set
+# CONFIG_DRIVER_TI_TPS65090 is not set
+# CONFIG_DRIVERS_TI_TPS65913 is not set
+# CONFIG_DRIVERS_TI_TPS65913_RTC is not set
+CONFIG_DRIVERS_UART=y
+CONFIG_DRIVERS_UART_8250IO=y
+# CONFIG_NO_UART_ON_SUPERIO is not set
+# CONFIG_DRIVERS_UART_8250MEM is not set
+# CONFIG_DRIVERS_UART_8250MEM_32 is not set
+# CONFIG_HAVE_UART_SPECIAL is not set
+# CONFIG_DRIVERS_UART_OXPCIE is not set
+# CONFIG_DRIVERS_UART_PL011 is not set
+CONFIG_HAVE_USBDEBUG=y
+CONFIG_HAVE_USBDEBUG_OPTIONS=y
+# CONFIG_DRIVER_XPOWERS_AXP209 is not set
+CONFIG_RTC=y
+# CONFIG_TPM is not set
+CONFIG_STACK_SIZE=0x1000
+CONFIG_MMCONF_SUPPORT_DEFAULT=y
+CONFIG_MMCONF_SUPPORT=y
+# CONFIG_BOOTMODE_STRAPS is not set
+
+#
+# Console
+#
+CONFIG_SQUELCH_EARLY_SMP=y
+CONFIG_CONSOLE_SERIAL=y
+
+#
+# I/O mapped, 8250-compatible
+#
+
+#
+# Serial port base address = 0x3f8
+#
+CONFIG_CONSOLE_SERIAL_115200=y
+# CONFIG_CONSOLE_SERIAL_57600 is not set
+# CONFIG_CONSOLE_SERIAL_38400 is not set
+# CONFIG_CONSOLE_SERIAL_19200 is not set
+# CONFIG_CONSOLE_SERIAL_9600 is not set
+CONFIG_TTYS0_BAUD=115200
+# CONFIG_SPKMODEM is not set
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_NO_POST is not set
+# CONFIG_CMOS_POST is not set
+CONFIG_CONSOLE_POST=y
+# CONFIG_POST_IO is not set
+# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set
+CONFIG_HAVE_ACPI_RESUME=y
+CONFIG_HAVE_HARD_RESET=y
+# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set
+# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set
+CONFIG_HAVE_MONOTONIC_TIMER=y
+# CONFIG_GENERIC_UDELAY is not set
+# CONFIG_TIMER_QUEUE is not set
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+CONFIG_HAVE_SMI_HANDLER=y
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_IOAPIC=y
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+CONFIG_VGA=y
+# CONFIG_GFXUMA is not set
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_COMMON_FADT=y
+
+#
+# System tables
+#
+# CONFIG_GENERATE_MP_TABLE is not set
+# CONFIG_GENERATE_PIRQ_TABLE is not set
+CONFIG_GENERATE_SMBIOS_TABLES=y
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="GA-B75M-D3H"
+
+#
+# Payload
+#
+# CONFIG_PAYLOAD_NONE is not set
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_PAYLOAD_GRUB2 is not set
+CONFIG_PAYLOAD_SEABIOS=y
+# CONFIG_PAYLOAD_LINUX is not set
+# CONFIG_PAYLOAD_TIANOCORE is not set
+CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
+CONFIG_SEABIOS_STABLE=y
+# CONFIG_SEABIOS_MASTER is not set
+# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set
+CONFIG_COMPRESSED_PAYLOAD_LZMA=y
+
+#
+# Debugging
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_FATAL_ASSERTS is not set
+# CONFIG_DEBUG_CBFS is not set
+CONFIG_HAVE_DEBUG_RAM_SETUP=y
+# CONFIG_DEBUG_RAM_SETUP is not set
+# CONFIG_HAVE_DEBUG_CAR is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_SMM_RELOCATION is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_ACPI is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_TRACE is not set
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+CONFIG_WARNINGS_ARE_ERRORS=y
+CONFIG_IASL_WARNINGS_ARE_ERRORS=y
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+# CONFIG_REG_SCRIPT is not set
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/coreboot_console.txt b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/coreboot_console.txt
new file mode 100644
index 0000000..4764b42
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/coreboot_console.txt
@@ -0,0 +1,1780 @@
+
+
+coreboot-4.2-619-gd890b45 Sat Dec 26 19:53:49 UTC 2015 romstage starting...
+Setting up static southbridge registers... done.
+Disabling Watchdog reboot... done.
+Setting up static northbridge registers... done.
+Initializing Graphics...
+Back from sandybridge_early_initialization()
+POST: 0x38
+SMBus controller enabled.
+POST: 0x39
+POST: 0x3a
+CPU id(306a9): Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz
+AES supported, TXT supported, VT supported
+PCH type: B75, device id: 1e49, rev id 4
+Intel ME early init
+Intel ME firmware is ready
+ME: Requested 32MB UMA
+Starting native Platform init
+ Row addr bits : 16
+ Column addr bits : 10
+ Number of ranks : 1
+ DIMM Capacity : 4096 MB
+ CAS latencies : 5 6 7 8 9 10 11
+ tCKmin : 1.250 ns
+ tAAmin : 13.125 ns
+ tWRmin : 15.000 ns
+ tRCDmin : 13.125 ns
+ tRRDmin : 6.000 ns
+ tRPmin : 13.125 ns
+ tRASmin : 35.000 ns
+ tRCmin : 48.125 ns
+ tRFCmin : 260.000 ns
+ tWTRmin : 7.500 ns
+ tRTPmin : 7.500 ns
+ tFAWmin : 30.000 ns
+rankmap[0] = 0x1
+ Row addr bits : 16
+ Column addr bits : 10
+ Number of ranks : 1
+ DIMM Capacity : 4096 MB
+ CAS latencies : 5 6 7 8 9 10 11
+ tCKmin : 1.250 ns
+ tAAmin : 13.125 ns
+ tWRmin : 15.000 ns
+ tRCDmin : 13.125 ns
+ tRRDmin : 6.000 ns
+ tRPmin : 13.125 ns
+ tRASmin : 35.000 ns
+ tRCmin : 48.125 ns
+ tRFCmin : 260.000 ns
+ tWTRmin : 7.500 ns
+ tRTPmin : 7.500 ns
+ tFAWmin : 30.000 ns
+rankmap[1] = 0x1
+ PLL busy...done
+MCU frequency is set at : 800 MHz
+Selected DRAM frequency: 800 MHz
+Minimum CAS latency : 11T
+Selected CAS latency : 11T
+Selected CWL latency : 8T
+Selected tRCD : 11T
+Selected tRP : 11T
+Selected tRAS : 28T
+Selected tWR : 12T
+Selected tFAW : 24T
+Selected tRRD : 5T
+Selected tRTP : 6T
+Selected tWTR : 6T
+Selected tRFC : 208T
+[c14] = 1000000
+[320c] = 24000
+[d14] = 1000000
+[330c] = 24000
+[4000] = 1c8bbb
+[4004] = cc186465
+[400c] = a08b4
+[4298] = 6cd01860
+[42a4] = 41f88200
+[4400] = 1c8bbb
+[4404] = cc186465
+[440c] = a08b4
+[4698] = 6cd01860
+[46a4] = 41f88200
+Done dimm mapping
+PCI:[a0] = 0
+PCI:[a4] = 2
+PCI:[bc] = c2a00000
+PCI:[a8] = 3b600000
+PCI:[ac] = 2
+PCI:[b8] = c0000000
+PCI:[b0] = c0a00000
+PCI:[b4] = c0800000
+PCI:[7c] = 7f
+PCI:[70] = fe000000
+PCI:[74] = 1
+PCI:[78] = fe000c00
+Done memory map
+RCOMP...done
+COMP2 done
+COMP1 done
+FORCE RCOMP and wait 20us...done
+Done io registers
+Done jedec reset
+Done MRS commands
+High adjust 0:0000ffffffffffff
+High adjust 1:00000000ffffffff
+High adjust 2:00000000ffffffff
+High adjust 3:00000000ffffffff
+High adjust 4:00000000ffffffff
+High adjust 5:00000000ffffffff
+High adjust 6:00000000ffffffff
+High adjust 7:00000000ffffffff
+High adjust 0:0000fffffff
+
+*** Log truncated, 2653 characters dropped. ***
+
+Relocate MRC DATA from feffa79c to bffdd000 (1040 bytes)
+POST: 0x3c
+POST: 0x3d
+POST: 0x3f
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'fallback/ramstage'
+CBFS: Found @ offset 740100 size 108ab
+
+
+coreboot-4.2-619-gd890b45 Sat Dec 26 19:53:49 UTC 2015 ramstage starting...
+POST: 0x39
+Moving GDT to bfffe8a0...ok
+POST: 0x80
+Normal boot.
+POST: 0x70
+BS: BS_PRE_DEVICE times (us): entry 0 run 1054 exit 0
+POST: 0x71
+BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1054 exit 0
+POST: 0x72
+Enumerating buses...
+Show all devs... Before device enumeration.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 00: enabled 1
+APIC: acac: enabled 0
+DOMAIN: 0000: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 00:02.0: enabled 1
+PCI: 00:14.0: enabled 1
+PCI: 00:16.0: enabled 1
+PCI: 00:16.1: enabled 0
+PCI: 00:16.2: enabled 0
+PCI: 00:16.3: enabled 0
+PCI: 00:19.0: enabled 0
+PCI: 00:1a.0: enabled 1
+PCI: 00:1b.0: enabled 1
+PCI: 00:1c.0: enabled 1
+PCI: 00:1c.1: enabled 0
+PCI: 00:1c.2: enabled 0
+PCI: 00:1c.3: enabled 0
+PCI: 00:1c.4: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:1c.5: enabled 0
+PCI: 00:1c.6: enabled 0
+PCI: 00:1c.7: enabled 0
+PCI: 00:1d.0: enabled 1
+PCI: 00:1e.0: enabled 1
+PCI: 00:1f.0: enabled 1
+PNP: 002e.0: enabled 0
+PNP: 002e.1: enabled 1
+PNP: 002e.2: enabled 1
+PNP: 002e.3: enabled 1
+PNP: 002e.4: enabled 1
+PNP: 002e.5: enabled 1
+PNP: 002e.6: enabled 1
+PNP: 002e.7: enabled 0
+PNP: 002e.a: enabled 0
+PCI: 00:1f.2: enabled 1
+PCI: 00:1f.3: enabled 1
+PCI: 00:1f.4: enabled 0
+PCI: 00:1f.5: enabled 0
+Compare with tree...
+Root Device: enabled 1
+ CPU_CLUSTER: 0: enabled 1
+ APIC: 00: enabled 1
+ APIC: acac: enabled 0
+ DOMAIN: 0000: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:01.0: enabled 1
+ PCI: 00:02.0: enabled 1
+ PCI: 00:14.0: enabled 1
+ PCI: 00:16.0: enabled 1
+ PCI: 00:16.1: enabled 0
+ PCI: 00:16.2: enabled 0
+ PCI: 00:16.3: enabled 0
+ PCI: 00:19.0: enabled 0
+ PCI: 00:1a.0: enabled 1
+ PCI: 00:1b.0: enabled 1
+ PCI: 00:1c.0: enabled 1
+ PCI: 00:1c.1: enabled 0
+ PCI: 00:1c.2: enabled 0
+ PCI: 00:1c.3: enabled 0
+ PCI: 00:1c.4: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:1c.5: enabled 0
+ PCI: 00:1c.6: enabled 0
+ PCI: 00:1c.7: enabled 0
+ PCI: 00:1d.0: enabled 1
+ PCI: 00:1e.0: enabled 1
+ PCI: 00:1f.0: enabled 1
+ PNP: 002e.0: enabled 0
+ PNP: 002e.1: enabled 1
+ PNP: 002e.2: enabled 1
+ PNP: 002e.3: enabled 1
+ PNP: 002e.4: enabled 1
+ PNP: 002e.5: enabled 1
+ PNP: 002e.6: enabled 1
+ PNP: 002e.7: enabled 0
+ PNP: 002e.a: enabled 0
+ PCI: 00:1f.2: enabled 1
+ PCI: 00:1f.3: enabled 1
+ PCI: 00:1f.4: enabled 0
+ PCI: 00:1f.5: enabled 0
+Root Device scanning...
+root_dev_scan_bus for Root Device
+CPU_CLUSTER: 0 enabled
+DOMAIN: 0000 enabled
+DOMAIN: 0000 scanning...
+PCI: pci_scan_bus for bus 00
+POST: 0x24
+PCI: 00:00.0 [8086/0150] ops
+Normal boot.
+PCI: 00:00.0 [8086/0150] enabled
+Capability: type 0x0d @ 0x88
+Capability: type 0x01 @ 0x80
+Capability: type 0x05 @ 0x90
+Capability: type 0x10 @ 0xa0
+Capability: type 0x0d @ 0x88
+Capability: type 0x01 @ 0x80
+Capability: type 0x05 @ 0x90
+Capability: type 0x10 @ 0xa0
+PCI: 00:01.0 subordinate bus PCI Express
+PCI: 00:01.0 [8086/0151] enabled
+PCI: 00:02.0 [8086/0000] ops
+PCI: 00:02.0 [8086/0162] enabled
+PCI: 00:14.0 [8086/0000] ops
+PCI: 00:14.0 [8086/1e31] enabled
+PCI: 00:16.0 [8086/1e3a] ops
+PCI: 00:16.0 [8086/1e3a] enabled
+PCI: 00:16.1: Disabling device
+PCI: 00:16.1 [8086/1e3b] disabled No operations
+PCI: 00:16.2: Disabling device
+PCI: 00:16.2 [8086/1e3c] disabled No operations
+PCI: 00:16.3: Disabling device
+PCI: 00:16.3 [8086/1e3d] disabled No operations
+PCI: 00:19.0: Disabling device
+PCI: 00:1a.0 [8086/0000] ops
+PCI: 00:1a.0 [8086/1e2d] enabled
+PCI: 00:1b.0 [8086/0000] ops
+PCI: 00:1b.0 [8086/1e20] enabled
+PCI: 00:1c.0 [8086/0000] bus ops
+PCI: 00:1c.0 [8086/1e10] enabled
+PCI: 00:1c.1: Disabling device
+PCI: 00:1c.2: Disabling device
+PCI: 00:1c.3: Disabling device
+PCI: 00:1c.4 [8086/0000] bus ops
+PCI: 00:1c.4 [8086/1e18] enabled
+PCI: 00:1c.5: Disabling device
+PCI: 00:1c.6: Disabling device
+PCI: 00:1c.7: Disabling device
+PCH: RPFN 0x76543210 -> 0xfed4ba90
+PCI: 00:1d.0 [8086/0000] ops
+PCI: 00:1d.0 [8086/1e26] enabled
+Capability: type 0x0d @ 0x50
+Capability: type 0x0d @ 0x50
+PCI: 00:1e.0 [8086/244e] enabled
+PCI: 00:1f.0 [8086/0000] bus ops
+PCI: 00:1f.0 [8086/1e49] enabled
+PCI: 00:1f.2 [8086/0000] ops
+PCI: 00:1f.2 [8086/1e00] enabled
+PCI: 00:1f.3 [8086/0000] bus ops
+PCI: 00:1f.3 [8086/1e22] enabled
+PCI: 00:1f.4: Disabling device
+PCI: 00:1f.5: Disabling device
+POST: 0x25
+PCI: 00:01.0 scanning...
+do_pci_scan_bridge for PCI: 00:01.0
+PCI: pci_scan_bus for bus 01
+POST: 0x24
+POST: 0x25
+POST: 0x55
+scan_bus: scanning of bus PCI: 00:01.0 took 11259 usecs
+PCI: 00:1c.0 scanning...
+do_pci_scan_bridge for PCI: 00:1c.0
+PCI: pci_scan_bus for bus 02
+POST: 0x24
+PCI: 02:00.0 [1106/3432] enabled
+POST: 0x25
+POST: 0x55
+Capability: type 0x01 @ 0x80
+Capability: type 0x05 @ 0x90
+Capability: type 0x10 @ 0xc4
+Capability: type 0x10 @ 0x40
+Enabling Common Clock Configuration
+ASPM: Enabled None
+scan_bus: scanning of bus PCI: 00:1c.0 took 29765 usecs
+PCI: 00:1c.4 scanning...
+do_pci_scan_bridge for PCI: 00:1c.4
+PCI: pci_scan_bus for bus 03
+POST: 0x24
+PCI: 03:00.0 [10ec/8168] enabled
+POST: 0x25
+POST: 0x55
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x70
+Capability: type 0x10 @ 0x40
+Enabling Common Clock Configuration
+ASPM: Enabled L1
+scan_bus: scanning of bus PCI: 00:1c.4 took 29605 usecs
+PCI: 00:1e.0 scanning...
+do_pci_scan_bridge for PCI: 00:1e.0
+PCI: pci_scan_bus for bus 04
+POST: 0x24
+POST: 0x25
+POST: 0x55
+scan_bus: scanning of bus PCI: 00:1e.0 took 11287 usecs
+PCI: 00:1f.0 scanning...
+scan_lpc_bus for PCI: 00:1f.0
+PNP: 002e.0 disabled
+PNP: 002e.1 enabled
+PNP: 002e.2 enabled
+PNP: 002e.3 enabled
+PNP: 002e.4 enabled
+PNP: 002e.5 enabled
+PNP: 002e.6 enabled
+PNP: 002e.7 disabled
+PNP: 002e.a disabled
+scan_lpc_bus for PCI: 00:1f.0 done
+scan_bus: scanning of bus PCI: 00:1f.0 took 25006 usecs
+PCI: 00:1f.3 scanning...
+scan_smbus for PCI: 00:1f.3
+scan_smbus for PCI: 00:1f.3 done
+scan_bus: scanning of bus PCI: 00:1f.3 took 7748 usecs
+POST: 0x55
+scan_bus: scanning of bus DOMAIN: 0000 took 306736 usecs
+root_dev_scan_bus for Root Device done
+scan_bus: scanning of bus Root Device took 324480 usecs
+done
+BS: BS_DEV_ENUMERATE times (us): entry 0 run 522632 exit 0
+POST: 0x73
+found VGA at PCI: 00:02.0
+Setting up VGA for PCI: 00:02.0
+Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
+Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
+Allocating resources...
+Reading resources...
+Root Device read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
+DOMAIN: 0000 read_resources bus 0 link: 0
+Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
+PCI: 00:01.0 read_resources bus 1 link: 0
+PCI: 00:01.0 read_resources bus 1 link: 0 done
+PCI: 00:1c.0 read_resources bus 2 link: 0
+PCI: 00:1c.0 read_resources bus 2 link: 0 done
+PCI: 00:1c.4 read_resources bus 3 link: 0
+PCI: 00:1c.4 read_resources bus 3 link: 0 done
+PCI: 00:1e.0 read_resources bus 4 link: 0
+PCI: 00:1e.0 read_resources bus 4 link: 0 done
+PCI: 00:1f.0 read_resources bus 0 link: 0
+PCI: 00:1f.0 read_resources bus 0 link: 0 done
+DOMAIN: 0000 read_resources bus 0 link: 0 done
+Root Device read_resources bus 0 link: 0 done
+Done reading resources.
+Show resources in subtree (Root Device)...After reading.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 00
+ APIC: 00
+ APIC: acac
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
+ PCI: 00:00.0
+ PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
+ PCI: 00:01.0
+ PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 00:02.0
+ PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
+ PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
+ PCI: 00:14.0
+ PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:16.0
+ PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:16.1
+ PCI: 00:16.2
+ PCI: 00:16.3
+ PCI: 00:19.0
+ PCI: 00:1a.0
+ PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
+ PCI: 00:1b.0
+ PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:1c.0 child on link 0 PCI: 02:00.0
+ PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:1c.1
+ PCI: 00:1c.2
+ PCI: 00:1c.3
+ PCI: 00:1c.4 child on link 0 PCI: 03:00.0
+ PCI: 00:1c.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 03:00.0
+ PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
+ PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18
+ PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
+ PCI: 00:1c.5
+ PCI: 00:1c.6
+ PCI: 00:1c.7
+ PCI: 00:1d.0
+ PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
+ PCI: 00:1e.0
+ PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 00:1f.0 child on link 0 PNP: 002e.0
+ PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 002e.0
+ PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
+ PNP: 002e.1
+ PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
+ PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.2
+ PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
+ PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.3
+ PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags c0000100 index 60
+ PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
+ PNP: 002e.4
+ PNP: 002e.4 resource base a30 size 8 align 3 gran 3 limit fff flags c0000100 index 60
+ PNP: 002e.4 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.4 resource base a20 size 8 align 3 gran 3 limit fff flags c0000100 index 62
+ PNP: 002e.5
+ PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
+ PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
+ PNP: 002e.6
+ PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.7
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
+ PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
+ PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.a
+ PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PCI: 00:1f.2
+ PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
+ PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
+ PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
+ PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
+ PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
+ PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
+ PCI: 00:1f.3
+ PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
+ PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:1f.4
+ PCI: 00:1f.5
+DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
+PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 03:00.0 10 * [0x0 - 0xff] io
+PCI: 00:1c.4 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 00:1e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:1e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.4 1c * [0x0 - 0xfff] io
+PCI: 00:02.0 20 * [0x1000 - 0x103f] io
+PCI: 00:1f.2 20 * [0x1040 - 0x105f] io
+PCI: 00:1f.2 10 * [0x1060 - 0x1067] io
+PCI: 00:1f.2 18 * [0x1068 - 0x106f] io
+PCI: 00:1f.2 14 * [0x1070 - 0x1073] io
+PCI: 00:1f.2 1c * [0x1074 - 0x1077] io
+DOMAIN: 0000 io: base: 1078 size: 1078 align: 12 gran: 0 limit: ffff done
+DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
+PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 02:00.0 10 * [0x0 - 0xfff] mem
+PCI: 00:1c.0 mem: base: 1000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1c.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 03:00.0 20 * [0x0 - 0x3fff] prefmem
+PCI: 03:00.0 18 * [0x4000 - 0x4fff] prefmem
+PCI: 00:1c.4 prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:1c.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:1e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
+PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem
+PCI: 00:1c.0 20 * [0x10400000 - 0x104fffff] mem
+PCI: 00:1c.4 24 * [0x10500000 - 0x105fffff] prefmem
+PCI: 00:14.0 10 * [0x10600000 - 0x1060ffff] mem
+PCI: 00:1b.0 10 * [0x10610000 - 0x10613fff] mem
+PCI: 00:1f.2 24 * [0x10614000 - 0x106147ff] mem
+PCI: 00:1a.0 10 * [0x10615000 - 0x106153ff] mem
+PCI: 00:1d.0 10 * [0x10616000 - 0x106163ff] mem
+PCI: 00:1f.3 10 * [0x10617000 - 0x106170ff] mem
+PCI: 00:16.0 10 * [0x10618000 - 0x1061800f] mem
+DOMAIN: 0000 mem: base: 10618010 size: 10618010 align: 28 gran: 0 limit: ffffffff done
+avoid_fixed_resources: DOMAIN: 0000
+avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
+constrain_resources: PCI: 00:00.0 cf base f0000000 limit f3ffffff mem (fixed)
+constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
+avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 base d0000000 limit efffffff
+Setting resources...
+DOMAIN: 0000 io: base:1000 size:1078 align:12 gran:0 limit:ffff
+PCI: 00:1c.4 1c * [0x1000 - 0x1fff] io
+PCI: 00:02.0 20 * [0x2000 - 0x203f] io
+PCI: 00:1f.2 20 * [0x2040 - 0x205f] io
+PCI: 00:1f.2 10 * [0x2060 - 0x2067] io
+PCI: 00:1f.2 18 * [0x2068 - 0x206f] io
+PCI: 00:1f.2 14 * [0x2070 - 0x2073] io
+PCI: 00:1f.2 1c * [0x2074 - 0x2077] io
+DOMAIN: 0000 io: next_base: 2078 size: 1078 align: 12 gran: 0 done
+PCI: 00:01.0 io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:01.0 io: next_base: ffff size: 0 align: 12 gran: 12 done
+PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done
+PCI: 00:1c.4 io: base:1000 size:1000 align:12 gran:12 limit:1fff
+PCI: 03:00.0 10 * [0x1000 - 0x10ff] io
+PCI: 00:1c.4 io: next_base: 1100 size: 1000 align: 12 gran: 12 done
+PCI: 00:1e.0 io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:1e.0 io: next_base: ffff size: 0 align: 12 gran: 12 done
+DOMAIN: 0000 mem: base:d0000000 size:10618010 align:28 gran:0 limit:efffffff
+PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem
+PCI: 00:02.0 10 * [0xe0000000 - 0xe03fffff] mem
+PCI: 00:1c.0 20 * [0xe0400000 - 0xe04fffff] mem
+PCI: 00:1c.4 24 * [0xe0500000 - 0xe05fffff] prefmem
+PCI: 00:14.0 10 * [0xe0600000 - 0xe060ffff] mem
+PCI: 00:1b.0 10 * [0xe0610000 - 0xe0613fff] mem
+PCI: 00:1f.2 24 * [0xe0614000 - 0xe06147ff] mem
+PCI: 00:1a.0 10 * [0xe0615000 - 0xe06153ff] mem
+PCI: 00:1d.0 10 * [0xe0616000 - 0xe06163ff] mem
+PCI: 00:1f.3 10 * [0xe0617000 - 0xe06170ff] mem
+PCI: 00:16.0 10 * [0xe0618000 - 0xe061800f] mem
+DOMAIN: 0000 mem: next_base: e0618010 size: 10618010 align: 28 gran: 0 done
+PCI: 00:01.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:01.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:01.0 mem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:01.0 mem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.0 mem: base:e0400000 size:100000 align:20 gran:20 limit:e04fffff
+PCI: 02:00.0 10 * [0xe0400000 - 0xe0400fff] mem
+PCI: 00:1c.0 mem: next_base: e0401000 size: 100000 align: 20 gran: 20 done
+PCI: 00:1c.4 prefmem: base:e0500000 size:100000 align:20 gran:20 limit:e05fffff
+PCI: 03:00.0 20 * [0xe0500000 - 0xe0503fff] prefmem
+PCI: 03:00.0 18 * [0xe0504000 - 0xe0504fff] prefmem
+PCI: 00:1c.4 prefmem: next_base: e0505000 size: 100000 align: 20 gran: 20 done
+PCI: 00:1c.4 mem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.4 mem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1e.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1e.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1e.0 mem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1e.0 mem: next_base: efffffff size: 0 align: 20 gran: 20 done
+Root Device assign_resources, bus 0 link: 0
+TOUUD 0x23b600000 TOLUD 0xc2a00000 TOM 0x200000000
+MEBASE 0x1fe000000
+IGD decoded, subtracting 32M UMA and 2M GTT
+TSEG base 0xc0000000 size 8M
+Available memory below 4GB: 3072M
+Available memory above 4GB: 5046M
+Adding PCIe config bar base=0xf0000000 size=0x4000000
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig>
+PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
+PCI: 00:01.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem
+PCI: 00:01.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 mem
+PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64
+PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64
+PCI: 00:02.0 20 <- [0x0000002000 - 0x000000203f] size 0x00000040 gran 0x06 io
+PCI: 00:14.0 10 <- [0x00e0600000 - 0x00e060ffff] size 0x00010000 gran 0x10 mem64
+PCI: 00:16.0 10 <- [0x00e0618000 - 0x00e061800f] size 0x00000010 gran 0x04 mem64
+PCI: 00:1a.0 10 <- [0x00e0615000 - 0x00e06153ff] size 0x00000400 gran 0x0a mem
+PCI: 00:1b.0 10 <- [0x00e0610000 - 0x00e0613fff] size 0x00004000 gran 0x0e mem64
+PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
+PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem
+PCI: 00:1c.0 20 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus 02 mem
+PCI: 00:1c.0 assign_resources, bus 2 link: 0
+PCI: 02:00.0 10 <- [0x00e0400000 - 0x00e0400fff] size 0x00001000 gran 0x0c mem
+PCI: 00:1c.0 assign_resources, bus 2 link: 0
+PCI: 00:1c.4 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io
+PCI: 00:1c.4 24 <- [0x00e0500000 - 0x00e05fffff] size 0x00100000 gran 0x14 bus 03 prefmem
+PCI: 00:1c.4 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem
+PCI: 00:1c.4 assign_resources, bus 3 link: 0
+PCI: 03:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
+PCI: 03:00.0 18 <- [0x00e0504000 - 0x00e0504fff] size 0x00001000 gran 0x0c prefmem64
+PCI: 03:00.0 20 <- [0x00e0500000 - 0x00e0503fff] size 0x00004000 gran 0x0e prefmem64
+PCI: 00:1c.4 assign_resources, bus 3 link: 0
+PCI: 00:1d.0 10 <- [0x00e0616000 - 0x00e06163ff] size 0x00000400 gran 0x0a mem
+PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io
+PCI: 00:1e.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem
+PCI: 00:1e.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 mem
+PCI: 00:1f.0 assign_resources, bus 0 link: 0
+PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
+PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
+PNP: 002e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
+PNP: 002e.2 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
+PNP: 002e.3 60 <- [0x0000000378 - 0x000000037b] size 0x00000004 gran 0x02 io
+PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
+PNP: 002e.3 74 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 drq
+PNP: 002e.4 60 <- [0x0000000a30 - 0x0000000a37] size 0x00000008 gran 0x03 io
+PNP: 002e.4 70 <- [0x0000000009 - 0x0000000009] size 0x00000001 gran 0x00 irq
+PNP: 002e.4 62 <- [0x0000000a20 - 0x0000000a27] size 0x00000008 gran 0x03 io
+PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
+PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
+PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
+PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
+PCI: 00:1f.0 assign_resources, bus 0 link: 0
+PCI: 00:1f.2 10 <- [0x0000002060 - 0x0000002067] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 14 <- [0x0000002070 - 0x0000002073] size 0x00000004 gran 0x02 io
+PCI: 00:1f.2 18 <- [0x0000002068 - 0x000000206f] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 1c <- [0x0000002074 - 0x0000002077] size 0x00000004 gran 0x02 io
+PCI: 00:1f.2 20 <- [0x0000002040 - 0x000000205f] size 0x00000020 gran 0x05 io
+PCI: 00:1f.2 24 <- [0x00e0614000 - 0x00e06147ff] size 0x00000800 gran 0x0b mem
+PCI: 00:1f.3 10 <- [0x00e0617000 - 0x00e06170ff] size 0x00000100 gran 0x08 mem64
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+Root Device assign_resources, bus 0 link: 0
+Done setting resources.
+Show resources in subtree (Root Device)...After assigning values.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 00
+ APIC: 00
+ APIC: acac
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 1000 size 1078 align 12 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base d0000000 size 10618010 align 28 gran 0 limit efffffff flags 40040200 index 10000100
+ DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
+ DOMAIN: 0000 resource base 100000 size bff00000 align 0 gran 0 limit 0 flags e0004200 index 4
+ DOMAIN: 0000 resource base 100000000 size 13b600000 align 0 gran 0 limit 0 flags e0004200 index 5
+ DOMAIN: 0000 resource base c0000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
+ DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7
+ DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8
+ DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9
+ DOMAIN: 0000 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
+ DOMAIN: 0000 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
+ PCI: 00:00.0
+ PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
+ PCI: 00:01.0
+ PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:01.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:01.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20
+ PCI: 00:02.0
+ PCI: 00:02.0 resource base e0000000 size 400000 align 22 gran 22 limit e03fffff flags 60000201 index 10
+ PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 18
+ PCI: 00:02.0 resource base 2000 size 40 align 6 gran 6 limit 203f flags 60000100 index 20
+ PCI: 00:14.0
+ PCI: 00:14.0 resource base e0600000 size 10000 align 16 gran 16 limit e060ffff flags 60000201 index 10
+ PCI: 00:16.0
+ PCI: 00:16.0 resource base e0618000 size 10 align 12 gran 4 limit e061800f flags 60000201 index 10
+ PCI: 00:16.1
+ PCI: 00:16.2
+ PCI: 00:16.3
+ PCI: 00:19.0
+ PCI: 00:1a.0
+ PCI: 00:1a.0 resource base e0615000 size 400 align 12 gran 10 limit e06153ff flags 60000200 index 10
+ PCI: 00:1b.0
+ PCI: 00:1b.0 resource base e0610000 size 4000 align 14 gran 14 limit e0613fff flags 60000201 index 10
+ PCI: 00:1c.0 child on link 0 PCI: 02:00.0
+ PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1c.0 resource base e0400000 size 100000 align 20 gran 20 limit e04fffff flags 60080202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base e0400000 size 1000 align 12 gran 12 limit e0400fff flags 60000200 index 10
+ PCI: 00:1c.1
+ PCI: 00:1c.2
+ PCI: 00:1c.3
+ PCI: 00:1c.4 child on link 0 PCI: 03:00.0
+ PCI: 00:1c.4 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
+ PCI: 00:1c.4 resource base e0500000 size 100000 align 20 gran 20 limit e05fffff flags 60081202 index 24
+ PCI: 00:1c.4 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20
+ PCI: 03:00.0
+ PCI: 03:00.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 10
+ PCI: 03:00.0 resource base e0504000 size 1000 align 12 gran 12 limit e0504fff flags 60001201 index 18
+ PCI: 03:00.0 resource base e0500000 size 4000 align 14 gran 14 limit e0503fff flags 60001201 index 20
+ PCI: 00:1c.5
+ PCI: 00:1c.6
+ PCI: 00:1c.7
+ PCI: 00:1d.0
+ PCI: 00:1d.0 resource base e0616000 size 400 align 12 gran 10 limit e06163ff flags 60000200 index 10
+ PCI: 00:1e.0
+ PCI: 00:1e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1e.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1e.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20
+ PCI: 00:1f.0 child on link 0 PNP: 002e.0
+ PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 002e.0
+ PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
+ PNP: 002e.1
+ PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
+ PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.2
+ PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
+ PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.3
+ PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags e0000100 index 60
+ PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000800 index 74
+ PNP: 002e.4
+ PNP: 002e.4 resource base a30 size 8 align 3 gran 3 limit fff flags e0000100 index 60
+ PNP: 002e.4 resource base 9 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.4 resource base a20 size 8 align 3 gran 3 limit fff flags e0000100 index 62
+ PNP: 002e.5
+ PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
+ PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
+ PNP: 002e.6
+ PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.7
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
+ PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
+ PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.a
+ PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PCI: 00:1f.2
+ PCI: 00:1f.2 resource base 2060 size 8 align 3 gran 3 limit 2067 flags 60000100 index 10
+ PCI: 00:1f.2 resource base 2070 size 4 align 2 gran 2 limit 2073 flags 60000100 index 14
+ PCI: 00:1f.2 resource base 2068 size 8 align 3 gran 3 limit 206f flags 60000100 index 18
+ PCI: 00:1f.2 resource base 2074 size 4 align 2 gran 2 limit 2077 flags 60000100 index 1c
+ PCI: 00:1f.2 resource base 2040 size 20 align 5 gran 5 limit 205f flags 60000100 index 20
+ PCI: 00:1f.2 resource base e0614000 size 800 align 12 gran 11 limit e06147ff flags 60000200 index 24
+ PCI: 00:1f.3
+ PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
+ PCI: 00:1f.3 resource base e0617000 size 100 align 12 gran 8 limit e06170ff flags 60000201 index 10
+ PCI: 00:1f.4
+ PCI: 00:1f.5
+Done allocating resources.
+BS: BS_DEV_RESOURCES times (us): entry 0 run 2299218 exit 0
+POST: 0x74
+Enabling resources...
+PCI: 00:00.0 subsystem <- 1458/5000
+PCI: 00:00.0 cmd <- 06
+PCI: 00:01.0 bridge ctrl <- 0003
+PCI: 00:01.0 cmd <- 00
+PCI: 00:02.0 subsystem <- 1458/d000
+PCI: 00:02.0 cmd <- 03
+PCI: 00:14.0 subsystem <- 1458/5007
+PCI: 00:14.0 cmd <- 102
+PCI: 00:16.0 subsystem <- 1458/5000
+PCI: 00:16.0 cmd <- 02
+PCI: 00:1a.0 subsystem <- 1458/5006
+PCI: 00:1a.0 cmd <- 102
+PCI: 00:1b.0 subsystem <- 1458/a002
+PCI: 00:1b.0 cmd <- 102
+PCI: 00:1c.0 bridge ctrl <- 0003
+PCI: 00:1c.0 subsystem <- 1458/5000
+PCI: 00:1c.0 cmd <- 106
+PCI: 00:1c.4 bridge ctrl <- 0003
+PCI: 00:1c.4 subsystem <- 1458/5000
+PCI: 00:1c.4 cmd <- 107
+PCI: 00:1d.0 subsystem <- 1458/5006
+PCI: 00:1d.0 cmd <- 102
+PCI: 00:1e.0 bridge ctrl <- 0003
+PCI: 00:1e.0 cmd <- 100
+pch_decode_init
+PCI: 00:1f.0 subsystem <- 1458/5001
+PCI: 00:1f.0 cmd <- 107
+PCI: 00:1f.2 subsystem <- 1458/b005
+PCI: 00:1f.2 cmd <- 03
+PCI: 00:1f.3 subsystem <- 1458/5001
+PCI: 00:1f.3 cmd <- 103
+PCI: 02:00.0 cmd <- 02
+PCI: 03:00.0 subsystem <- 1458/e000
+PCI: 03:00.0 cmd <- 103
+done.
+BS: BS_DEV_ENABLE times (us): entry 0 run 93275 exit 0
+POST: 0x75
+Initializing devices...
+Root Device init ...
+Root Device init finished in 1921 usecs
+POST: 0x75
+CPU_CLUSTER: 0 init ...
+start_eip=0x00001000, code_size=0x00000031
+Setting up SMI for CPU
+Loading module at 00038000 with entry 00038000. filesize: 0x160 memsize: 0x160
+Processing 10 relocs. Offset value of 0x00038000
+SMM Module: stub loaded at 00038000. Will call 00113e0a(001316a0)
+Installing SMM handler to 0xc0000000
+Loading module at c0010000 with entry c001010c. filesize: 0xed0 memsize: 0x4ef0
+Processing 50 relocs. Offset value of 0xc0010000
+Loading module at c0008000 with entry c0008000. filesize: 0x160 memsize: 0x160
+Processing 10 relocs. Offset value of 0xc0008000
+SMM Module: placing jmp sequence at c0007c00 rel16 0x03fd
+SMM Module: placing jmp sequence at c0007800 rel16 0x07fd
+SMM Module: placing jmp sequence at c0007400 rel16 0x0bfd
+SMM Module: placing jmp sequence at c0007000 rel16 0x0ffd
+SMM Module: placing jmp sequence at c0006c00 rel16 0x13fd
+SMM Module: placing jmp sequence at c0006800 rel16 0x17fd
+SMM Module: placing jmp sequence at c0006400 rel16 0x1bfd
+SMM Module: stub loaded at c0008000. Will call c001010c(00000000)
+Initializing southbridge SMI... ... pmbase = 0x0500
+
+SMI_STS: PM1
+PM1_STS: PRBTNOR PWRBTN TMROF
+GPE0_STS: GPIO14 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 TCO_SCI
+ALT_GP_SMI_STS: GPI14 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0
+TCO_STS:
+ ... raise SMI#
+In relocation handler: cpu 0
+New SMBASE=0xc0000000 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Relocation complete.
+Locking SMM.
+Initializing CPU #0
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+POST: 0x60
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 700180 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x1b
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Physical address space:
+0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
+0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
+0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
+0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 0
+0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
+0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
+0x0000000100000000 - 0x000000023b600000 size 0x13b600000 type 6
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+MTRR: default type WB/UC MTRR counts: 3/10.
+MTRR: WB selected as default type.
+MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
+MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
+MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+Setting up local apic... apic_id: 0x00 done.
+POST: 0x9b
+Enabling VMX
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+Turbo is available but hidden
+Turbo has been enabled
+CPU: 0 has 4 cores, 2 threads per core
+CPU: 0 has core 1
+CPU1: stack_base 0012b000, stack_end 0012bff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 1.
+After apic_write.
+In relocation handler: cpu 1
+New SMBASE=0xbffffc00 IEDBASE=0xc0400000 @ 0003fc00
+Startup point 1.
+Waiting for send to finish...
++Writing SMRR. base = 0xc0000006, mask=0xff800800
+Sending STARTUP #2 to 1.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+Initializing CPU #1
+CPU: 0 has core 2
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+POST: 0x60
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 700180 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x1b
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+Setting up local apic... apic_id: 0x01 done.
+POST: 0x9b
+Enabling VMX
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #1 initialized
+CPU2: stack_base 0012a000, stack_end 0012aff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 2.
+After apic_write.
+In relocation handler: cpu 2
+Startup point 1.
+Waiting for send to finish...
++New SMBASE=0xbffff800 IEDBASE=0xc0400000 @ 0003fc00
+Sending STARTUP #2 to 2.
+After apic_write.
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 3
+Initializing CPU #2
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+POST: 0x60
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 700180 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x0
+microcode: updated to revision 0x1b date=2014-05-29
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+Setting up local apic... apic_id: 0x02 done.
+POST: 0x9b
+Enabling VMX
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #2 initialized
+CPU3: stack_base 00129000, stack_end 00129ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 3.
+After apic_write.
+In relocation handler: cpu 3
+New SMBASE=0xbffff400 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 3.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 4
+Initializing CPU #3
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+POST: 0x60
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 700180 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x1b
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+Setting up local apic... apic_id: 0x03 done.
+POST: 0x9b
+Enabling VMX
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #3 initialized
+CPU4: stack_base 00128000, stack_end 00128ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 4.
+After apic_write.
+In relocation handler: cpu 4
+Startup point 1.
+Waiting for send to finish...
++New SMBASE=0xbffff000 IEDBASE=0xc0400000 @ 0003fc00
+Sending STARTUP #2 to 4.
+After apic_write.
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 5
+Initializing CPU #4
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+POST: 0x60
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 700180 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x0
+microcode: updated to revision 0x1b date=2014-05-29
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+Setting up local apic... apic_id: 0x04 done.
+POST: 0x9b
+Enabling VMX
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #4 initialized
+CPU5: stack_base 00127000, stack_end 00127ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 5.
+After apic_write.
+In relocation handler: cpu 5
+New SMBASE=0xbfffec00 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 5.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 6
+Initializing CPU #5
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+POST: 0x60
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 700180 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x1b
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+Setting up local apic... apic_id: 0x05 done.
+POST: 0x9b
+Enabling VMX
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #5 initialized
+CPU6: stack_base 00126000, stack_end 00126ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 6.
+After apic_write.
+In relocation handler: cpu 6
+Startup point 1.
+Waiting for send to finish...
++New SMBASE=0xbfffe800 IEDBASE=0xc0400000 @ 0003fc00
+Sending STARTUP #2 to 6.
+After apic_write.
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 7
+Initializing CPU #6
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+POST: 0x60
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 700180 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x0
+microcode: updated to revision 0x1b date=2014-05-29
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+Setting up local apic... apic_id: 0x06 done.
+POST: 0x9b
+Enabling VMX
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #6 initialized
+CPU7: stack_base 00125000, stack_end 00125ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 7.
+After apic_write.
+In relocation handler: cpu 7
+New SMBASE=0xbfffe400 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 7.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU #0 initialized
+Waiting for 1 CPUS to stop
+Initializing CPU #7
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+POST: 0x60
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 700180 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x1b
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+Setting up local apic... apic_id: 0x07 done.
+POST: 0x9b
+Enabling VMX
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #7 initialized
+All AP CPUs stopped (213381 loops)
+CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cacc, stack used: 1332 bytes
+CPU1: stack: 0012b000 - 0012c000, lowest used address 0012bc78, stack used: 904 bytes
+CPU2: stack: 0012a000 - 0012b000, lowest used address 0012ac78, stack used: 904 bytes
+CPU3: stack: 00129000 - 0012a000, lowest used address 00129c78, stack used: 904 bytes
+CPU4: stack: 00128000 - 00129000, lowest used address 00128c78, stack used: 904 bytes
+CPU5: stack: 00127000 - 00128000, lowest used address 00127c78, stack used: 904 bytes
+CPU6: stack: 00126000 - 00127000, lowest used address 00126c78, stack used: 904 bytes
+CPU7: stack: 00125000 - 00126000, lowest used address 00125c78, stack used: 904 bytes
+CPU_CLUSTER: 0 init finished in 24301122 usecs
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+PCI: 00:00.0 init ...
+Disabling PEG12.
+Disabling PEG11.
+Disabling PEG60.
+Set BIOS_RESET_CPL
+CPU TDP: 77 Watts
+PCI: 00:00.0 init finished in 11130 usecs
+POST: 0x75
+POST: 0x75
+PCI: 00:02.0 init ...
+GT Power Management Init
+IVB GT2 35W Power Meter Weights
+GT Power Management Init (post VBIOS)
+PCI: 00:02.0 init finished in 10919 usecs
+POST: 0x75
+PCI: 00:14.0 init ...
+XHCI: Setting up controller.. done.
+PCI: 00:14.0 init finished in 5241 usecs
+POST: 0x75
+PCI: 00:16.0 init ...
+ME: FW Partition Table : OK
+ME: Bringup Loader Failure : NO
+ME: Firmware Init Complete : YES
+ME: Manufacturing Mode : YES
+ME: Boot Options Present : NO
+ME: Update In Progress : NO
+ME: Current Working State : Normal
+ME: Current Operation State : M0 with UMA
+ME: Current Operation Mode : Normal
+ME: Error Code : No Error
+ME: Progress Phase : Host Communication
+ME: Power Management Event : Moff->Mx wake after an error
+ME: Progress Phase State : Host communication established
+ME: BIOS path: Normal
+ME: Extend SHA-256: f0b1b87824433f0a421ddc0cf152d1cd3d2b5e3ce7a373b3333a70ce98dd821d
+ME: MBP item header 00020103
+ME: MBP item header 00050102
+ME: MBP item header 00020501
+ME: MBP item header 00020201
+ME: MBP item header 02030101
+ME: MBP item header 02060301
+ME: MBP item header 02090401
+ME: mbp read OK after 1 cycles
+ME: found version 8.1.30.1350
+ME Capability: Full Network manageability : disabled
+ME Capability: Regular Network manageability : disabled
+ME Capability: Manageability : enabled
+ME Capability: Small business technology : enabled
+ME Capability: Level III manageability : disabled
+ME Capability: IntelR Anti-Theft (AT) : enabled
+ME Capability: IntelR Capability Licensing Service (CLS) : enabled
+ME Capability: IntelR Power Sharing Technology (MPC) : enabled
+ME Capability: ICC Over Clocking : enabled
+ME Capability: Protected Audio Video Path (PAVP) : enabled
+ME Capability: IPV6 : disabled
+ME Capability: KVM Remote Control (KVM) : disabled
+ME Capability: Outbreak Containment Heuristic (OCH) : disabled
+ME Capability: Virtual LAN (VLAN) : enabled
+ME Capability: TLS : enabled
+ME Capability: Wireless LAN (WLAN) : disabled
+PCI: 00:16.0 init finished in 177781 usecs
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+PCI: 00:1a.0 init ...
+EHCI: Setting up controller.. done.
+PCI: 00:1a.0 init finished in 5248 usecs
+POST: 0x75
+PCI: 00:1b.0 init ...
+Azalia: base = e0610000
+Azalia: codec_mask = 0c
+Azalia: Initializing codec #3
+Azalia: codec viddid: 80862806
+Azalia: No verb!
+Azalia: Initializing codec #2
+Azalia: codec viddid: 10ec0887
+Azalia: No verb!
+PCI: 00:1b.0 init finished in 22535 usecs
+POST: 0x75
+PCI: 00:1c.0 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.0 init finished in 4710 usecs
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+PCI: 00:1c.4 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.4 init finished in 4710 usecs
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+PCI: 00:1d.0 init ...
+EHCI: Setting up controller.. done.
+PCI: 00:1d.0 init finished in 5248 usecs
+POST: 0x75
+POST: 0x75
+PCI: 00:1f.0 init ...
+pch: lpc_init
+IOAPIC: Initializing IOAPIC at 0xfec00000
+IOAPIC: Bootstrap Processor Local APIC = 0x00
+IOAPIC: ID = 0x02
+IOAPIC: Dumping registers
+ reg 0x0000: 0x02000000
+ reg 0x0001: 0x00170020
+ reg 0x0002: 0x00170020
+Set power off after power failure.
+NMI sources disabled.
+PantherPoint PM init
+rtc_failed = 0x0
+RTC Init
+Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
+done.
+pch_spi_init
+PCI: 00:1f.0 init finished in 39221 usecs
+POST: 0x75
+PCI: 00:1f.2 init ...
+SATA: Initializing...
+SATA: Controller in AHCI mode.
+ABAR: e0614000
+PCI: 00:1f.2 init finished in 8264 usecs
+POST: 0x75
+PCI: 00:1f.3 init ...
+PCI: 00:1f.3 init finished in 2012 usecs
+POST: 0x75
+POST: 0x75
+POST: 0x75
+PCI: 02:00.0 init ...
+PCI: 02:00.0 init finished in 2007 usecs
+POST: 0x75
+PCI: 03:00.0 init ...
+PCI: 03:00.0 init finished in 2005 usecs
+POST: 0x75
+POST: 0x75
+PNP: 002e.1 init ...
+PNP: 002e.1 init finished in 1919 usecs
+POST: 0x75
+PNP: 002e.2 init ...
+PNP: 002e.2 init finished in 1919 usecs
+POST: 0x75
+PNP: 002e.3 init ...
+PNP: 002e.3 init finished in 1919 usecs
+POST: 0x75
+PNP: 002e.4 init ...
+ITE IT8728F Super I/O HWM: Initializing Hardware Monitor..
+ITE IT8728F Super I/O HWM: Base Address at 0xa35
+PNP: 002e.4 init finished in 11494 usecs
+POST: 0x75
+PNP: 002e.5 init ...
+PNP: 002e.5 init finished in 1947 usecs
+POST: 0x75
+PNP: 002e.6 init ...
+PNP: 002e.6 init finished in 1918 usecs
+POST: 0x75
+POST: 0x75
+Devices initialized
+Show all devs... After init.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 00: enabled 1
+APIC: acac: enabled 0
+DOMAIN: 0000: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 00:02.0: enabled 1
+PCI: 00:14.0: enabled 1
+PCI: 00:16.0: enabled 1
+PCI: 00:16.1: enabled 0
+PCI: 00:16.2: enabled 0
+PCI: 00:16.3: enabled 0
+PCI: 00:19.0: enabled 0
+PCI: 00:1a.0: enabled 1
+PCI: 00:1b.0: enabled 1
+PCI: 00:1c.0: enabled 1
+PCI: 00:1c.1: enabled 0
+PCI: 00:1c.2: enabled 0
+PCI: 00:1c.3: enabled 0
+PCI: 00:1c.4: enabled 1
+PCI: 03:00.0: enabled 1
+PCI: 00:1c.5: enabled 0
+PCI: 00:1c.6: enabled 0
+PCI: 00:1c.7: enabled 0
+PCI: 00:1d.0: enabled 1
+PCI: 00:1e.0: enabled 1
+PCI: 00:1f.0: enabled 1
+PNP: 002e.0: enabled 0
+PNP: 002e.1: enabled 1
+PNP: 002e.2: enabled 1
+PNP: 002e.3: enabled 1
+PNP: 002e.4: enabled 1
+PNP: 002e.5: enabled 1
+PNP: 002e.6: enabled 1
+PNP: 002e.7: enabled 0
+PNP: 002e.a: enabled 0
+PCI: 00:1f.2: enabled 1
+PCI: 00:1f.3: enabled 1
+PCI: 00:1f.4: enabled 0
+PCI: 00:1f.5: enabled 0
+PCI: 02:00.0: enabled 1
+APIC: 01: enabled 1
+APIC: 02: enabled 1
+APIC: 03: enabled 1
+APIC: 04: enabled 1
+APIC: 05: enabled 1
+APIC: 06: enabled 1
+APIC: 07: enabled 1
+BS: BS_DEV_INIT times (us): entry 5 run 24867283 exit 0
+POST: 0x76
+Finalize devices...
+PCI: 00:1f.0 final
+Devices finalized
+BS: BS_POST_DEVICE times (us): entry 0 run 6295 exit 0
+POST: 0x77
+BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1054 exit 0
+Updating MRC cache data.
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'mrc.cache'
+CBFS: Found @ offset 7300c0 size 10000
+find_current_mrc_cache_local: picked entry 4 from cache block
+SF: Detected W25Q64 with sector size 0x1000, total 0x800000
+find_next_mrc_cache: picked next entry from cache block at fff35100
+Finally: write MRC cache update to flash at fff35100
+POST: 0x79
+POST: 0x9c
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'fallback/dsdt.aml'
+CBFS: Found @ offset 706580 size 261c
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'fallback/slic'
+CBFS: 'fallback/slic' not found.
+ACPI: Writing ACPI tables at bfeb9000.
+ACPI: * FACS
+ACPI: * DSDT
+ACPI: * IGD OpRegion
+GET_VBIOS: 87b4 1a1b 29 fe b0
+VBIOS not found.
+ACPI: * FADT
+ACPI: added table 1/32, length now 40
+ACPI: * SSDT
+Found 1 CPU(s) with 8 core(s) each.
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+ACPI: added table 2/32, length now 44
+ACPI: * MCFG
+ACPI: * TCPA
+TCPA log created at bfea6000
+ACPI: added table 3/32, length now 48
+ACPI: * MADT
+ACPI: added table 4/32, length now 52
+current = bfebe200
+ACPI: * DMAR
+ACPI: added table 5/32, length now 56
+current = bfebe2b0
+ACPI: * HPET
+ACPI: added table 6/32, length now 60
+ACPI: done.
+ACPI tables: 21232 bytes.
+smbios_write_tables: bfea5000
+Root Device (GIGABYTE GA-B75M-D3H)
+CPU_CLUSTER: 0 (Intel SandyBridge/IvyBridge integrated Northbridge)
+APIC: 00 (unknown)
+APIC: acac (Intel SandyBridge/IvyBridge CPU)
+DOMAIN: 0000 (Intel SandyBridge/IvyBridge integrated Northbridge)
+PCI: 00:00.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
+PCI: 00:01.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
+PCI: 00:02.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
+PCI: 00:14.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 03:00.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1e.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PNP: 002e.0 (ITE IT8728F Super I/O)
+PNP: 002e.1 (ITE IT8728F Super I/O)
+PNP: 002e.2 (ITE IT8728F Super I/O)
+PNP: 002e.3 (ITE IT8728F Super I/O)
+PNP: 002e.4 (ITE IT8728F Super I/O)
+PNP: 002e.5 (ITE IT8728F Super I/O)
+PNP: 002e.6 (ITE IT8728F Super I/O)
+PNP: 002e.7 (ITE IT8728F Super I/O)
+PNP: 002e.a (ITE IT8728F Super I/O)
+PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1f.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 02:00.0 (unknown)
+APIC: 01 (unknown)
+APIC: 02 (unknown)
+APIC: 03 (unknown)
+APIC: 04 (unknown)
+APIC: 05 (unknown)
+APIC: 06 (unknown)
+APIC: 07 (unknown)
+SMBIOS tables: 355 bytes.
+POST: 0x9e
+POST: 0x9d
+Writing table forward entry at 0x00000500
+Wrote coreboot table at: 00000500, 0x10 bytes, checksum 6ff4
+Table forward entry ends at 0x00000528.
+... aligned to 0x00001000
+Writing coreboot table at 0xbfe9d000
+rom_table_end = 0xbfe9d000
+... aligned to 0xbfea0000
+ 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
+ 1. 0000000000001000-000000000009ffff: RAM
+ 2. 00000000000a0000-00000000000fffff: RESERVED
+ 3. 0000000000100000-00000000bfe9cfff: RAM
+ 4. 00000000bfe9d000-00000000bfffffff: CONFIGURATION TABLES
+ 5. 00000000c0000000-00000000c29fffff: RESERVED
+ 6. 00000000f0000000-00000000f3ffffff: RESERVED
+ 7. 00000000fed90000-00000000fed91fff: RESERVED
+ 8. 0000000100000000-000000023b5fffff: RAM
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+No FMAP found at 0 offset.
+Wrote coreboot table at: bfe9d000, 0x2f0 bytes, checksum 925f
+coreboot table: 776 bytes.
+IMD ROOT 0. bffff000 00001000
+IMD SMALL 1. bfffe000 00001000
+CONSOLE 2. bffde000 00020000
+MRC DATA 3. bffdd000 00000420
+ACPI RESUME 4. bfedd000 00100000
+ACPI 5. bfeb9000 00024000
+ACPI GNVS 6. bfeb8000 00001000
+4f444749 7. bfeb6000 00002000
+TCPA LOG 8. bfea6000 00010000
+SMBIOS 9. bfea5000 00000800
+COREBOOT 10. bfe9d000 00008000
+IMD small region:
+ IMD ROOT 0. bfffec00 00000400
+ CAR GLOBALS 1. bfffeac0 00000140
+ ROMSTAGE 2. bfffeaa0 00000004
+ GDT 3. bfffe8a0 00000200
+BS: BS_WRITE_TABLES times (us): entry 2093317 run 4791474 exit 0
+POST: 0x7a
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'fallback/payload'
+CBFS: Found @ offset 721180 size ed70
+Loading segment from rom address 0xfff211b8
+ code (compression=1)
+ New segment dstaddr 0xe44a4 memsize 0x1bb5c srcaddr 0xfff211f0 filesize 0xed38
+Loading segment from rom address 0xfff211d4
+ Entry Point 0x000ff06e
+Payload being loaded below 1MiB without region being marked as RAM usable.
+Bounce Buffer at bfe32000, 437792 bytes
+Loading Segment: addr: 0x00000000000e44a4 memsz: 0x000000000001bb5c filesz: 0x000000000000ed38
+lb: [0x0000000000100000, 0x0000000000135710)
+Post relocation: addr: 0x00000000000e44a4 memsz: 0x000000000001bb5c filesz: 0x000000000000ed38
+using LZMA
+[ 0x000e44a4, 00100000, 0x00100000) <- fff211f0
+dest 000e44a4, end 00100000, bouncebuffer bfe32000
+Loaded segments
+BS: BS_PAYLOAD_LOAD times (us): entry 0 run 2147231 exit 0
+POST: 0x7b
+PCH watchdog disabled
+Jumping to boot code at 000ff06e(bfe9d000)
+POST: 0xf8
+CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cacc, stack used: 1332 bytes
+entry = 0x000ff06e
+lb_start = 0x00100000
+lb_size = 0x00035710
+buffer = 0xbfe32000
+SeaBIOS (version rel-1.9.0-0-g01a84be)
+BUILD: gcc: (coreboot toolchain v1.31 June 17th, 2015) 4.9.2 binutils: (GNU Binutils) 2.25
+Found coreboot cbmem console @ bffde000
+Found mainboard GIGABYTE GA-B75M-D3H
+Relocating init from 0x000e58b0 to 0xbfe51ed0 (size 45216)
+Found CBFS header at 0xfff00138
+multiboot: eax=0, ebx=0
+Found 16 PCI devices (max PCI bus is 04)
+Copying SMBIOS entry point from 0xbfea5000 to 0x000f0930
+Copying ACPI RSDP from 0xbfeb9000 to 0x000f0900
+Using pmtimer, ioport 0x508
+Scan for VGA option rom
+XHCI init on dev 00:14.0: regs @ 0xe0600000, 8 ports, 32 slots, 32 byte contexts
+XHCI protocol USB 2.00, 4 ports (offset 1), def 3001
+XHCI protocol USB 3.00, 4 ports (offset 5), def 1000
+XHCI extcap 0xc1 @ e0608040
+XHCI extcap 0xc0 @ e0608070
+XHCI extcap 0x1 @ e0608330
+XHCI init on dev 02:00.0: regs @ 0xe0400000, 5 ports, 16 slots, 32 byte contexts
+XHCI extcap 0x1 @ e04000a0
+XHCI protocol USB 2.00, 1 ports (offset 1), def 6
+XHCI protocol USB 3.00, 4 ports (offset 2), def 0
+Found 0 lpt ports
+Found 1 serial ports
+AHCI controller at 1f.2, iobase e0614000, irq 10
+EHCI init on dev 00:1a.0 (regs=0xe0615020)
+EHCI init on dev 00:1d.0 (regs=0xe0616020)
+Got ps2 nak (status=51)
+XHCI port #1: 0x40200e03, powered, enabled, pls 0, speed 3 [High]
+XHCI no devices found
+Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/storage@3/*@0/*@0,0
+Searching bootorder for: /pci@i0cf8/usb@1d/hub@1/usb-*@3
+Searching bootorder for: /pci@i0cf8/*@1f,2/drive@3/disk@0
+AHCI/3: registering: "DVD/CD [AHCI/3: ASUS BC-12B1ST ATAPI-8 DVD/CD]"
+USB mouse initialized
+USB keyboard initialized
+Initialized USB HUB (0 ports used)
+XHCI no devices found
+Initialized USB HUB (2 ports used)
+USB MSC vendor='SanDisk' product='Extreme' rev='0001' type=0 removable=0
+USB MSC blksize=512 sectors=31277232
+Initialized USB HUB (1 ports used)
+All threads complete.
+Scan for option roms
+
+Press ESC for boot menu.
+
+Searching bootorder for: HALT
+drive 0x000f08b0: PCHS=0/0/0 translation=lba LCHS=1024/255/63 s=31277232
+Space available for UMB: c0000-ee000, f0000-f0830
+Returned 53248 bytes of ZoneHigh
+e820 map has 8 items:
+ 0: 0000000000000000 - 000000000009fc00 = 1 RAM
+ 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
+ 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
+ 3: 0000000000100000 - 00000000bfe6a000 = 1 RAM
+ 4: 00000000bfe6a000 - 00000000c2a00000 = 2 RESERVED
+ 5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
+ 6: 00000000fed90000 - 00000000fed92000 = 2 RESERVED
+ 7: 0000000100000000 - 000000023b600000 = 1 RAM
+enter handle_19:
+ NULL
+Booting from DVD/CD...
+Device reports MEDIUM NOT PRESENT
+scsi_is_ready returned -1
+Boot failed: Could not read from CDROM (code 0003)
+enter handle_18:
+ NULL
+Booting from Hard Disk...
+Booting from 0000:7c00
+
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/coreboot_timestamps.txt b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/coreboot_timestamps.txt
new file mode 100644
index 0000000..5acef36
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/coreboot_timestamps.txt
@@ -0,0 +1 @@
+No timestamps found in coreboot table.
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/kernel_log.txt b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/kernel_log.txt
new file mode 100644
index 0000000..bfdfd15
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/kernel_log.txt
@@ -0,0 +1,808 @@
+[ 0.000000] Initializing cgroup subsys cpuset
+[ 0.000000] Initializing cgroup subsys cpu
+[ 0.000000] Initializing cgroup subsys cpuacct
+[ 0.000000] Linux version 3.16.0-38-generic (buildd@allspice) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #52~14.04.1-Ubuntu SMP Fri May 8 09:43:57 UTC 2015 (Ubuntu 3.16.0-38.52~14.04.1-generic 3.16.7-ckt10)
+[ 0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-3.16.0-38-generic root=UUID=a03069c3-2690-4f21-9b08-29ad72edd6bc ro console=tty0 console=ttyS0,115200n8
+[ 0.000000] KERNEL supported cpus:
+[ 0.000000] Intel GenuineIntel
+[ 0.000000] AMD AuthenticAMD
+[ 0.000000] Centaur CentaurHauls
+[ 0.000000] e820: BIOS-provided physical RAM map:
+[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009fbff] usable
+[ 0.000000] BIOS-e820: [mem 0x000000000009fc00-0x000000000009ffff] reserved
+[ 0.000000] BIOS-e820: [mem 0x00000000000f0000-0x00000000000fffff] reserved
+[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x00000000bfe69fff] usable
+[ 0.000000] BIOS-e820: [mem 0x00000000bfe6a000-0x00000000c29fffff] reserved
+[ 0.000000] BIOS-e820: [mem 0x00000000f0000000-0x00000000f3ffffff] reserved
+[ 0.000000] BIOS-e820: [mem 0x00000000fed90000-0x00000000fed91fff] reserved
+[ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000023b5fffff] usable
+[ 0.000000] NX (Execute Disable) protection: active
+[ 0.000000] SMBIOS 2.7 present.
+[ 0.000000] DMI: GIGABYTE GA-B75M-D3H/GA-B75M-D3H, BIOS 4.2-619-gd890b45 12/26/2015
+[ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
+[ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
+[ 0.000000] AGP: No AGP bridge found
+[ 0.000000] e820: last_pfn = 0x23b600 max_arch_pfn = 0x400000000
+[ 0.000000] MTRR default type: write-back
+[ 0.000000] MTRR fixed ranges enabled:
+[ 0.000000] 00000-9FFFF write-back
+[ 0.000000] A0000-BFFFF uncachable
+[ 0.000000] C0000-FFFFF write-back
+[ 0.000000] MTRR variable ranges enabled:
+[ 0.000000] 0 base 0C0000000 mask FF0000000 uncachable
+[ 0.000000] 1 base 0D0000000 mask FF0000000 write-combining
+[ 0.000000] 2 base 0E0000000 mask FE0000000 uncachable
+[ 0.000000] 3 disabled
+[ 0.000000] 4 disabled
+[ 0.000000] 5 disabled
+[ 0.000000] 6 disabled
+[ 0.000000] 7 disabled
+[ 0.000000] 8 disabled
+[ 0.000000] 9 disabled
+[ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106
+[ 0.000000] e820: last_pfn = 0xbfe6a max_arch_pfn = 0x400000000
+[ 0.000000] Scanning 1 areas for low memory corruption
+[ 0.000000] Base memory trampoline at [ffff880000099000] 99000 size 24576
+[ 0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff]
+[ 0.000000] [mem 0x00000000-0x000fffff] page 4k
+[ 0.000000] BRK [0x01fbd000, 0x01fbdfff] PGTABLE
+[ 0.000000] BRK [0x01fbe000, 0x01fbefff] PGTABLE
+[ 0.000000] BRK [0x01fbf000, 0x01fbffff] PGTABLE
+[ 0.000000] init_memory_mapping: [mem 0x23b400000-0x23b5fffff]
+[ 0.000000] [mem 0x23b400000-0x23b5fffff] page 2M
+[ 0.000000] BRK [0x01fc0000, 0x01fc0fff] PGTABLE
+[ 0.000000] init_memory_mapping: [mem 0x238000000-0x23b3fffff]
+[ 0.000000] [mem 0x238000000-0x23b3fffff] page 2M
+[ 0.000000] init_memory_mapping: [mem 0x200000000-0x237ffffff]
+[ 0.000000] [mem 0x200000000-0x237ffffff] page 2M
+[ 0.000000] init_memory_mapping: [mem 0x00100000-0xbfe69fff]
+[ 0.000000] [mem 0x00100000-0x001fffff] page 4k
+[ 0.000000] [mem 0x00200000-0xbfdfffff] page 2M
+[ 0.000000] [mem 0xbfe00000-0xbfe69fff] page 4k
+[ 0.000000] init_memory_mapping: [mem 0x100000000-0x1ffffffff]
+[ 0.000000] [mem 0x100000000-0x1ffffffff] page 2M
+[ 0.000000] BRK [0x01fc1000, 0x01fc1fff] PGTABLE
+[ 0.000000] BRK [0x01fc2000, 0x01fc2fff] PGTABLE
+[ 0.000000] RAMDISK: [mem 0x347ce000-0x363defff]
+[ 0.000000] ACPI: Early table checksum verification disabled
+[ 0.000000] ACPI: RSDP 0x00000000000F0900 000024 (v02 CORE )
+[ 0.000000] ACPI: XSDT 0x00000000BFEB90E0 000054 (v01 CORE COREBOOT 00000000 CORE 00000000)
+[ 0.000000] ACPI: FACP 0x00000000BFEBB8B0 0000F4 (v04 CORE COREBOOT 00000000 CORE 00000000)
+[ 0.000000] ACPI: DSDT 0x00000000BFEB9280 00262C (v03 COREv4 COREBOOT 20141018 INTL 20150619)
+[ 0.000000] ACPI: FACS 0x00000000BFEB9240 000040
+[ 0.000000] ACPI: SSDT 0x00000000BFEBB9B0 00277D (v02 CORE COREBOOT 0000002A CORE 0000002A)
+[ 0.000000] ACPI: TCPA 0x00000000BFEBE130 000032 (v02 CORE COREBOOT 00000000 CORE 00000000)
+[ 0.000000] ACPI: APIC 0x00000000BFEBE170 00008C (v01 CORE COREBOOT 00000000 CORE 00000000)
+[ 0.000000] ACPI: DMAR 0x00000000BFEBE200 0000A8 (v01 CORE COREBOOT 00000000 CORE 00000000)
+[ 0.000000] ACPI: HPET 0x00000000BFEBE2B0 000038 (v01 CORE COREBOOT 00000000 CORE 00000000)
+[ 0.000000] ACPI: Local APIC address 0xfee00000
+[ 0.000000] No NUMA configuration found
+[ 0.000000] Faking a node at [mem 0x0000000000000000-0x000000023b5fffff]
+[ 0.000000] Initmem setup node 0 [mem 0x00000000-0x23b5fffff]
+[ 0.000000] NODE_DATA [mem 0x23b5f6000-0x23b5fafff]
+[ 0.000000] [ffffea0000000000-ffffea0008ffffff] PMD -> [ffff880232c00000-ffff88023abfffff] on node 0
+[ 0.000000] Zone ranges:
+[ 0.000000] DMA [mem 0x00001000-0x00ffffff]
+[ 0.000000] DMA32 [mem 0x01000000-0xffffffff]
+[ 0.000000] Normal [mem 0x100000000-0x23b5fffff]
+[ 0.000000] Movable zone start for each node
+[ 0.000000] Early memory node ranges
+[ 0.000000] node 0: [mem 0x00001000-0x0009efff]
+[ 0.000000] node 0: [mem 0x00100000-0xbfe69fff]
+[ 0.000000] node 0: [mem 0x100000000-0x23b5fffff]
+[ 0.000000] On node 0 totalpages: 2077704
+[ 0.000000] DMA zone: 64 pages used for memmap
+[ 0.000000] DMA zone: 21 pages reserved
+[ 0.000000] DMA zone: 3998 pages, LIFO batch:0
+[ 0.000000] DMA32 zone: 12218 pages used for memmap
+[ 0.000000] DMA32 zone: 781930 pages, LIFO batch:31
+[ 0.000000] Normal zone: 20184 pages used for memmap
+[ 0.000000] Normal zone: 1291776 pages, LIFO batch:31
+[ 0.000000] Reserving Intel graphics stolen memory at 0xc0a00000-0xc29fffff
+[ 0.000000] ACPI: PM-Timer IO Port: 0x508
+[ 0.000000] ACPI: Local APIC address 0xfee00000
+[ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled)
+[ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled)
+[ 0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] enabled)
+[ 0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x03] enabled)
+[ 0.000000] ACPI: LAPIC (acpi_id[0x04] lapic_id[0x04] enabled)
+[ 0.000000] ACPI: LAPIC (acpi_id[0x05] lapic_id[0x05] enabled)
+[ 0.000000] ACPI: LAPIC (acpi_id[0x06] lapic_id[0x06] enabled)
+[ 0.000000] ACPI: LAPIC (acpi_id[0x07] lapic_id[0x07] enabled)
+[ 0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0])
+[ 0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-23
+[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
+[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
+[ 0.000000] ACPI: IRQ0 used by override.
+[ 0.000000] ACPI: IRQ2 used by override.
+[ 0.000000] ACPI: IRQ9 used by override.
+[ 0.000000] Using ACPI (MADT) for SMP configuration information
+[ 0.000000] ACPI: HPET id: 0x8086a701 base: 0xfed00000
+[ 0.000000] smpboot: Allowing 8 CPUs, 0 hotplug CPUs
+[ 0.000000] nr_irqs_gsi: 40
+[ 0.000000] PM: Registered nosave memory: [mem 0x0009f000-0x0009ffff]
+[ 0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000effff]
+[ 0.000000] PM: Registered nosave memory: [mem 0x000f0000-0x000fffff]
+[ 0.000000] PM: Registered nosave memory: [mem 0xbfe6a000-0xc29fffff]
+[ 0.000000] PM: Registered nosave memory: [mem 0xc2a00000-0xefffffff]
+[ 0.000000] PM: Registered nosave memory: [mem 0xf0000000-0xf3ffffff]
+[ 0.000000] PM: Registered nosave memory: [mem 0xf4000000-0xfed8ffff]
+[ 0.000000] PM: Registered nosave memory: [mem 0xfed90000-0xfed91fff]
+[ 0.000000] PM: Registered nosave memory: [mem 0xfed92000-0xffffffff]
+[ 0.000000] e820: [mem 0xc2a00000-0xefffffff] available for PCI devices
+[ 0.000000] Booting paravirtualized kernel on bare hardware
+[ 0.000000] setup_percpu: NR_CPUS:256 nr_cpumask_bits:256 nr_cpu_ids:8 nr_node_ids:1
+[ 0.000000] PERCPU: Embedded 27 pages/cpu @ffff88023b200000 s81408 r8192 d20992 u262144
+[ 0.000000] pcpu-alloc: s81408 r8192 d20992 u262144 alloc=1*2097152
+[ 0.000000] pcpu-alloc: [0] 0 1 2 3 4 5 6 7
+[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 2045217
+[ 0.000000] Policy zone: Normal
+[ 0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-3.16.0-38-generic root=UUID=a03069c3-2690-4f21-9b08-29ad72edd6bc ro console=tty0 console=ttyS0,115200n8
+[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
+[ 0.000000] xsave: enabled xstate_bv 0x7, cntxt size 0x340
+[ 0.000000] AGP: Checking aperture...
+[ 0.000000] AGP: No AGP bridge found
+[ 0.000000] Calgary: detecting Calgary via BIOS EBDA area
+[ 0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing!
+[ 0.000000] Memory: 8067572K/8310816K available (7626K kernel code, 1131K rwdata, 3596K rodata, 1352K init, 1300K bss, 243244K reserved)
+[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
+[ 0.000000] Hierarchical RCU implementation.
+[ 0.000000] RCU dyntick-idle grace-period acceleration is enabled.
+[ 0.000000] RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
+[ 0.000000] Offload RCU callbacks from all CPUs
+[ 0.000000] Offload RCU callbacks from CPUs: 0-7.
+[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
+[ 0.000000] NR_IRQS:16640 nr_irqs:744 16
+[ 0.000000] Console: colour dummy device 80x25
+[ 0.000000] console [tty0] enabled
+[ 0.000000] console [ttyS0] enabled
+[ 0.000000] allocated 33554432 bytes of page_cgroup
+[ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups
+[ 0.000000] hpet clockevent registered
+[ 0.000000] tsc: Fast TSC calibration using PIT
+[ 0.000000] tsc: Detected 3392.348 MHz processor
+[ 0.000026] Calibrating delay loop (skipped), value calculated using timer frequency.. 6784.69 BogoMIPS (lpj=13569392)
+[ 0.010743] pid_max: default: 32768 minimum: 301
+[ 0.015368] ACPI: Core revision 20140424
+[ 0.020853] ACPI: All ACPI Tables successfully acquired
+[ 0.026149] Security Framework initialized
+[ 0.030264] AppArmor: AppArmor initialized
+[ 0.034370] Yama: becoming mindful.
+[ 0.038233] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes)
+[ 0.047017] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes)
+[ 0.054816] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes)
+[ 0.061699] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes)
+[ 0.069177] Initializing cgroup subsys memory
+[ 0.073560] Initializing cgroup subsys devices
+[ 0.078014] Initializing cgroup subsys freezer
+[ 0.082467] Initializing cgroup subsys net_cls
+[ 0.086916] Initializing cgroup subsys blkio
+[ 0.091199] Initializing cgroup subsys perf_event
+[ 0.095906] Initializing cgroup subsys net_prio
+[ 0.100443] Initializing cgroup subsys hugetlb
+[ 0.104914] CPU: Physical Processor ID: 0
+[ 0.108929] CPU: Processor Core ID: 0
+[ 0.112861] mce: CPU supports 9 MCE banks
+[ 0.116890] CPU0: Thermal monitoring enabled (TM1)
+[ 0.121689] Last level iTLB entries: 4KB 512, 2MB 8, 4MB 8
+[ 0.121689] Last level dTLB entries: 4KB 512, 2MB 32, 4MB 32, 1GB 0
+[ 0.121689] tlb_flushall_shift: 2
+[ 0.136821] Freeing SMP alternatives memory: 32K (ffffffff81e6e000 - ffffffff81e76000)
+[ 0.145613] ftrace: allocating 29244 entries in 115 pages
+[ 0.161286] dmar: Host address width 40
+[ 0.165132] dmar: DRHD base: 0x000000fed90000 flags: 0x0
+[ 0.170450] dmar: IOMMU 0: reg_base_addr fed90000 ver 1:0 cap c0000020e60262 ecap f0101a
+[ 0.178546] dmar: DRHD base: 0x000000fed91000 flags: 0x1
+[ 0.183861] dmar: IOMMU 1: reg_base_addr fed91000 ver 1:0 cap c9008020660262 ecap f0105a
+[ 0.192016] IOAPIC id 2 under DRHD base 0xfed91000 IOMMU 1
+[ 0.197587] HPET id 0 under DRHD base 0xfed91000
+[ 0.202200] HPET id 0 under DRHD base 0xfed91000
+[ 0.206813] HPET id 0 under DRHD base 0xfed91000
+[ 0.211424] HPET id 0 under DRHD base 0xfed91000
+[ 0.216037] HPET id 0 under DRHD base 0xfed91000
+[ 0.220652] HPET id 0 under DRHD base 0xfed91000
+[ 0.225264] HPET id 0 under DRHD base 0xfed91000
+[ 0.229877] HPET id 0 under DRHD base 0xfed91000
+[ 0.234489] Queued invalidation will be enabled to support x2apic and Intr-remapping.
+[ 0.242419] Enabled IRQ remapping in x2apic mode
+[ 0.247035] Enabling x2apic
+[ 0.249827] Enabled x2apic
+[ 0.252543] Switched APIC routing to cluster x2apic.
+[ 0.257892] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
+[ 0.303592] smpboot: CPU0: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz (fam: 06, model: 3a, stepping: 09)
+[ 0.312857] TSC deadline timer enabled
+[ 0.312874] Performance Events: PEBS fmt1+, 16-deep LBR, IvyBridge events, full-width counters, Intel PMU driver.
+[ 0.323223] ... version: 3
+[ 0.327232] ... bit width: 48
+[ 0.331332] ... generic registers: 4
+[ 0.335336] ... value mask: 0000ffffffffffff
+[ 0.340643] ... max period: 0000ffffffffffff
+[ 0.345950] ... fixed-purpose events: 3
+[ 0.349955] ... event mask: 000000070000000f
+[ 0.356513] x86: Booting SMP configuration:
+[ 0.360701] .... node #0, CPUs: #1
+[ 0.377986] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter.
+[ 0.386248] #2 #3 #4 #5 #6 #7
+[ 0.469618] x86: Booted up 1 node, 8 CPUs
+[ 0.473818] smpboot: Total of 8 processors activated (54277.56 BogoMIPS)
+[ 0.486889] devtmpfs: initialized
+[ 0.492188] evm: security.selinux
+[ 0.495501] evm: security.SMACK64
+[ 0.498814] evm: security.SMACK64EXEC
+[ 0.502472] evm: security.SMACK64TRANSMUTE
+[ 0.506565] evm: security.SMACK64MMAP
+[ 0.510231] evm: security.ima
+[ 0.513199] evm: security.capability
+[ 0.517430] pinctrl core: initialized pinctrl subsystem
+[ 0.522709] regulator-dummy: no parameters
+[ 0.526832] RTC time: 20:02:44, date: 12/27/15
+[ 0.531315] NET: Registered protocol family 16
+[ 0.535867] cpuidle: using governor ladder
+[ 0.539967] cpuidle: using governor menu
+[ 0.543926] ACPI: bus type PCI registered
+[ 0.547932] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
+[ 0.554412] PCI: Using configuration type 1 for base access
+[ 0.564347] ACPI: Added _OSI(Module Device)
+[ 0.568537] ACPI: Added _OSI(Processor Device)
+[ 0.572982] ACPI: Added _OSI(3.0 _SCP Extensions)
+[ 0.577683] ACPI: Added _OSI(Processor Aggregator Device)
+[ 0.584950] ACPI: Interpreter enabled
+[ 0.588618] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S1_] (20140424/hwxface-580)
+[ 0.597876] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20140424/hwxface-580)
+[ 0.607133] ACPI: (supports S0 S3 S4 S5)
+[ 0.611053] ACPI: Using IOAPIC for interrupt routing
+[ 0.616029] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
+[ 0.626675] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
+[ 0.632856] acpi PNP0A08:00: _OSC: OS supports [ASPM ClockPM Segments MSI]
+[ 0.639740] acpi PNP0A08:00: _OSC: not requesting OS control; OS requires [ExtendedConfig ASPM ClockPM MSI]
+[ 0.649529] acpi PNP0A08:00: fail to add MMCONFIG information, can't access extended PCI configuration space under this bridge.
+[ 0.661083] PCI host bridge to bus 0000:00
+[ 0.665177] pci_bus 0000:00: root bus resource [bus 00-ff]
+[ 0.670664] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7]
+[ 0.676840] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff]
+[ 0.683021] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff]
+[ 0.689889] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000c3fff]
+[ 0.696765] pci_bus 0000:00: root bus resource [mem 0x000c4000-0x000c7fff]
+[ 0.703639] pci_bus 0000:00: root bus resource [mem 0x000c8000-0x000cbfff]
+[ 0.710507] pci_bus 0000:00: root bus resource [mem 0x000cc000-0x000cffff]
+[ 0.717384] pci_bus 0000:00: root bus resource [mem 0x000d0000-0x000d3fff]
+[ 0.724259] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff]
+[ 0.731136] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff]
+[ 0.738011] pci_bus 0000:00: root bus resource [mem 0x000dc000-0x000dffff]
+[ 0.744885] pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000e3fff]
+[ 0.751752] pci_bus 0000:00: root bus resource [mem 0x000e4000-0x000e7fff]
+[ 0.758619] pci_bus 0000:00: root bus resource [mem 0x000e8000-0x000ebfff]
+[ 0.765487] pci_bus 0000:00: root bus resource [mem 0x000ec000-0x000effff]
+[ 0.772356] pci_bus 0000:00: root bus resource [mem 0x000f0000-0x000fffff]
+[ 0.779231] pci_bus 0000:00: root bus resource [mem 0xc2a00000-0xefffffff]
+[ 0.786105] pci_bus 0000:00: root bus resource [mem 0xfed40000-0xfed44fff]
+[ 0.792978] pci 0000:00:00.0: [8086:0150] type 00 class 0x060000
+[ 0.793032] pci 0000:00:01.0: [8086:0151] type 01 class 0x060400
+[ 0.793052] pci 0000:00:01.0: PME# supported from D0 D3hot D3cold
+[ 0.793094] pci 0000:00:02.0: [8086:0162] type 00 class 0x030000
+[ 0.793103] pci 0000:00:02.0: reg 0x10: [mem 0xe0000000-0xe03fffff 64bit]
+[ 0.793108] pci 0000:00:02.0: reg 0x18: [mem 0xd0000000-0xdfffffff 64bit pref]
+[ 0.793111] pci 0000:00:02.0: reg 0x20: [io 0x2000-0x203f]
+[ 0.793179] pci 0000:00:14.0: [8086:1e31] type 00 class 0x0c0330
+[ 0.793198] pci 0000:00:14.0: reg 0x10: [mem 0xe0600000-0xe060ffff 64bit]
+[ 0.793262] pci 0000:00:14.0: PME# supported from D3hot D3cold
+[ 0.793286] pci 0000:00:14.0: System wakeup disabled by ACPI
+[ 0.798978] pci 0000:00:16.0: [8086:1e3a] type 00 class 0x078000
+[ 0.798998] pci 0000:00:16.0: reg 0x10: [mem 0xe0618000-0xe061800f 64bit]
+[ 0.799068] pci 0000:00:16.0: PME# supported from D0 D3hot D3cold
+[ 0.799126] pci 0000:00:1a.0: [8086:1e2d] type 00 class 0x0c0320
+[ 0.799145] pci 0000:00:1a.0: reg 0x10: [mem 0xe0615000-0xe06153ff]
+[ 0.799227] pci 0000:00:1a.0: PME# supported from D0 D3hot D3cold
+[ 0.799251] pci 0000:00:1a.0: System wakeup disabled by ACPI
+[ 0.804942] pci 0000:00:1b.0: [8086:1e20] type 00 class 0x040300
+[ 0.804954] pci 0000:00:1b.0: reg 0x10: [mem 0xe0610000-0xe0613fff 64bit]
+[ 0.805015] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
+[ 0.805038] pci 0000:00:1b.0: System wakeup disabled by ACPI
+[ 0.810724] pci 0000:00:1c.0: [8086:1e10] type 01 class 0x060400
+[ 0.810794] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
+[ 0.810846] pci 0000:00:1c.4: [8086:1e18] type 01 class 0x060400
+[ 0.810915] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold
+[ 0.810972] pci 0000:00:1d.0: [8086:1e26] type 00 class 0x0c0320
+[ 0.810991] pci 0000:00:1d.0: reg 0x10: [mem 0xe0616000-0xe06163ff]
+[ 0.811073] pci 0000:00:1d.0: PME# supported from D0 D3hot D3cold
+[ 0.811097] pci 0000:00:1d.0: System wakeup disabled by ACPI
+[ 0.816781] pci 0000:00:1e.0: [8086:244e] type 01 class 0x060401
+[ 0.816857] pci 0000:00:1f.0: [8086:1e49] type 00 class 0x060100
+[ 0.816997] pci 0000:00:1f.2: [8086:1e02] type 00 class 0x010601
+[ 0.817015] pci 0000:00:1f.2: reg 0x10: [io 0x2060-0x2067]
+[ 0.817022] pci 0000:00:1f.2: reg 0x14: [io 0x2070-0x2073]
+[ 0.817030] pci 0000:00:1f.2: reg 0x18: [io 0x2068-0x206f]
+[ 0.817038] pci 0000:00:1f.2: reg 0x1c: [io 0x2074-0x2077]
+[ 0.817045] pci 0000:00:1f.2: reg 0x20: [io 0x2040-0x205f]
+[ 0.817053] pci 0000:00:1f.2: reg 0x24: [mem 0xe0614000-0xe06147ff]
+[ 0.817097] pci 0000:00:1f.2: PME# supported from D3hot
+[ 0.817141] pci 0000:00:1f.3: [8086:1e22] type 00 class 0x0c0500
+[ 0.817154] pci 0000:00:1f.3: reg 0x10: [mem 0xe0617000-0xe06170ff 64bit]
+[ 0.817172] pci 0000:00:1f.3: reg 0x20: [io 0x0400-0x041f]
+[ 0.817241] pci 0000:00:01.0: PCI bridge to [bus 01]
+[ 0.822266] pci 0000:02:00.0: [1106:3432] type 00 class 0x0c0330
+[ 0.822281] pci 0000:02:00.0: reg 0x10: [mem 0xe0400000-0xe0400fff]
+[ 0.822399] pci 0000:02:00.0: PME# supported from D0 D1 D2 D3hot D3cold
+[ 0.830231] pci 0000:00:1c.0: PCI bridge to [bus 02]
+[ 0.835203] pci 0000:00:1c.0: bridge window [mem 0xe0400000-0xe04fffff]
+[ 0.835273] pci 0000:03:00.0: [10ec:8168] type 00 class 0x020000
+[ 0.835290] pci 0000:03:00.0: reg 0x10: [io 0x1000-0x10ff]
+[ 0.835322] pci 0000:03:00.0: reg 0x18: [mem 0xe0504000-0xe0504fff 64bit pref]
+[ 0.835343] pci 0000:03:00.0: reg 0x20: [mem 0xe0500000-0xe0503fff 64bit pref]
+[ 0.835431] pci 0000:03:00.0: supports D1 D2
+[ 0.835432] pci 0000:03:00.0: PME# supported from D0 D1 D2 D3hot D3cold
+[ 0.843227] pci 0000:00:1c.4: PCI bridge to [bus 03]
+[ 0.848200] pci 0000:00:1c.4: bridge window [io 0x1000-0x1fff]
+[ 0.848207] pci 0000:00:1c.4: bridge window [mem 0xe0500000-0xe05fffff 64bit pref]
+[ 0.848266] pci 0000:00:1e.0: PCI bridge to [bus 04] (subtractive decode)
+[ 0.855062] pci 0000:00:1e.0: bridge window [io 0x0000-0x0cf7] (subtractive decode)
+[ 0.855063] pci 0000:00:1e.0: bridge window [io 0x0d00-0xffff] (subtractive decode)
+[ 0.855064] pci 0000:00:1e.0: bridge window [mem 0x000a0000-0x000bffff] (subtractive decode)
+[ 0.855065] pci 0000:00:1e.0: bridge window [mem 0x000c0000-0x000c3fff] (subtractive decode)
+[ 0.855066] pci 0000:00:1e.0: bridge window [mem 0x000c4000-0x000c7fff] (subtractive decode)
+[ 0.855067] pci 0000:00:1e.0: bridge window [mem 0x000c8000-0x000cbfff] (subtractive decode)
+[ 0.855069] pci 0000:00:1e.0: bridge window [mem 0x000cc000-0x000cffff] (subtractive decode)
+[ 0.855070] pci 0000:00:1e.0: bridge window [mem 0x000d0000-0x000d3fff] (subtractive decode)
+[ 0.855071] pci 0000:00:1e.0: bridge window [mem 0x000d4000-0x000d7fff] (subtractive decode)
+[ 0.855072] pci 0000:00:1e.0: bridge window [mem 0x000d8000-0x000dbfff] (subtractive decode)
+[ 0.855073] pci 0000:00:1e.0: bridge window [mem 0x000dc000-0x000dffff] (subtractive decode)
+[ 0.855074] pci 0000:00:1e.0: bridge window [mem 0x000e0000-0x000e3fff] (subtractive decode)
+[ 0.855075] pci 0000:00:1e.0: bridge window [mem 0x000e4000-0x000e7fff] (subtractive decode)
+[ 0.855076] pci 0000:00:1e.0: bridge window [mem 0x000e8000-0x000ebfff] (subtractive decode)
+[ 0.855077] pci 0000:00:1e.0: bridge window [mem 0x000ec000-0x000effff] (subtractive decode)
+[ 0.855078] pci 0000:00:1e.0: bridge window [mem 0x000f0000-0x000fffff] (subtractive decode)
+[ 0.855079] pci 0000:00:1e.0: bridge window [mem 0xc2a00000-0xefffffff] (subtractive decode)
+[ 0.855080] pci 0000:00:1e.0: bridge window [mem 0xfed40000-0xfed44fff] (subtractive decode)
+[ 0.855154] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 10 12 14 15) *11
+[ 0.862439] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 *11 12 14 15)
+[ 0.869437] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 10 12 14 15) *11
+[ 0.876720] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 *11 12 14 15)
+[ 0.883718] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 10 12 14 15) *11
+[ 0.890991] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 *11 12 14 15)
+[ 0.897989] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 10 12 14 15) *11
+[ 0.905264] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 *11 12 14 15)
+[ 0.912398] vgaarb: setting as boot device: PCI:0000:00:02.0
+[ 0.918055] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
+[ 0.926145] vgaarb: loaded
+[ 0.928856] vgaarb: bridge control possible 0000:00:02.0
+[ 0.934323] SCSI subsystem initialized
+[ 0.938103] libata version 3.00 loaded.
+[ 0.938119] ACPI: bus type USB registered
+[ 0.942145] usbcore: registered new interface driver usbfs
+[ 0.947636] usbcore: registered new interface driver hub
+[ 0.952957] usbcore: registered new device driver usb
+[ 0.958101] PCI: Using ACPI for IRQ routing
+[ 0.962287] PCI: pci_cache_line_size set to 64 bytes
+[ 0.962326] e820: reserve RAM buffer [mem 0x0009fc00-0x0009ffff]
+[ 0.962327] e820: reserve RAM buffer [mem 0xbfe6a000-0xbfffffff]
+[ 0.962328] e820: reserve RAM buffer [mem 0x23b600000-0x23bffffff]
+[ 0.962400] NetLabel: Initializing
+[ 0.965802] NetLabel: domain hash size = 128
+[ 0.970157] NetLabel: protocols = UNLABELED CIPSOv4
+[ 0.975135] NetLabel: unlabeled traffic allowed by default
+[ 0.980751] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
+[ 0.987089] hpet0: 8 comparators, 64-bit 14.318180 MHz counter
+[ 0.994949] Switched to clocksource hpet
+[ 1.002618] AppArmor: AppArmor Filesystem Enabled
+[ 1.007354] pnp: PnP ACPI init
+[ 1.010420] ACPI: bus type PNP registered
+[ 1.014478] system 00:00: [mem 0xfed1c000-0xfed1ffff] has been reserved
+[ 1.021093] system 00:00: [mem 0xfed10000-0xfed17fff] has been reserved
+[ 1.027705] system 00:00: [mem 0xfed18000-0xfed18fff] has been reserved
+[ 1.034322] system 00:00: [mem 0xfed19000-0xfed19fff] has been reserved
+[ 1.040939] system 00:00: [mem 0xf0000000-0xf3ffffff] has been reserved
+[ 1.047555] system 00:00: [mem 0xfed20000-0xfed3ffff] has been reserved
+[ 1.054170] system 00:00: [mem 0xfed40000-0xfed44fff] has been reserved
+[ 1.060786] system 00:00: [mem 0xfed45000-0xfed8ffff] has been reserved
+[ 1.067404] system 00:00: [mem 0x20000000-0x201fffff] could not be reserved
+[ 1.074364] system 00:00: [mem 0x40000000-0x401fffff] could not be reserved
+[ 1.081328] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active)
+[ 1.081456] system 00:01: [mem 0xfed00000-0xfed003ff] has been reserved
+[ 1.088072] system 00:01: Plug and Play ACPI device, IDs PNP0103 PNP0c01 (active)
+[ 1.088098] system 00:02: [io 0x0500-0x057f] could not be reserved
+[ 1.094369] system 00:02: [io 0x0480-0x04bf] has been reserved
+[ 1.100290] system 00:02: Plug and Play ACPI device, IDs PNP0c02 (active)
+[ 1.100305] pnp 00:03: Plug and Play ACPI device, IDs PNP0b00 (active)
+[ 1.100314] pnp: PnP ACPI: found 4 devices
+[ 1.104415] ACPI: bus type PNP unregistered
+[ 1.114559] pci 0000:00:01.0: PCI bridge to [bus 01]
+[ 1.119534] pci 0000:00:1c.0: PCI bridge to [bus 02]
+[ 1.124509] pci 0000:00:1c.0: bridge window [mem 0xe0400000-0xe04fffff]
+[ 1.131299] pci 0000:00:1c.4: PCI bridge to [bus 03]
+[ 1.136263] pci 0000:00:1c.4: bridge window [io 0x1000-0x1fff]
+[ 1.142362] pci 0000:00:1c.4: bridge window [mem 0xe0500000-0xe05fffff 64bit pref]
+[ 1.150105] pci 0000:00:1e.0: PCI bridge to [bus 04]
+[ 1.155077] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7]
+[ 1.155079] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff]
+[ 1.155080] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff]
+[ 1.155081] pci_bus 0000:00: resource 7 [mem 0x000c0000-0x000c3fff]
+[ 1.155082] pci_bus 0000:00: resource 8 [mem 0x000c4000-0x000c7fff]
+[ 1.155083] pci_bus 0000:00: resource 9 [mem 0x000c8000-0x000cbfff]
+[ 1.155084] pci_bus 0000:00: resource 10 [mem 0x000cc000-0x000cffff]
+[ 1.155085] pci_bus 0000:00: resource 11 [mem 0x000d0000-0x000d3fff]
+[ 1.155086] pci_bus 0000:00: resource 12 [mem 0x000d4000-0x000d7fff]
+[ 1.155087] pci_bus 0000:00: resource 13 [mem 0x000d8000-0x000dbfff]
+[ 1.155088] pci_bus 0000:00: resource 14 [mem 0x000dc000-0x000dffff]
+[ 1.155089] pci_bus 0000:00: resource 15 [mem 0x000e0000-0x000e3fff]
+[ 1.155090] pci_bus 0000:00: resource 16 [mem 0x000e4000-0x000e7fff]
+[ 1.155092] pci_bus 0000:00: resource 17 [mem 0x000e8000-0x000ebfff]
+[ 1.155093] pci_bus 0000:00: resource 18 [mem 0x000ec000-0x000effff]
+[ 1.155094] pci_bus 0000:00: resource 19 [mem 0x000f0000-0x000fffff]
+[ 1.155095] pci_bus 0000:00: resource 20 [mem 0xc2a00000-0xefffffff]
+[ 1.155096] pci_bus 0000:00: resource 21 [mem 0xfed40000-0xfed44fff]
+[ 1.155097] pci_bus 0000:02: resource 1 [mem 0xe0400000-0xe04fffff]
+[ 1.155098] pci_bus 0000:03: resource 0 [io 0x1000-0x1fff]
+[ 1.155099] pci_bus 0000:03: resource 2 [mem 0xe0500000-0xe05fffff 64bit pref]
+[ 1.155101] pci_bus 0000:04: resource 4 [io 0x0000-0x0cf7]
+[ 1.155102] pci_bus 0000:04: resource 5 [io 0x0d00-0xffff]
+[ 1.155103] pci_bus 0000:04: resource 6 [mem 0x000a0000-0x000bffff]
+[ 1.155104] pci_bus 0000:04: resource 7 [mem 0x000c0000-0x000c3fff]
+[ 1.155105] pci_bus 0000:04: resource 8 [mem 0x000c4000-0x000c7fff]
+[ 1.155106] pci_bus 0000:04: resource 9 [mem 0x000c8000-0x000cbfff]
+[ 1.155107] pci_bus 0000:04: resource 10 [mem 0x000cc000-0x000cffff]
+[ 1.155108] pci_bus 0000:04: resource 11 [mem 0x000d0000-0x000d3fff]
+[ 1.155109] pci_bus 0000:04: resource 12 [mem 0x000d4000-0x000d7fff]
+[ 1.155110] pci_bus 0000:04: resource 13 [mem 0x000d8000-0x000dbfff]
+[ 1.155111] pci_bus 0000:04: resource 14 [mem 0x000dc000-0x000dffff]
+[ 1.155112] pci_bus 0000:04: resource 15 [mem 0x000e0000-0x000e3fff]
+[ 1.155113] pci_bus 0000:04: resource 16 [mem 0x000e4000-0x000e7fff]
+[ 1.155114] pci_bus 0000:04: resource 17 [mem 0x000e8000-0x000ebfff]
+[ 1.155115] pci_bus 0000:04: resource 18 [mem 0x000ec000-0x000effff]
+[ 1.155116] pci_bus 0000:04: resource 19 [mem 0x000f0000-0x000fffff]
+[ 1.155118] pci_bus 0000:04: resource 20 [mem 0xc2a00000-0xefffffff]
+[ 1.155119] pci_bus 0000:04: resource 21 [mem 0xfed40000-0xfed44fff]
+[ 1.155137] NET: Registered protocol family 2
+[ 1.159629] TCP established hash table entries: 65536 (order: 7, 524288 bytes)
+[ 1.166957] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
+[ 1.173772] TCP: Hash tables configured (established 65536 bind 65536)
+[ 1.180310] TCP: reno registered
+[ 1.183550] UDP hash table entries: 4096 (order: 5, 131072 bytes)
+[ 1.189671] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes)
+[ 1.196243] NET: Registered protocol family 1
+[ 1.200610] pci 0000:00:02.0: Video device with shadowed ROM
+[ 1.201358] PCI: CLS 64 bytes, default 64
+[ 1.201398] Trying to unpack rootfs image as initramfs...
+[ 1.521529] Freeing initrd memory: 28740K (ffff8800347ce000 - ffff8800363df000)
+[ 1.528892] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
+[ 1.535341] software IO TLB [mem 0xbbe6a000-0xbfe6a000] (64MB) mapped at [ffff8800bbe6a000-ffff8800bfe69fff]
+[ 1.545422] RAPL PMU detected, hw unit 2^-16 Joules, API unit is 2^-32 Joules, 3 fixed counters 163840 ms ovfl timer
+[ 1.555988] microcode: CPU0 sig=0x306a9, pf=0x2, revision=0x1b
+[ 1.561836] microcode: CPU1 sig=0x306a9, pf=0x2, revision=0x1b
+[ 1.567673] microcode: CPU2 sig=0x306a9, pf=0x2, revision=0x1b
+[ 1.573505] microcode: CPU3 sig=0x306a9, pf=0x2, revision=0x1b
+[ 1.579340] microcode: CPU4 sig=0x306a9, pf=0x2, revision=0x1b
+[ 1.585175] microcode: CPU5 sig=0x306a9, pf=0x2, revision=0x1b
+[ 1.591010] microcode: CPU6 sig=0x306a9, pf=0x2, revision=0x1b
+[ 1.596847] microcode: CPU7 sig=0x306a9, pf=0x2, revision=0x1b
+[ 1.602715] microcode: Microcode Update Driver: v2.00 <tigran@aivazian.fsnet.co.uk>, Peter Oruba
+[ 1.611520] Scanning for low memory corruption every 60 seconds
+[ 1.617676] futex hash table entries: 2048 (order: 5, 131072 bytes)
+[ 1.623966] Initialise system trusted keyring
+[ 1.628352] audit: initializing netlink subsys (disabled)
+[ 1.633771] audit: type=2000 audit(1451246564.320:1): initialized
+[ 1.640091] HugeTLB registered 2 MB page size, pre-allocated 0 pages
+[ 1.647394] zpool: loaded
+[ 1.650019] zbud: loaded
+[ 1.652673] VFS: Disk quotas dquot_6.5.2
+[ 1.656627] Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
+[ 1.663386] fuse init (API version 7.23)
+[ 1.667370] msgmni has been set to 15813
+[ 1.671339] Key type big_key registered
+[ 1.675528] Key type asymmetric registered
+[ 1.679638] Asymmetric key parser 'x509' registered
+[ 1.684559] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252)
+[ 1.692001] io scheduler noop registered
+[ 1.695928] io scheduler deadline registered (default)
+[ 1.701099] io scheduler cfq registered
+[ 1.705051] pcieport 0000:00:01.0: can't derive routing for PCI INT A
+[ 1.711499] pcieport 0000:00:01.0: PCI INT A: no GSI
+[ 1.716606] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
+[ 1.722190] pciehp: PCI Express Hot Plug Controller Driver version: 0.4
+[ 1.728844] intel_idle: MWAIT substates: 0x1120
+[ 1.728845] intel_idle: v0.4 model 0x3A
+[ 1.728845] intel_idle: lapic_timer_reliable_states 0xffffffff
+[ 1.729076] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input0
+[ 1.736472] ACPI: Power Button [PWRF]
+[ 1.740698] GHES: HEST is not enabled!
+[ 1.744529] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled
+[ 1.771296] serial8250: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
+[ 1.780090] Linux agpgart interface v0.103
+[ 1.785037] brd: module loaded
+[ 1.788517] loop: module loaded
+[ 1.791817] libphy: Fixed MDIO Bus: probed
+[ 1.795919] tun: Universal TUN/TAP device driver, 1.6
+[ 1.800971] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
+[ 1.807214] PPP generic driver version 2.4.2
+[ 1.811529] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
+[ 1.818066] ehci-pci: EHCI PCI platform driver
+[ 1.822585] ehci-pci 0000:00:1a.0: EHCI Host Controller
+[ 1.827818] ehci-pci 0000:00:1a.0: new USB bus registered, assigned bus number 1
+[ 1.835221] ehci-pci 0000:00:1a.0: debug port 2
+[ 1.843646] ehci-pci 0000:00:1a.0: cache line size of 64 is not supported
+[ 1.843659] ehci-pci 0000:00:1a.0: irq 21, io mem 0xe0615000
+[ 1.859370] ehci-pci 0000:00:1a.0: USB 2.0 started, EHCI 1.00
+[ 1.865146] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
+[ 1.871939] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
+[ 1.879162] usb usb1: Product: EHCI Host Controller
+[ 1.884043] usb usb1: Manufacturer: Linux 3.16.0-38-generic ehci_hcd
+[ 1.890398] usb usb1: SerialNumber: 0000:00:1a.0
+[ 1.895159] hub 1-0:1.0: USB hub found
+[ 1.898921] hub 1-0:1.0: 3 ports detected
+[ 1.903092] ehci-pci 0000:00:1d.0: EHCI Host Controller
+[ 1.908324] ehci-pci 0000:00:1d.0: new USB bus registered, assigned bus number 2
+[ 1.915727] ehci-pci 0000:00:1d.0: debug port 2
+[ 1.924158] ehci-pci 0000:00:1d.0: cache line size of 64 is not supported
+[ 1.924168] ehci-pci 0000:00:1d.0: irq 19, io mem 0xe0616000
+[ 1.939425] ehci-pci 0000:00:1d.0: USB 2.0 started, EHCI 1.00
+[ 1.945215] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002
+[ 1.952004] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
+[ 1.959225] usb usb2: Product: EHCI Host Controller
+[ 1.964104] usb usb2: Manufacturer: Linux 3.16.0-38-generic ehci_hcd
+[ 1.970463] usb usb2: SerialNumber: 0000:00:1d.0
+[ 1.975233] hub 2-0:1.0: USB hub found
+[ 1.978993] hub 2-0:1.0: 3 ports detected
+[ 1.983094] ehci-platform: EHCI generic platform driver
+[ 1.988329] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
+[ 1.994518] ohci-pci: OHCI PCI platform driver
+[ 1.998968] ohci-platform: OHCI generic platform driver
+[ 2.004210] uhci_hcd: USB Universal Host Controller Interface driver
+[ 2.010636] xhci_hcd 0000:00:14.0: xHCI Host Controller
+[ 2.015865] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 3
+[ 2.023343] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported
+[ 2.023362] xhci_hcd 0000:00:14.0: irq 42 for MSI/MSI-X
+[ 2.023406] usb usb3: New USB device found, idVendor=1d6b, idProduct=0002
+[ 2.030196] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
+[ 2.037415] usb usb3: Product: xHCI Host Controller
+[ 2.042299] usb usb3: Manufacturer: Linux 3.16.0-38-generic xhci_hcd
+[ 2.048653] usb usb3: SerialNumber: 0000:00:14.0
+[ 2.053410] hub 3-0:1.0: USB hub found
+[ 2.057179] hub 3-0:1.0: 4 ports detected
+[ 2.061269] xhci_hcd 0000:00:14.0: xHCI Host Controller
+[ 2.066500] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 4
+[ 2.073921] usb usb4: New USB device found, idVendor=1d6b, idProduct=0003
+[ 2.080713] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
+[ 2.087934] usb usb4: Product: xHCI Host Controller
+[ 2.092813] usb usb4: Manufacturer: Linux 3.16.0-38-generic xhci_hcd
+[ 2.099168] usb usb4: SerialNumber: 0000:00:14.0
+[ 2.103924] hub 4-0:1.0: USB hub found
+[ 2.107696] hub 4-0:1.0: 4 ports detected
+[ 2.111915] xhci_hcd 0000:02:00.0: xHCI Host Controller
+[ 2.117146] xhci_hcd 0000:02:00.0: new USB bus registered, assigned bus number 5
+[ 2.124674] xhci_hcd 0000:02:00.0: irq 43 for MSI/MSI-X
+[ 2.124726] usb usb5: New USB device found, idVendor=1d6b, idProduct=0002
+[ 2.131511] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
+[ 2.138735] usb usb5: Product: xHCI Host Controller
+[ 2.143614] usb usb5: Manufacturer: Linux 3.16.0-38-generic xhci_hcd
+[ 2.149971] usb usb5: SerialNumber: 0000:02:00.0
+[ 2.154720] hub 5-0:1.0: USB hub found
+[ 2.158485] hub 5-0:1.0: 1 port detected
+[ 2.162462] xhci_hcd 0000:02:00.0: xHCI Host Controller
+[ 2.167695] xhci_hcd 0000:02:00.0: new USB bus registered, assigned bus number 6
+[ 2.175125] usb usb6: New USB device found, idVendor=1d6b, idProduct=0003
+[ 2.181912] usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1
+[ 2.189137] usb usb6: Product: xHCI Host Controller
+[ 2.194017] usb usb6: Manufacturer: Linux 3.16.0-38-generic xhci_hcd
+[ 2.200376] usb usb6: SerialNumber: 0000:02:00.0
+[ 2.205151] hub 6-0:1.0: USB hub found
+[ 2.208916] hub 6-0:1.0: 4 ports detected
+[ 2.213037] i8042: PNP: No PS/2 controller found. Probing ports directly.
+[ 2.215546] usb 1-1: new high-speed USB device number 2 using ehci-pci
+[ 2.226807] serio: i8042 KBD port at 0x60,0x64 irq 1
+[ 2.231783] serio: i8042 AUX port at 0x60,0x64 irq 12
+[ 2.237045] mousedev: PS/2 mouse device common for all mice
+[ 2.242899] rtc_cmos 00:03: RTC can wake from S4
+[ 2.247666] rtc_cmos 00:03: rtc core: registered rtc_cmos as rtc0
+[ 2.253793] rtc_cmos 00:03: alarms up to one month, 242 bytes nvram, hpet irqs
+[ 2.261055] device-mapper: uevent: version 1.0.3
+[ 2.265758] device-mapper: ioctl: 4.27.0-ioctl (2013-10-30) initialised: dm-devel@redhat.com
+[ 2.274216] Intel P-state driver initializing.
+[ 2.278678] Intel pstate controlling: cpu 0
+[ 2.282898] Intel pstate controlling: cpu 1
+[ 2.287243] Intel pstate controlling: cpu 2
+[ 2.291466] Intel pstate controlling: cpu 3
+[ 2.295689] Intel pstate controlling: cpu 4
+[ 2.299908] Intel pstate controlling: cpu 5
+[ 2.304151] Intel pstate controlling: cpu 6
+[ 2.308379] Intel pstate controlling: cpu 7
+[ 2.312583] Consider also installing thermald for improved thermal control.
+[ 2.319544] ledtrig-cpu: registered to indicate activity on CPUs
+[ 2.325612] TCP: cubic registered
+[ 2.328993] NET: Registered protocol family 10
+[ 2.333662] NET: Registered protocol family 17
+[ 2.338123] Key type dns_resolver registered
+[ 2.342973] Loading compiled-in X.509 certificates
+[ 2.348287] Loaded X.509 cert 'Magrathea: Glacier signing key: c284edaccf0b473652c34d23bec356944236e63b'
+[ 2.357772] registered taskstats version 1
+[ 2.359966] usb 1-1: New USB device found, idVendor=8087, idProduct=0024
+[ 2.359967] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
+[ 2.360111] hub 1-1:1.0: USB hub found
+[ 2.360218] hub 1-1:1.0: 6 ports detected
+[ 2.385367] Key type trusted registered
+[ 2.392195] Key type encrypted registered
+[ 2.396227] AppArmor: AppArmor sha1 policy hashing enabled
+[ 2.401725] ima: No TPM chip found, activating TPM-bypass!
+[ 2.407239] evm: HMAC attrs: 0x1
+[ 2.410871] Magic number: 11:151:44
+[ 2.414661] rtc_cmos 00:03: setting system clock to 2015-12-27 20:02:46 UTC (1451246566)
+[ 2.422926] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found
+[ 2.428943] EDD information not available.
+[ 2.433068] PM: Hibernation image not present or could not be loaded.
+[ 2.433783] Freeing unused kernel memory: 1352K (ffffffff81d1c000 - ffffffff81e6e000)
+[ 2.441627] Write protecting the kernel read-only data: 12288k
+[ 2.448489] Freeing unused kernel memory: 556K (ffff880001775000 - ffff880001800000)
+[ 2.457123] Freeing unused kernel memory: 500K (ffff880001b83000 - ffff880001c00000)
+[ 2.471671] usb 2-1: new high-speed USB device number 2 using ehci-pci
+[ 2.479859] systemd-udevd[145]: starting version 204
+[ 2.493096] ahci 0000:00:1f.2: version 3.0
+[ 2.493192] ahci 0000:00:1f.2: irq 44 for MSI/MSI-X
+[ 2.493207] ahci 0000:00:1f.2: SSS flag set, parallel bus scan disabled
+[ 2.500084] r8169 Gigabit Ethernet driver 2.3LK-NAPI loaded
+[ 2.506634] [drm] Initialized drm 1.1.0 20060810
+[ 2.506741] r8169 0000:03:00.0: irq 45 for MSI/MSI-X
+[ 2.506920] r8169 0000:03:00.0 eth0: RTL8168evl/8111evl at 0xffffc90000e74000, 40:8d:5c:57:3e:d7, XID 0c900800 IRQ 45
+[ 2.506921] r8169 0000:03:00.0 eth0: jumbo features [frames: 9200 bytes, tx checksumming: ko]
+[ 2.515731] ahci 0000:00:1f.2: AHCI 0001.0300 32 slots 6 ports 6 Gbps 0x3f impl SATA mode
+[ 2.515733] ahci 0000:00:1f.2: flags: 64bit ncq sntf ilck stag pm led clo pio slum part apst
+[ 2.516388] scsi0 : ahci
+[ 2.516526] scsi1 : ahci
+[ 2.516650] scsi2 : ahci
+[ 2.516760] scsi3 : ahci
+[ 2.516873] scsi4 : ahci
+[ 2.516984] scsi5 : ahci
+[ 2.517023] ata1: SATA max UDMA/133 abar m2048@0xe0614000 port 0xe0614100 irq 44
+[ 2.517025] ata2: SATA max UDMA/133 abar m2048@0xe0614000 port 0xe0614180 irq 44
+[ 2.517026] ata3: SATA max UDMA/133 abar m2048@0xe0614000 port 0xe0614200 irq 44
+[ 2.517029] ata4: SATA max UDMA/133 abar m2048@0xe0614000 port 0xe0614280 irq 44
+[ 2.517032] ata5: SATA max UDMA/133 abar m2048@0xe0614000 port 0xe0614300 irq 44
+[ 2.517035] ata6: SATA max UDMA/133 abar m2048@0xe0614000 port 0xe0614380 irq 44
+[ 2.543685] tsc: Refined TSC clocksource calibration: 3392.291 MHz
+[ 2.608077] usb 2-1: New USB device found, idVendor=8087, idProduct=0024
+[ 2.608078] usb 2-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0
+[ 2.608367] hub 2-1:1.0: USB hub found
+[ 2.608455] hub 2-1:1.0: 6 ports detected
+[ 2.645104] [drm] Memory usable by graphics device = 2048M
+[ 2.650624] [drm] Replacing VGA console driver
+[ 2.715828] i915 0000:00:02.0: irq 46 for MSI/MSI-X
+[ 2.715842] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
+[ 2.719803] usb 5-1: new high-speed USB device number 2 using xhci_hcd
+[ 2.729056] [drm] Driver supports precise vblank timestamp query.
+[ 2.735195] i915 0000:00:02.0: Invalid ROM contents
+[ 2.740104] [drm] failed to find VBIOS tables
+[ 2.744501] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
+[ 2.836401] fbcon: inteldrmfb (fb0) is primary device
+[ 2.839061] Console: switching to colour frame buffer device 180x56
+[ 2.843855] ata1: SATA link down (SStatus 0 SControl 300)
+[ 2.852453] usb 5-1: New USB device found, idVendor=2109, idProduct=0811
+[ 2.852454] usb 5-1: New USB device strings: Mfr=0, Product=1, SerialNumber=0
+[ 2.852455] usb 5-1: Product: USB2.0 Hub
+[ 2.852943] hub 5-1:1.0: USB hub found
+[ 2.853082] hub 5-1:1.0: 4 ports detected
+[ 2.883498] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
+[ 2.889710] i915 0000:00:02.0: registered panic notifier
+[ 2.900026] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no)
+[ 2.924053] acpi device:03: registered as cooling_device8
+[ 2.929555] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input5
+[ 2.931981] usb 1-1.5: new low-speed USB device number 3 using ehci-pci
+[ 2.945484] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0
+[ 3.032316] usb 1-1.5: New USB device found, idVendor=03f0, idProduct=0324
+[ 3.039226] usb 1-1.5: New USB device strings: Mfr=1, Product=2, SerialNumber=0
+[ 3.046583] usb 1-1.5: Product: HP Basic USB Keyboard
+[ 3.051666] usb 1-1.5: Manufacturer: Lite-On Technology Corp.
+[ 3.060128] hidraw: raw HID events driver (C) Jiri Kosina
+[ 3.069845] usbcore: registered new interface driver usbhid
+[ 3.075454] usbhid: USB HID core driver
+[ 3.080372] input: Lite-On Technology Corp. HP Basic USB Keyboard as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.5/1-1.5:1.0/0003:03F0:0324.0001/input/input6
+[ 3.094806] hid-generic 0003:03F0:0324.0001: input,hidraw0: USB HID v1.10 Keyboard [Lite-On Technology Corp. HP Basic USB Keyboard] on usb-0000:00:1a.0-1.5/input0
+[ 3.128198] usb 1-1.6: new low-speed USB device number 4 using ehci-pci
+[ 3.163998] ata2: SATA link down (SStatus 0 SControl 300)
+[ 3.229154] usb 1-1.6: New USB device found, idVendor=046d, idProduct=c402
+[ 3.236085] usb 1-1.6: New USB device strings: Mfr=1, Product=2, SerialNumber=0
+[ 3.243458] usb 1-1.6: Product: Trackball
+[ 3.247504] usb 1-1.6: Manufacturer: Logitech
+[ 3.254860] input: Logitech Trackball as /devices/pci0000:00/0000:00:1a.0/usb1/1-1/1-1.6/1-1.6:1.0/0003:046D:C402.0002/input/input7
+[ 3.267070] hid-generic 0003:046D:C402.0002: input,hidraw1: USB HID v1.10 Mouse [Logitech Trackball] on usb-0000:00:1a.0-1.6/input0
+[ 3.352199] usb 2-1.3: new high-speed USB device number 3 using ehci-pci
+[ 3.453790] usb 2-1.3: New USB device found, idVendor=0781, idProduct=5580
+[ 3.461513] usb 2-1.3: New USB device strings: Mfr=1, Product=2, SerialNumber=3
+[ 3.469653] usb 2-1.3: Product: Extreme
+[ 3.474346] usb 2-1.3: Manufacturer: SanDisk
+[ 3.479417] usb 2-1.3: SerialNumber: AA010605140138082427
+[ 3.487662] usb-storage 2-1.3:1.0: USB Mass Storage device detected
+[ 3.494917] scsi6 : usb-storage 2-1.3:1.0
+[ 3.496168] ata3: SATA link down (SStatus 0 SControl 300)
+[ 3.505968] usbcore: registered new interface driver usb-storage
+[ 3.513674] usbcore: registered new interface driver uas
+[ 3.544191] Switched to clocksource tsc
+[ 3.816271] ata4: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
+[ 3.823646] ata4.00: ATAPI: ASUS BC-12B1ST, 1.01, max UDMA/100
+[ 3.831142] ata4.00: configured for UDMA/100
+[ 3.838825] scsi 3:0:0:0: CD-ROM ASUS BC-12B1ST 1.01 PQ: 0 ANSI: 5
+[ 3.861805] sr0: scsi3-mmc drive: 48x/48x writer dvd-ram cd/rw xa/form2 cdda tray
+[ 3.870109] cdrom: Uniform CD-ROM driver Revision: 3.20
+[ 3.876335] sr 3:0:0:0: Attached scsi CD-ROM sr0
+[ 3.876467] sr 3:0:0:0: Attached scsi generic sg0 type 5
+[ 4.084756] [drm] Enabling RC6 states: RC6 on, RC6p on, RC6pp off
+[ 4.200464] ata5: SATA link down (SStatus 0 SControl 300)
+[ 4.505352] scsi 6:0:0:0: Direct-Access SanDisk Extreme 0001 PQ: 0 ANSI: 6
+[ 4.514465] sd 6:0:0:0: Attached scsi generic sg1 type 0
+[ 4.515096] sd 6:0:0:0: [sda] 31277232 512-byte logical blocks: (16.0 GB/14.9 GiB)
+[ 4.516094] sd 6:0:0:0: [sda] Write Protect is off
+[ 4.516095] sd 6:0:0:0: [sda] Mode Sense: 33 00 00 08
+[ 4.517094] sd 6:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
+[ 4.524605] ata6: SATA link down (SStatus 0 SControl 300)
+[ 4.526850] sda: sda1 sda2 < sda5 >
+[ 4.531984] sd 6:0:0:0: [sda] Attached SCSI disk
+[ 4.821746] EXT4-fs (sda1): INFO: recovery required on readonly filesystem
+[ 4.828683] EXT4-fs (sda1): write access will be enabled during recovery
+[ 4.857221] EXT4-fs (sda1): recovery complete
+[ 4.863486] EXT4-fs (sda1): mounted filesystem with ordered data mode. Opts: (null)
+[ 5.157802] random: init urandom read with 91 bits of entropy available
+[ 6.526014] random: nonblocking pool is initialized
+[ 12.517757] Adding 1047548k swap on /dev/sda5. Priority:-1 extents:1 across:1047548k FS
+[ 12.592041] systemd-udevd[422]: starting version 204
+[ 12.616182] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
+[ 12.618038] lp: driver loaded but no devices found
+[ 12.627164] ACPI Warning: SystemIO range 0x0000000000000528-0x000000000000052f conflicts with OpRegion 0x0000000000000500-0x000000000000057f (\PMIO) (20140424/utaddress-258)
+[ 12.627171] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
+[ 12.627175] ACPI Warning: SystemIO range 0x00000000000004c0-0x00000000000004cf conflicts with OpRegion 0x0000000000000480-0x00000000000004eb (\GPIO) (20140424/utaddress-258)
+[ 12.627178] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
+[ 12.627179] ACPI Warning: SystemIO range 0x00000000000004b0-0x00000000000004bf conflicts with OpRegion 0x0000000000000480-0x00000000000004eb (\GPIO) (20140424/utaddress-258)
+[ 12.627182] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
+[ 12.627183] ACPI Warning: SystemIO range 0x0000000000000480-0x00000000000004af conflicts with OpRegion 0x0000000000000480-0x00000000000004eb (\GPIO) (20140424/utaddress-258)
+[ 12.627185] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver
+[ 12.627186] lpc_ich: Resource conflict(s) found affecting gpio_ich
+[ 12.628465] ppdev: user-space parallel port driver
+[ 12.634837] mei_me 0000:00:16.0: irq 47 for MSI/MSI-X
+[ 12.643521] AVX version of gcm_enc/dec engaged.
+[ 12.668446] intel_rapl: Found RAPL domain package
+[ 12.668449] intel_rapl: Found RAPL domain core
+[ 12.668450] intel_rapl: Found RAPL domain uncore
+[ 12.669309] device-mapper: multipath: version 1.7.0 loaded
+[ 12.683451] WARNING! power/level is deprecated; use power/control instead
+[ 12.768468] systemd-udevd[442]: renamed network interface eth0 to eth5
+[ 12.857689] snd_hda_intel 0000:00:1b.0: irq 48 for MSI/MSI-X
+[ 12.885909] sound hdaudioC0D2: autoconfig: line_outs=4 (0x14/0x16/0x15/0x17/0x0) type:line
+[ 12.885911] sound hdaudioC0D2: speaker_outs=0 (0x0/0x0/0x0/0x0/0x0)
+[ 12.885912] sound hdaudioC0D2: hp_outs=1 (0x1b/0x0/0x0/0x0/0x0)
+[ 12.885913] sound hdaudioC0D2: mono: mono_out=0x0
+[ 12.885914] sound hdaudioC0D2: dig-out=0x1e/0x0
+[ 12.885914] sound hdaudioC0D2: inputs:
+[ 12.885916] sound hdaudioC0D2: Rear Mic=0x18
+[ 12.885917] sound hdaudioC0D2: Front Mic=0x19
+[ 12.885918] sound hdaudioC0D2: Line=0x1a
+[ 12.885919] sound hdaudioC0D2: CD=0x1c
+[ 12.908333] input: HDA Intel PCH Rear Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input8
+[ 12.908407] input: HDA Intel PCH Front Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input9
+[ 12.908468] input: HDA Intel PCH Line as /devices/pci0000:00/0000:00:1b.0/sound/card0/input10
+[ 12.908564] input: HDA Intel PCH Line Out Front as /devices/pci0000:00/0000:00:1b.0/sound/card0/input11
+[ 12.909031] input: HDA Intel PCH Line Out Surround as /devices/pci0000:00/0000:00:1b.0/sound/card0/input12
+[ 12.909111] input: HDA Intel PCH Line Out CLFE as /devices/pci0000:00/0000:00:1b.0/sound/card0/input13
+[ 12.909200] input: HDA Intel PCH Line Out Side as /devices/pci0000:00/0000:00:1b.0/sound/card0/input14
+[ 12.909314] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1b.0/sound/card0/input15
+[ 12.909409] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:1b.0/sound/card0/input16
+[ 12.909503] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:1b.0/sound/card0/input17
+[ 13.166506] EXT4-fs (sda1): re-mounted. Opts: errors=remount-ro
+[ 13.340202] init: failsafe main process (770) killed by TERM signal
+[ 13.571085] Bluetooth: Core ver 2.19
+[ 13.571098] NET: Registered protocol family 31
+[ 13.571099] Bluetooth: HCI device and connection manager initialized
+[ 13.571105] Bluetooth: HCI socket layer initialized
+[ 13.571107] Bluetooth: L2CAP socket layer initialized
+[ 13.571114] Bluetooth: SCO socket layer initialized
+[ 13.579203] Bluetooth: RFCOMM TTY layer initialized
+[ 13.579209] Bluetooth: RFCOMM socket layer initialized
+[ 13.579212] Bluetooth: RFCOMM ver 1.11
+[ 13.587546] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
+[ 13.587547] Bluetooth: BNEP filters: protocol multicast
+[ 13.587552] Bluetooth: BNEP socket layer initialized
+[ 13.686165] init: cups main process (894) killed by HUP signal
+[ 13.686169] init: cups main process ended, respawning
+[ 14.130115] init: alsa-restore main process (1028) terminated with status 99
+[ 14.288178] init: samba-ad-dc main process (989) terminated with status 1
+[ 14.463266] r8169 0000:03:00.0 eth5: link down
+[ 14.463284] r8169 0000:03:00.0 eth5: link down
+[ 14.463314] IPv6: ADDRCONF(NETDEV_UP): eth5: link is not ready
+[ 14.736422] init: plymouth-upstart-bridge main process ended, respawning
+[ 15.493803] init: plymouth-stop pre-start process (1530) terminated with status 1
+[ 16.115610] r8169 0000:03:00.0 eth5: link up
+[ 16.115618] IPv6: ADDRCONF(NETDEV_CHANGE): eth5: link becomes ready
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/payload_config.txt b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/payload_config.txt
new file mode 100644
index 0000000..9f6bb3d
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/payload_config.txt
@@ -0,0 +1,91 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# SeaBIOS Configuration
+#
+
+#
+# General Features
+#
+CONFIG_COREBOOT=y
+# CONFIG_QEMU is not set
+# CONFIG_CSM is not set
+# CONFIG_QEMU_HARDWARE is not set
+CONFIG_THREADS=y
+CONFIG_RELOCATE_INIT=y
+CONFIG_BOOTMENU=y
+CONFIG_BOOTSPLASH=y
+CONFIG_BOOTORDER=y
+CONFIG_COREBOOT_FLASH=y
+CONFIG_LZMA=y
+CONFIG_CBFS_LOCATION=0
+CONFIG_MULTIBOOT=y
+CONFIG_ENTRY_EXTRASTACK=y
+CONFIG_MALLOC_UPPERMEMORY=y
+CONFIG_ROM_SIZE=0
+
+#
+# Hardware support
+#
+CONFIG_ATA=y
+# CONFIG_ATA_DMA is not set
+# CONFIG_ATA_PIO32 is not set
+CONFIG_AHCI=y
+CONFIG_SDCARD=y
+CONFIG_MEGASAS=y
+CONFIG_FLOPPY=y
+CONFIG_FLASH_FLOPPY=y
+CONFIG_PS2PORT=y
+CONFIG_USB=y
+CONFIG_USB_UHCI=y
+CONFIG_USB_OHCI=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_XHCI=y
+CONFIG_USB_MSC=y
+CONFIG_USB_UAS=y
+CONFIG_USB_HUB=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_USB_MOUSE=y
+CONFIG_SERIAL=y
+CONFIG_LPT=y
+CONFIG_RTC_TIMER=y
+CONFIG_HARDWARE_IRQ=y
+CONFIG_PMTIMER=y
+CONFIG_TSC_TIMER=y
+
+#
+# BIOS interfaces
+#
+CONFIG_DRIVES=y
+CONFIG_CDROM_BOOT=y
+CONFIG_CDROM_EMU=y
+CONFIG_PCIBIOS=y
+CONFIG_APMBIOS=y
+CONFIG_PNPBIOS=y
+CONFIG_OPTIONROMS=y
+CONFIG_PMM=y
+CONFIG_BOOT=y
+CONFIG_KEYBOARD=y
+CONFIG_KBD_CALL_INT15_4F=y
+CONFIG_MOUSE=y
+CONFIG_S3_RESUME=y
+CONFIG_VGAHOOKS=y
+# CONFIG_DISABLE_A20 is not set
+CONFIG_TCGBIOS=y
+
+#
+# VGA ROM
+#
+CONFIG_NO_VGABIOS=y
+# CONFIG_VGA_GEODEGX2 is not set
+# CONFIG_VGA_GEODELX is not set
+# CONFIG_VGA_COREBOOT is not set
+# CONFIG_BUILD_VGABIOS is not set
+CONFIG_VGA_EXTRA_STACK_SIZE=512
+
+#
+# Debugging
+#
+CONFIG_DEBUG_LEVEL=1
+CONFIG_DEBUG_SERIAL=y
+CONFIG_DEBUG_SERIAL_PORT=0x3f8
+CONFIG_DEBUG_COREBOOT=y
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/revision.txt b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/revision.txt
new file mode 100644
index 0000000..e5d0730
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/revision.txt
@@ -0,0 +1,5 @@
+Local revision: d890b45
+Tagged revision: 4.2-619-gd890b45
+Upstream revision: d890b45
+Upstream URL: review.coreboot.org:29418/coreboot
+Timestamp: 2015-12-26T19:53:49Z
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/acpidump.err.log b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/acpidump.err.log
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/acpidump.err.log
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/acpidump.log b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/acpidump.log
new file mode 100644
index 0000000..25b88d1
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/acpidump.log
@@ -0,0 +1,1326 @@
+RSD @ 0x00000000000F0900
+ 0000: 52 53 44 20 50 54 52 20 0C 43 4F 52 45 20 20 02 RSD PTR .CORE .
+ 0010: 30 90 EB BF 24 00 00 00 E0 90 EB BF 00 00 00 00 0...$...........
+ 0020: C2 00 00 00 ....
+
+RSDT @ 0x00000000BFEB9030
+ 0000: 52 53 44 54 3C 00 00 00 01 F4 43 4F 52 45 20 20 RSDT<.....CORE
+ 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 COREBOOT....CORE
+ 0020: 00 00 00 00 B0 B8 EB BF B0 B9 EB BF 30 E1 EB BF ............0...
+ 0030: 70 E1 EB BF 00 E2 EB BF B0 E2 EB BF p...........
+
+XSDT @ 0x00000000BFEB90E0
+ 0000: 58 53 44 54 54 00 00 00 01 D6 43 4F 52 45 20 20 XSDTT.....CORE
+ 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 COREBOOT....CORE
+ 0020: 00 00 00 00 B0 B8 EB BF 00 00 00 00 B0 B9 EB BF ................
+ 0030: 00 00 00 00 30 E1 EB BF 00 00 00 00 70 E1 EB BF ....0.......p...
+ 0040: 00 00 00 00 00 E2 EB BF 00 00 00 00 B0 E2 EB BF ................
+ 0050: 00 00 00 00 ....
+
+DSDT @ 0x00000000BFEB9280
+ 0000: 44 53 44 54 2C 26 00 00 03 92 43 4F 52 45 76 34 DSDT,&....COREv4
+ 0010: 43 4F 52 45 42 4F 4F 54 18 10 14 20 49 4E 54 4C COREBOOT... INTL
+ 0020: 19 06 15 20 10 8F 00 00 5C 00 08 4E 56 53 41 0C ... ....\..NVSA.
+ 0030: 00 80 EB BF 5B 80 41 50 4D 50 01 0A B2 0A 02 5B ....[.APMP.....[
+ 0040: 81 10 41 50 4D 50 01 41 50 4D 43 08 41 50 4D 53 ..APMP.APMC.APMS
+ 0050: 08 5B 80 50 4F 53 54 01 0A 80 01 5B 81 0B 50 4F .[.POST....[..PO
+ 0060: 53 54 11 44 42 47 30 08 14 17 54 52 41 50 09 70 ST.DBG0...TRAP.p
+ 0070: 68 53 4D 49 46 70 00 54 52 50 30 A4 53 4D 49 46 hSMIFp.TRP0.SMIF
+ 0080: 14 0C 5F 50 49 43 01 70 68 50 49 43 4D 14 06 5F .._PIC.phPICM.._
+ 0090: 50 54 53 01 14 0C 5F 57 41 4B 01 A4 12 04 02 00 PTS..._WAK......
+ 00A0: 00 14 4D 08 50 4E 4F 54 00 A0 23 92 95 50 43 4E ..M.PNOT..#..PCN
+ 00B0: 54 0A 02 86 5C 2E 5F 50 52 5F 43 50 30 30 0A 81 T...\._PR_CP00..
+ 00C0: 86 5C 2E 5F 50 52 5F 43 50 30 31 0A 81 A0 23 92 .\._PR_CP01...#.
+ 00D0: 95 50 43 4E 54 0A 04 86 5C 2E 5F 50 52 5F 43 50 .PCNT...\._PR_CP
+ 00E0: 30 32 0A 81 86 5C 2E 5F 50 52 5F 43 50 30 33 0A 02...\._PR_CP03.
+ 00F0: 81 A0 3D 92 95 50 43 4E 54 0A 08 86 5C 2E 5F 50 ..=..PCNT...\._P
+ 0100: 52 5F 43 50 30 34 0A 81 86 5C 2E 5F 50 52 5F 43 R_CP04...\._PR_C
+ 0110: 50 30 35 0A 81 86 5C 2E 5F 50 52 5F 43 50 30 36 P05...\._PR_CP06
+ 0120: 0A 81 86 5C 2E 5F 50 52 5F 43 50 30 37 0A 81 14 ...\._PR_CP07...
+ 0130: 4D 08 50 50 43 4E 00 A0 23 92 95 50 43 4E 54 0A M.PPCN..#..PCNT.
+ 0140: 02 86 5C 2E 5F 50 52 5F 43 50 30 30 0A 80 86 5C ..\._PR_CP00...\
+ 0150: 2E 5F 50 52 5F 43 50 30 31 0A 80 A0 23 92 95 50 ._PR_CP01...#..P
+ 0160: 43 4E 54 0A 04 86 5C 2E 5F 50 52 5F 43 50 30 32 CNT...\._PR_CP02
+ 0170: 0A 80 86 5C 2E 5F 50 52 5F 43 50 30 33 0A 80 A0 ...\._PR_CP03...
+ 0180: 3D 92 95 50 43 4E 54 0A 08 86 5C 2E 5F 50 52 5F =..PCNT...\._PR_
+ 0190: 43 50 30 34 0A 80 86 5C 2E 5F 50 52 5F 43 50 30 CP04...\._PR_CP0
+ 01A0: 35 0A 80 86 5C 2E 5F 50 52 5F 43 50 30 36 0A 80 5...\._PR_CP06..
+ 01B0: 86 5C 2E 5F 50 52 5F 43 50 30 37 0A 80 14 4D 08 .\._PR_CP07...M.
+ 01C0: 54 4E 4F 54 00 A0 23 92 95 50 43 4E 54 0A 02 86 TNOT..#..PCNT...
+ 01D0: 5C 2E 5F 50 52 5F 43 50 30 30 0A 82 86 5C 2E 5F \._PR_CP00...\._
+ 01E0: 50 52 5F 43 50 30 31 0A 82 A0 23 92 95 50 43 4E PR_CP01...#..PCN
+ 01F0: 54 0A 04 86 5C 2E 5F 50 52 5F 43 50 30 32 0A 82 T...\._PR_CP02..
+ 0200: 86 5C 2E 5F 50 52 5F 43 50 30 33 0A 82 A0 3D 92 .\._PR_CP03...=.
+ 0210: 95 50 43 4E 54 0A 08 86 5C 2E 5F 50 52 5F 43 50 .PCNT...\._PR_CP
+ 0220: 30 34 0A 82 86 5C 2E 5F 50 52 5F 43 50 30 35 0A 04...\._PR_CP05.
+ 0230: 82 86 5C 2E 5F 50 52 5F 43 50 30 36 0A 82 86 5C ..\._PR_CP06...\
+ 0240: 2E 5F 50 52 5F 43 50 30 37 0A 82 14 44 0D 50 50 ._PR_CP07...D.PP
+ 0250: 4B 47 00 A0 4F 05 92 95 50 43 4E 54 0A 08 A4 12 KG..O...PCNT....
+ 0260: 43 05 08 5C 2E 5F 50 52 5F 43 50 30 30 5C 2E 5F C..\._PR_CP00\._
+ 0270: 50 52 5F 43 50 30 31 5C 2E 5F 50 52 5F 43 50 30 PR_CP01\._PR_CP0
+ 0280: 32 5C 2E 5F 50 52 5F 43 50 30 33 5C 2E 5F 50 52 2\._PR_CP03\._PR
+ 0290: 5F 43 50 30 34 5C 2E 5F 50 52 5F 43 50 30 35 5C _CP04\._PR_CP05\
+ 02A0: 2E 5F 50 52 5F 43 50 30 36 5C 2E 5F 50 52 5F 43 ._PR_CP06\._PR_C
+ 02B0: 50 30 37 A1 4C 06 A0 35 92 95 50 43 4E 54 0A 04 P07.L..5..PCNT..
+ 02C0: A4 12 2A 04 5C 2E 5F 50 52 5F 43 50 30 30 5C 2E ..*.\._PR_CP00\.
+ 02D0: 5F 50 52 5F 43 50 30 31 5C 2E 5F 50 52 5F 43 50 _PR_CP01\._PR_CP
+ 02E0: 30 32 5C 2E 5F 50 52 5F 43 50 30 33 A1 33 A0 21 02\._PR_CP03.3.!
+ 02F0: 92 95 50 43 4E 54 0A 02 A4 12 16 02 5C 2E 5F 50 ..PCNT......\._P
+ 0300: 52 5F 43 50 30 30 5C 2E 5F 50 52 5F 43 50 30 31 R_CP00\._PR_CP01
+ 0310: A1 0F A4 12 0C 01 5C 2E 5F 50 52 5F 43 50 30 30 ......\._PR_CP00
+ 0320: 08 50 49 43 4D 00 08 44 53 45 4E 01 5B 80 47 4E .PICM..DSEN.[.GN
+ 0330: 56 53 00 4E 56 53 41 0B 00 0F 5B 81 48 2B 47 4E VS.NVSA...[.H+GN
+ 0340: 56 53 01 4F 53 59 53 10 53 4D 49 46 08 50 52 4D VS.OSYS.SMIF.PRM
+ 0350: 30 08 50 52 4D 31 08 53 43 49 46 08 50 52 4D 32 0.PRM1.SCIF.PRM2
+ 0360: 08 50 52 4D 33 08 4C 43 4B 46 08 50 52 4D 34 08 .PRM3.LCKF.PRM4.
+ 0370: 50 52 4D 35 08 50 38 30 44 20 4C 49 44 53 08 50 PRM5.P80D LIDS.P
+ 0380: 57 52 53 08 54 4C 56 4C 08 46 4C 56 4C 08 54 43 WRS.TLVL.FLVL.TC
+ 0390: 52 54 08 54 50 53 56 08 54 4D 41 58 08 46 30 4F RT.TPSV.TMAX.F0O
+ 03A0: 46 08 46 30 4F 4E 08 46 30 50 57 08 46 31 4F 46 F.F0ON.F0PW.F1OF
+ 03B0: 08 46 31 4F 4E 08 46 31 50 57 08 46 32 4F 46 08 .F1ON.F1PW.F2OF.
+ 03C0: 46 32 4F 4E 08 46 32 50 57 08 46 33 4F 46 08 46 F2ON.F2PW.F3OF.F
+ 03D0: 33 4F 4E 08 46 33 50 57 08 46 34 4F 46 08 46 34 3ON.F3PW.F4OF.F4
+ 03E0: 4F 4E 08 46 34 50 57 08 54 4D 50 53 08 00 10 41 ON.F4PW.TMPS...A
+ 03F0: 50 49 43 08 4D 50 45 4E 08 50 43 50 30 08 50 43 PIC.MPEN.PCP0.PC
+ 0400: 50 31 08 50 50 43 4D 08 50 43 4E 54 08 00 20 4E P1.PPCM.PCNT.. N
+ 0410: 41 54 50 08 53 35 55 30 08 53 35 55 31 08 53 33 ATP.S5U0.S5U1.S3
+ 0420: 55 30 08 53 33 55 31 08 53 33 33 47 08 43 4D 45 U0.S3U1.S33G.CME
+ 0430: 4D 20 49 47 44 53 08 54 4C 53 54 08 43 41 44 4C M IGDS.TLST.CADL
+ 0440: 08 50 41 44 4C 08 43 53 54 45 10 4E 53 54 45 10 .PADL.CSTE.NSTE.
+ 0450: 53 53 54 45 10 4E 44 49 44 08 44 49 44 31 20 44 SSTE.NDID.DID1 D
+ 0460: 49 44 32 20 44 49 44 33 20 44 49 44 34 20 44 49 ID2 DID3 DID4 DI
+ 0470: 44 35 20 00 48 04 42 4C 43 53 08 42 52 54 4C 08 D5 .H.BLCS.BRTL.
+ 0480: 4F 44 44 53 08 00 38 41 4C 53 45 08 41 4C 41 46 ODDS..8ALSE.ALAF
+ 0490: 08 4C 4C 4F 57 08 4C 48 49 48 08 00 30 45 4D 41 .LLOW.LHIH..0EMA
+ 04A0: 45 08 45 4D 41 50 10 45 4D 41 4C 10 00 28 4D 45 E.EMAP.EMAL..(ME
+ 04B0: 46 45 08 00 48 04 54 50 4D 50 08 54 50 4D 45 08 FE..H.TPMP.TPME.
+ 04C0: 00 40 04 47 54 46 30 38 47 54 46 31 38 47 54 46 .@.GTF08GTF18GTF
+ 04D0: 32 38 49 44 45 4D 08 49 44 45 54 08 00 28 58 48 28IDEM.IDET..(XH
+ 04E0: 43 49 08 00 08 41 53 4C 42 20 49 42 54 54 08 49 CI...ASLB IBTT.I
+ 04F0: 50 41 54 08 49 54 56 46 08 49 54 56 4D 08 49 50 PAT.ITVF.ITVM.IP
+ 0500: 53 43 08 49 42 4C 43 08 49 42 49 41 08 49 53 53 SC.IBLC.IBIA.ISS
+ 0510: 43 08 49 34 30 39 08 49 35 30 39 08 49 36 30 39 C.I409.I509.I609
+ 0520: 08 49 37 30 39 08 49 44 4D 4D 08 49 44 4D 53 08 .I709.IDMM.IDMS.
+ 0530: 49 46 31 45 08 48 56 43 4F 08 4E 58 44 31 20 4E IF1E.HVCO.NXD1 N
+ 0540: 58 44 32 20 4E 58 44 33 20 4E 58 44 34 20 4E 58 XD2 NXD3 NXD4 NX
+ 0550: 44 35 20 4E 58 44 36 20 4E 58 44 37 20 4E 58 44 D5 NXD6 NXD7 NXD
+ 0560: 38 20 49 53 43 49 08 50 41 56 50 08 00 08 4F 53 8 ISCI.PAVP...OS
+ 0570: 43 43 08 4E 50 43 45 08 50 4C 46 4C 08 42 52 45 CC.NPCE.PLFL.BRE
+ 0580: 56 08 44 50 42 4D 08 44 50 43 4D 08 44 50 44 4D V.DPBM.DPCM.DPDM
+ 0590: 08 41 4C 46 50 08 49 4D 4F 4E 08 4D 4D 49 4F 08 .ALFP.IMON.MMIO.
+ 05A0: 00 48 05 56 42 54 30 20 56 42 54 31 20 56 42 54 .H.VBT0 VBT1 VBT
+ 05B0: 32 20 56 42 54 33 10 56 42 54 34 40 80 56 42 54 2 VBT3.VBT4@.VBT
+ 05C0: 35 40 20 56 42 54 36 40 20 56 42 54 37 20 56 42 5@ VBT6@ VBT7 VB
+ 05D0: 54 38 20 56 42 54 39 20 43 48 56 44 80 00 06 56 T8 VBT9 CHVD...V
+ 05E0: 42 54 41 20 4D 45 48 48 40 10 52 4D 4F 42 20 52 BTA MEHH@.RMOB R
+ 05F0: 4D 4F 4C 20 14 12 53 33 55 45 00 70 01 53 33 55 MOL ..S3UE.p.S3U
+ 0600: 30 70 01 53 33 55 31 14 12 53 33 55 44 00 70 00 0p.S3U1..S3UD.p.
+ 0610: 53 33 55 30 70 00 53 33 55 31 14 12 53 35 55 45 S3U0p.S3U1..S5UE
+ 0620: 00 70 01 53 35 55 30 70 01 53 35 55 31 14 12 53 .p.S5U0p.S5U1..S
+ 0630: 35 55 44 00 70 00 53 35 55 30 70 00 53 35 55 31 5UD.p.S5U0p.S5U1
+ 0640: 14 0C 53 33 47 45 00 70 01 53 33 33 47 14 0C 53 ..S3GE.p.S33G..S
+ 0650: 33 47 44 00 70 00 53 33 33 47 14 0C 58 48 43 45 3GD.p.S33G..XHCE
+ 0660: 00 70 01 58 48 43 49 14 0C 58 48 43 44 00 70 00 .p.XHCI..XHCD.p.
+ 0670: 58 48 43 49 14 3E 54 5A 55 50 00 A0 1B 5B 12 5C XHCI.>TZUP...[.\
+ 0680: 2E 5F 54 5A 5F 54 48 52 4D 00 86 5C 2E 5F 54 5A ._TZ_THRM..\._TZ
+ 0690: 5F 54 48 52 4D 0A 81 A0 1B 5B 12 5C 2E 5F 54 5A _THRM....[.\._TZ
+ 06A0: 5F 53 4B 49 4E 00 86 5C 2E 5F 54 5A 5F 53 4B 49 _SKIN..\._TZ_SKI
+ 06B0: 4E 0A 81 14 16 46 30 55 54 02 70 68 46 30 4F 46 N....F0UT.phF0OF
+ 06C0: 70 69 46 30 4F 4E 54 5A 55 50 14 16 46 31 55 54 piF0ONTZUP..F1UT
+ 06D0: 02 70 68 46 31 4F 46 70 69 46 31 4F 4E 54 5A 55 .phF1OFpiF1ONTZU
+ 06E0: 50 14 16 46 32 55 54 02 70 68 46 32 4F 46 70 69 P..F2UT.phF2OFpi
+ 06F0: 46 32 4F 4E 54 5A 55 50 14 16 46 33 55 54 02 70 F2ONTZUP..F3UT.p
+ 0700: 68 46 33 4F 46 70 69 46 33 4F 4E 54 5A 55 50 14 hF3OFpiF3ONTZUP.
+ 0710: 16 46 34 55 54 02 70 68 46 34 4F 46 70 69 46 34 .F4UT.phF4OFpiF4
+ 0720: 4F 4E 54 5A 55 50 14 10 54 4D 50 55 01 70 68 54 ONTZUP..TMPU.phT
+ 0730: 4D 50 53 54 5A 55 50 08 5F 53 30 5F 12 06 04 00 MPSTZUP._S0_....
+ 0740: 00 00 00 08 5F 53 33 5F 12 08 04 0A 05 0A 05 00 ...._S3_........
+ 0750: 00 08 5F 53 34 5F 12 08 04 0A 06 0A 06 00 00 08 .._S4_..........
+ 0760: 5F 53 35 5F 12 08 04 0A 07 0A 07 00 00 10 8E EB _S5_............
+ 0770: 01 5F 53 42 5F 5B 82 85 EB 01 50 43 49 30 08 5F ._SB_[....PCI0._
+ 0780: 48 49 44 0C 41 D0 0A 08 08 5F 43 49 44 0C 41 D0 HID.A...._CID.A.
+ 0790: 0A 03 08 5F 41 44 52 00 08 5F 42 42 4E 00 5B 82 ..._ADR.._BBN.[.
+ 07A0: 42 2D 4D 43 48 43 08 5F 41 44 52 00 5B 80 4D 43 B-MCHC._ADR.[.MC
+ 07B0: 48 50 02 00 0B 00 01 5B 81 4F 0B 4D 43 48 50 03 HP.....[.O.MCHP.
+ 07C0: 00 40 20 45 50 45 4E 01 00 0B 45 50 42 52 18 00 .@ EPEN...EPBR..
+ 07D0: 1C 4D 48 45 4E 01 00 0D 4D 48 42 52 16 00 4C 09 .MHEN...MHBR..L.
+ 07E0: 50 58 45 4E 01 50 58 53 5A 02 00 17 50 58 42 52 PXEN.PXSZ...PXBR
+ 07F0: 0A 00 1C 44 4D 45 4E 01 00 0B 44 4D 42 52 18 00 ...DMEN...DMBR..
+ 0800: 1C 4D 45 42 41 40 04 00 40 04 00 04 50 4D 30 48 .MEBA@..@...PM0H
+ 0810: 02 00 02 50 4D 31 4C 02 00 02 50 4D 31 48 02 00 ...PM1L...PM1H..
+ 0820: 02 50 4D 32 4C 02 00 02 50 4D 32 48 02 00 02 50 .PM2L...PM2H...P
+ 0830: 4D 33 4C 02 00 02 50 4D 33 48 02 00 02 50 4D 34 M3L...PM3H...PM4
+ 0840: 4C 02 00 02 50 4D 34 48 02 00 02 50 4D 35 4C 02 L...PM4H...PM5L.
+ 0850: 00 02 50 4D 35 48 02 00 02 50 4D 36 4C 02 00 02 ..PM5H...PM6L...
+ 0860: 50 4D 36 48 02 00 02 00 48 0C 54 4F 4D 5F 40 04 PM6H....H.TOM_@.
+ 0870: 00 40 0A 54 4C 55 44 20 5B 01 43 54 43 4D 01 08 .@.TLUD [.CTCM..
+ 0880: 43 54 43 43 00 08 43 54 43 4E 00 08 43 54 43 44 CTCC..CTCN..CTCD
+ 0890: 01 08 43 54 43 55 0A 02 5B 80 4D 43 48 42 00 0C ..CTCU..[.MCHB..
+ 08A0: 00 00 D1 FE 0B 00 80 5B 81 40 07 4D 43 48 42 13 .......[.@.MCHB.
+ 08B0: 00 80 98 2C 43 54 44 4E 0F 00 41 37 50 4C 31 56 ...,CTDN..A7PL1V
+ 08C0: 0F 50 4C 31 45 01 50 4C 31 43 01 50 4C 31 54 07 .PL1E.PL1C.PL1T.
+ 08D0: 00 08 50 4C 32 56 0F 50 4C 32 45 01 50 4C 32 43 ..PL2V.PL2E.PL2C
+ 08E0: 01 50 4C 32 54 07 00 88 CA 02 54 41 52 4E 08 00 .PL2T.....TARN..
+ 08F0: 18 43 54 44 44 0F 00 01 54 41 52 44 08 00 28 43 .CTDD...TARD..(C
+ 0900: 54 44 55 0F 00 01 54 41 52 55 08 00 28 43 54 43 TDU...TARU..(CTC
+ 0910: 53 02 00 1E 54 41 52 53 08 14 4B 04 50 53 53 53 S...TARS..K.PSSS
+ 0920: 01 70 01 60 70 87 5C 2F 03 5F 50 52 5F 43 50 30 .p.`p.\/._PR_CP0
+ 0930: 30 5F 50 53 53 61 A2 2C 95 60 61 7A 83 88 83 88 0_PSSa.,.`az....
+ 0940: 5C 2F 03 5F 50 52 5F 43 50 30 30 5F 50 53 53 60 \/._PR_CP00_PSS`
+ 0950: 00 0A 04 00 0A 08 62 A0 09 93 62 68 A4 74 60 01 ......b...bh.t`.
+ 0960: 00 75 60 A4 00 14 44 08 53 54 4E 44 08 A0 0B 5B .u`...D.STND...[
+ 0970: 23 43 54 43 4D 64 00 A4 00 A0 12 93 43 54 43 44 #CTCMd......CTCD
+ 0980: 43 54 43 43 5B 27 43 54 43 4D A4 00 70 0D 53 65 CTCC['CTCM..p.Se
+ 0990: 74 20 54 44 50 20 44 6F 77 6E 00 5B 31 70 43 54 t TDP Down.[1pCT
+ 09A0: 43 44 43 54 43 53 70 54 41 52 44 54 41 52 53 70 CDCTCSpTARDTARSp
+ 09B0: 50 53 53 53 54 41 52 44 50 50 43 4D 50 50 43 4E PSSSTARDPPCMPPCN
+ 09C0: 78 77 43 54 44 44 0A 7D 00 0A 64 00 50 4C 32 56 xwCTDD.}..d.PL2V
+ 09D0: 70 43 54 44 44 50 4C 31 56 70 43 54 43 44 43 54 pCTDDPL1VpCTCDCT
+ 09E0: 43 43 5B 27 43 54 43 4D A4 01 14 47 08 53 54 44 CC['CTCM...G.STD
+ 09F0: 4E 08 A0 0B 5B 23 43 54 43 4D 64 00 A4 00 A0 12 N...[#CTCMd.....
+ 0A00: 93 43 54 43 4E 43 54 43 43 5B 27 43 54 43 4D A4 .CTCNCTCC['CTCM.
+ 0A10: 00 70 0D 53 65 74 20 54 44 50 20 4E 6F 6D 69 6E .p.Set TDP Nomin
+ 0A20: 61 6C 00 5B 31 70 43 54 44 4E 50 4C 31 56 78 77 al.[1pCTDNPL1Vxw
+ 0A30: 43 54 44 4E 0A 7D 00 0A 64 00 50 4C 32 56 70 50 CTDN.}..d.PL2VpP
+ 0A40: 53 53 53 54 41 52 4E 50 50 43 4D 50 50 43 4E 70 SSSTARNPPCMPPCNp
+ 0A50: 54 41 52 4E 54 41 52 53 70 43 54 43 4E 43 54 43 TARNTARSpCTCNCTC
+ 0A60: 53 70 43 54 43 4E 43 54 43 43 5B 27 43 54 43 4D SpCTCNCTCC['CTCM
+ 0A70: A4 01 08 4D 43 52 53 11 43 1F 0B EE 01 88 0D 00 ...MCRS.C.......
+ 0A80: 02 0C 00 00 00 00 00 FF 00 00 00 00 01 87 17 00 ................
+ 0A90: 01 0C 03 00 00 00 00 00 00 00 00 F7 0C 00 00 00 ................
+ 0AA0: 00 00 00 F8 0C 00 00 47 01 F8 0C F8 0C 01 08 87 .......G........
+ 0AB0: 17 00 01 0C 03 00 00 00 00 00 0D 00 00 FF FF 00 ................
+ 0AC0: 00 00 00 00 00 00 F3 00 00 87 17 00 00 0C 03 00 ................
+ 0AD0: 00 00 00 00 00 0A 00 FF FF 0B 00 00 00 00 00 00 ................
+ 0AE0: 00 02 00 87 17 00 00 0C 03 00 00 00 00 00 00 0C ................
+ 0AF0: 00 FF 3F 0C 00 00 00 00 00 00 40 00 00 87 17 00 ..?.......@.....
+ 0B00: 00 0C 03 00 00 00 00 00 40 0C 00 FF 7F 0C 00 00 ........@.......
+ 0B10: 00 00 00 00 40 00 00 87 17 00 00 0C 03 00 00 00 ....@...........
+ 0B20: 00 00 80 0C 00 FF BF 0C 00 00 00 00 00 00 40 00 ..............@.
+ 0B30: 00 87 17 00 00 0C 03 00 00 00 00 00 C0 0C 00 FF ................
+ 0B40: FF 0C 00 00 00 00 00 00 40 00 00 87 17 00 00 0C ........@.......
+ 0B50: 03 00 00 00 00 00 00 0D 00 FF 3F 0D 00 00 00 00 ..........?.....
+ 0B60: 00 00 40 00 00 87 17 00 00 0C 03 00 00 00 00 00 ..@.............
+ 0B70: 40 0D 00 FF 7F 0D 00 00 00 00 00 00 40 00 00 87 @...........@...
+ 0B80: 17 00 00 0C 03 00 00 00 00 00 80 0D 00 FF BF 0D ................
+ 0B90: 00 00 00 00 00 00 40 00 00 87 17 00 00 0C 03 00 ......@.........
+ 0BA0: 00 00 00 00 C0 0D 00 FF FF 0D 00 00 00 00 00 00 ................
+ 0BB0: 40 00 00 87 17 00 00 0C 03 00 00 00 00 00 00 0E @...............
+ 0BC0: 00 FF 3F 0E 00 00 00 00 00 00 40 00 00 87 17 00 ..?.......@.....
+ 0BD0: 00 0C 03 00 00 00 00 00 40 0E 00 FF 7F 0E 00 00 ........@.......
+ 0BE0: 00 00 00 00 40 00 00 87 17 00 00 0C 03 00 00 00 ....@...........
+ 0BF0: 00 00 80 0E 00 FF BF 0E 00 00 00 00 00 00 40 00 ..............@.
+ 0C00: 00 87 17 00 00 0C 03 00 00 00 00 00 C0 0E 00 FF ................
+ 0C10: FF 0E 00 00 00 00 00 00 40 00 00 87 17 00 00 0C ........@.......
+ 0C20: 03 00 00 00 00 00 00 0F 00 FF FF 0F 00 00 00 00 ................
+ 0C30: 00 00 00 01 00 87 17 00 00 0C 03 00 00 00 00 00 ................
+ 0C40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 87 ................
+ 0C50: 17 00 00 0C 03 00 00 00 00 00 00 D4 FE FF 4F D4 ..............O.
+ 0C60: FE 00 00 00 00 00 50 00 00 79 00 14 49 07 5F 43 ......P..y..I._C
+ 0C70: 52 53 08 8A 4D 43 52 53 0B C2 01 50 4D 49 4E 8A RS..MCRS...PMIN.
+ 0C80: 4D 43 52 53 0B C6 01 50 4D 41 58 8A 4D 43 52 53 MCRS...PMAX.MCRS
+ 0C90: 0B CE 01 50 4C 45 4E 70 5E 2E 4D 43 48 43 54 4C ...PLENp^.MCHCTL
+ 0CA0: 55 44 60 70 5E 2E 4D 43 48 43 4D 45 42 41 61 A0 UD`p^.MCHCMEBAa.
+ 0CB0: 10 93 60 61 70 5E 2E 4D 43 48 43 54 4F 4D 5F 60 ..`ap^.MCHCTOM_`
+ 0CC0: 70 60 50 4D 49 4E 70 0C FF FF FF EF 50 4D 41 58 p`PMINp.....PMAX
+ 0CD0: 72 74 50 4D 41 58 50 4D 49 4E 00 01 50 4C 45 4E rtPMAXPMIN..PLEN
+ 0CE0: A4 4D 43 52 53 5B 82 46 0A 50 44 52 43 08 5F 48 .MCRS[.F.PDRC._H
+ 0CF0: 49 44 0C 41 D0 0C 02 08 5F 55 49 44 01 08 50 44 ID.A...._UID..PD
+ 0D00: 52 53 11 4E 07 0A 7A 86 09 00 01 00 C0 D1 FE 00 RS.N..z.........
+ 0D10: 40 00 00 86 09 00 01 00 00 D1 FE 00 80 00 00 86 @...............
+ 0D20: 09 00 01 00 80 D1 FE 00 10 00 00 86 09 00 01 00 ................
+ 0D30: 90 D1 FE 00 10 00 00 86 09 00 01 00 00 00 F0 00 ................
+ 0D40: 00 00 04 86 09 00 01 00 00 D2 FE 00 00 02 00 86 ................
+ 0D50: 09 00 01 00 00 D4 FE 00 50 00 00 86 09 00 01 00 ........P.......
+ 0D60: 50 D4 FE 00 B0 04 00 86 09 00 01 00 00 00 20 00 P............. .
+ 0D70: 00 20 00 86 09 00 01 00 00 00 40 00 00 20 00 79 . ........@.. .y
+ 0D80: 00 14 0B 5F 43 52 53 08 A4 50 44 52 53 5B 82 42 ..._CRS..PDRS[.B
+ 0D90: 1E 47 46 58 30 08 5F 41 44 52 0C 00 00 02 00 5B .GFX0._ADR.....[
+ 0DA0: 80 47 46 58 43 02 00 0B 00 01 5B 81 0F 47 46 58 .GFXC.....[..GFX
+ 0DB0: 43 03 00 40 08 42 41 52 30 40 04 5B 80 47 46 52 C..@.BAR0@.[.GFR
+ 0DC0: 47 00 7B 42 41 52 30 0E F0 FF FF FF FF FF FF FF G.{BAR0.........
+ 0DD0: 00 0C 00 00 40 00 5B 81 1A 47 46 52 47 03 00 C0 ....@.[..GFRG...
+ 0DE0: 2A 41 02 42 43 4C 56 10 00 C0 00 00 04 42 43 4C *A.BCLV......BCL
+ 0DF0: 4D 10 14 17 58 42 43 4D 01 70 78 77 68 42 43 4C M...XBCM.pxwhBCL
+ 0E00: 4D 00 0A 64 00 00 42 43 4C 56 14 44 05 58 42 51 M..d..BCLV.D.XBQ
+ 0E10: 43 00 70 42 43 4C 56 60 70 42 43 4C 4D 61 70 0A C.pBCLV`pBCLMap.
+ 0E20: 02 62 A2 33 95 62 74 87 42 52 49 47 01 00 70 83 .b.3.bt.BRIG..p.
+ 0E30: 88 42 52 49 47 62 00 63 70 78 77 63 61 00 0A 64 .BRIGb.cpxwca..d
+ 0E40: 00 00 63 A0 0E 92 94 60 63 A4 83 88 42 52 49 47 ..c....`c...BRIG
+ 0E50: 62 00 72 62 01 62 A4 83 88 42 52 49 47 62 00 08 b.rb.b...BRIGb..
+ 0E60: 42 52 43 54 00 14 23 42 52 49 44 01 70 89 42 52 BRCT..#BRID.p.BR
+ 0E70: 49 47 01 68 00 00 0A 02 60 A0 0D 93 60 FF A4 74 IG.h....`...`..t
+ 0E80: 87 42 52 49 47 01 00 A4 60 14 11 58 42 43 4C 00 .BRIG...`..XBCL.
+ 0E90: 70 01 42 52 43 54 A4 42 52 49 47 14 10 5F 44 4F p.BRCT.BRIG.._DO
+ 0EA0: 53 01 70 7B 68 0A 07 00 44 53 45 4E 14 34 44 45 S.p{h...DSEN.4DE
+ 0EB0: 43 42 00 A0 0C 42 52 43 54 86 4C 43 44 30 0A 87 CB...BRCT.LCD0..
+ 0EC0: A1 20 70 42 52 49 44 58 42 51 43 60 A0 08 92 93 . pBRIDXBQC`....
+ 0ED0: 60 0A 02 76 60 58 42 43 4D 83 88 42 52 49 47 60 `..v`XBCM..BRIG`
+ 0EE0: 00 14 3A 49 4E 43 42 00 A0 0C 42 52 43 54 86 4C ..:INCB...BRCT.L
+ 0EF0: 43 44 30 0A 86 A1 26 70 42 52 49 44 58 42 51 43 CD0...&pBRIDXBQC
+ 0F00: 60 A0 0E 92 93 60 74 87 42 52 49 47 01 00 75 60 `....`t.BRIG..u`
+ 0F10: 58 42 43 4D 83 88 42 52 49 47 60 00 14 1D 58 44 XBCM..BRIG`...XD
+ 0F20: 43 53 01 54 52 41 50 01 A0 0E 7B 43 53 54 45 79 CS.TRAP...{CSTEy
+ 0F30: 01 68 00 00 A4 0A 1F A4 0A 1D 14 16 58 44 47 53 .h..........XDGS
+ 0F40: 01 A0 0D 7B 4E 53 54 45 79 01 68 00 00 A4 01 A4 ...{NSTEy.h.....
+ 0F50: 00 14 1F 58 44 53 53 02 A0 18 93 7B 68 0C 00 00 ...XDSS....{h...
+ 0F60: 00 C0 00 0C 00 00 00 C0 70 4E 53 54 45 43 53 54 ........pNSTECST
+ 0F70: 45 10 4B 3B 5C 00 5B 80 49 4F 5F 54 01 0B 00 08 E.K;\.[.IO_T....
+ 0F80: 0A 10 5B 81 0E 49 4F 5F 54 01 00 40 04 54 52 50 ..[..IO_T..@.TRP
+ 0F90: 30 08 5B 80 50 4D 49 4F 01 0B 00 05 0A 80 5B 81 0.[.PMIO......[.
+ 0FA0: 4A 0B 50 4D 49 4F 01 00 40 10 00 10 47 53 30 30 J.PMIO..@...GS00
+ 0FB0: 01 47 53 30 31 01 47 53 30 32 01 47 53 30 33 01 .GS01.GS02.GS03.
+ 0FC0: 47 53 30 34 01 47 53 30 35 01 47 53 30 36 01 47 GS04.GS05.GS06.G
+ 0FD0: 53 30 37 01 47 53 30 38 01 47 53 30 39 01 47 53 S07.GS08.GS09.GS
+ 0FE0: 31 30 01 47 53 31 31 01 47 53 31 32 01 47 53 31 10.GS11.GS12.GS1
+ 0FF0: 33 01 47 53 31 34 01 47 53 31 35 01 00 20 00 10 3.GS14.GS15.. ..
+ 1000: 47 45 30 30 01 47 45 30 31 01 47 45 30 32 01 47 GE00.GE01.GE02.G
+ 1010: 45 30 33 01 47 45 30 34 01 47 45 30 35 01 47 45 E03.GE04.GE05.GE
+ 1020: 30 36 01 47 45 30 37 01 47 45 30 38 01 47 45 30 06.GE07.GE08.GE0
+ 1030: 39 01 47 45 31 30 01 47 45 31 31 01 47 45 31 32 9.GE10.GE11.GE12
+ 1040: 01 47 45 31 33 01 47 45 31 34 01 47 45 31 35 01 .GE13.GE14.GE15.
+ 1050: 00 40 0B 00 01 47 50 45 43 01 5B 80 47 50 49 4F .@...GPEC.[.GPIO
+ 1060: 01 0B 80 04 0A 6C 5B 81 4D 21 47 50 49 4F 01 47 .....l[.M!GPIO.G
+ 1070: 55 30 30 08 47 55 30 31 08 47 55 30 32 08 47 55 U00.GU01.GU02.GU
+ 1080: 30 33 08 47 49 4F 30 08 47 49 4F 31 08 47 49 4F 03.GIO0.GIO1.GIO
+ 1090: 32 08 47 49 4F 33 08 00 20 47 4C 30 30 01 47 50 2.GIO3.. GL00.GP
+ 10A0: 30 31 01 47 50 30 32 01 47 50 30 33 01 47 50 30 01.GP02.GP03.GP0
+ 10B0: 34 01 47 50 30 35 01 47 50 30 36 01 47 50 30 37 4.GP05.GP06.GP07
+ 10C0: 01 47 50 30 38 01 47 50 30 39 01 47 50 31 30 01 .GP08.GP09.GP10.
+ 10D0: 47 50 31 31 01 47 50 31 32 01 47 50 31 33 01 47 GP11.GP12.GP13.G
+ 10E0: 50 31 34 01 47 50 31 35 01 47 50 31 36 01 47 50 P14.GP15.GP16.GP
+ 10F0: 31 37 01 47 50 31 38 01 47 50 31 39 01 47 50 32 17.GP18.GP19.GP2
+ 1100: 30 01 47 50 32 31 01 47 50 32 32 01 47 50 32 33 0.GP21.GP22.GP23
+ 1110: 01 47 50 32 34 01 47 50 32 35 01 47 50 32 36 01 .GP24.GP25.GP26.
+ 1120: 47 50 32 37 01 47 50 32 38 01 47 50 32 39 01 47 GP27.GP28.GP29.G
+ 1130: 50 33 30 01 47 50 33 31 01 00 40 04 47 42 30 30 P30.GP31..@.GB00
+ 1140: 08 47 42 30 31 08 47 42 30 32 08 47 42 30 33 08 .GB01.GB02.GB03.
+ 1150: 00 40 08 47 49 56 30 08 47 49 56 31 08 47 49 56 .@.GIV0.GIV1.GIV
+ 1160: 32 08 47 49 56 33 08 47 55 30 34 08 47 55 30 35 2.GIV3.GU04.GU05
+ 1170: 08 47 55 30 36 08 47 55 30 37 08 47 49 4F 34 08 .GU06.GU07.GIO4.
+ 1180: 47 49 4F 35 08 47 49 4F 36 08 47 49 4F 37 08 47 GIO5.GIO6.GIO7.G
+ 1190: 50 33 32 01 47 50 33 33 01 47 50 33 34 01 47 50 P32.GP33.GP34.GP
+ 11A0: 33 35 01 47 50 33 36 01 47 50 33 37 01 47 50 33 35.GP36.GP37.GP3
+ 11B0: 38 01 47 50 33 39 01 47 50 34 30 01 47 50 34 31 8.GP39.GP40.GP41
+ 11C0: 01 47 50 34 32 01 47 50 34 33 01 47 50 34 34 01 .GP42.GP43.GP44.
+ 11D0: 47 50 34 35 01 47 50 34 36 01 47 50 34 37 01 47 GP45.GP46.GP47.G
+ 11E0: 50 34 38 01 47 50 34 39 01 47 50 35 30 01 47 50 P48.GP49.GP50.GP
+ 11F0: 35 31 01 47 50 35 32 01 47 50 35 33 01 47 50 35 51.GP52.GP53.GP5
+ 1200: 34 01 47 50 35 35 01 47 50 35 36 01 47 50 35 37 4.GP55.GP56.GP57
+ 1210: 01 47 50 35 38 01 47 50 35 39 01 47 50 36 30 01 .GP58.GP59.GP60.
+ 1220: 47 50 36 31 01 47 50 36 32 01 47 50 36 33 01 00 GP61.GP62.GP63..
+ 1230: 20 47 55 30 38 08 47 55 30 39 04 00 14 47 49 4F GU08.GU09...GIO
+ 1240: 38 08 47 49 4F 39 04 00 14 47 50 36 34 01 47 50 8.GIO9...GP64.GP
+ 1250: 36 35 01 47 50 36 36 01 47 50 36 37 01 47 50 36 65.GP66.GP67.GP6
+ 1260: 38 01 47 50 36 39 01 47 50 37 30 01 47 50 37 31 8.GP69.GP70.GP71
+ 1270: 01 47 50 37 32 01 47 50 37 33 01 47 50 37 34 01 .GP72.GP73.GP74.
+ 1280: 47 50 37 35 01 5B 80 52 43 52 42 00 0C 00 C0 D1 GP75.[.RCRB.....
+ 1290: FE 0B 00 40 5B 81 47 09 52 43 52 42 13 00 80 00 ...@[.G.RCRB....
+ 12A0: 08 00 80 00 10 00 80 02 02 48 50 41 53 02 00 05 .........HPAS...
+ 12B0: 48 50 54 45 01 00 48 09 00 01 50 43 49 44 01 53 HPTE..H...PCID.S
+ 12C0: 41 31 44 01 53 4D 42 44 01 48 44 41 44 01 00 08 A1D.SMBD.HDAD...
+ 12D0: 45 48 32 44 01 4C 50 42 44 01 45 48 31 44 01 52 EH2D.LPBD.EH1D.R
+ 12E0: 50 31 44 01 52 50 32 44 01 52 50 33 44 01 52 50 P1D.RP2D.RP3D.RP
+ 12F0: 34 44 01 52 50 35 44 01 52 50 36 44 01 52 50 37 4D.RP5D.RP6D.RP7
+ 1300: 44 01 52 50 38 44 01 54 54 52 44 01 53 41 32 44 D.RP8D.TTRD.SA2D
+ 1310: 01 00 46 06 42 44 46 44 01 4D 45 31 44 01 4D 45 ..F.BDFD.ME1D.ME
+ 1320: 32 44 01 49 44 52 44 01 4B 54 43 54 01 5B 82 1B 2D.IDRD.KTCT.[..
+ 1330: 48 44 45 46 08 5F 41 44 52 0C 00 00 1B 00 08 5F HDEF._ADR......_
+ 1340: 50 52 57 12 06 02 0A 0D 0A 04 14 45 2E 49 52 51 PRW........E.IRQ
+ 1350: 4D 09 08 5F 54 5F 30 00 08 49 51 41 41 12 2C 04 M.._T_0..IQAA.,.
+ 1360: 12 09 04 0B FF FF 00 00 0A 10 12 09 04 0B FF FF ................
+ 1370: 01 00 0A 11 12 0A 04 0B FF FF 0A 02 00 0A 12 12 ................
+ 1380: 0A 04 0B FF FF 0A 03 00 0A 13 08 49 51 41 50 12 ...........IQAP.
+ 1390: 4D 04 04 12 11 04 0B FF FF 00 5E 2E 4C 50 43 42 M.........^.LPCB
+ 13A0: 4C 4E 4B 41 00 12 11 04 0B FF FF 01 5E 2E 4C 50 LNKA........^.LP
+ 13B0: 43 42 4C 4E 4B 42 00 12 12 04 0B FF FF 0A 02 5E CBLNKB.........^
+ 13C0: 2E 4C 50 43 42 4C 4E 4B 43 00 12 12 04 0B FF FF .LPCBLNKC.......
+ 13D0: 0A 03 5E 2E 4C 50 43 42 4C 4E 4B 44 00 08 49 51 ..^.LPCBLNKD..IQ
+ 13E0: 42 41 12 2C 04 12 09 04 0B FF FF 00 00 0A 11 12 BA.,............
+ 13F0: 09 04 0B FF FF 01 00 0A 12 12 0A 04 0B FF FF 0A ................
+ 1400: 02 00 0A 13 12 0A 04 0B FF FF 0A 03 00 0A 10 08 ................
+ 1410: 49 51 42 50 12 4D 04 04 12 11 04 0B FF FF 00 5E IQBP.M.........^
+ 1420: 2E 4C 50 43 42 4C 4E 4B 42 00 12 11 04 0B FF FF .LPCBLNKB.......
+ 1430: 01 5E 2E 4C 50 43 42 4C 4E 4B 43 00 12 12 04 0B .^.LPCBLNKC.....
+ 1440: FF FF 0A 02 5E 2E 4C 50 43 42 4C 4E 4B 44 00 12 ....^.LPCBLNKD..
+ 1450: 12 04 0B FF FF 0A 03 5E 2E 4C 50 43 42 4C 4E 4B .......^.LPCBLNK
+ 1460: 41 00 08 49 51 43 41 12 2C 04 12 09 04 0B FF FF A..IQCA.,.......
+ 1470: 00 00 0A 12 12 09 04 0B FF FF 01 00 0A 13 12 0A ................
+ 1480: 04 0B FF FF 0A 02 00 0A 10 12 0A 04 0B FF FF 0A ................
+ 1490: 03 00 0A 11 08 49 51 43 50 12 4D 04 04 12 11 04 .....IQCP.M.....
+ 14A0: 0B FF FF 00 5E 2E 4C 50 43 42 4C 4E 4B 43 00 12 ....^.LPCBLNKC..
+ 14B0: 11 04 0B FF FF 01 5E 2E 4C 50 43 42 4C 4E 4B 44 ......^.LPCBLNKD
+ 14C0: 00 12 12 04 0B FF FF 0A 02 5E 2E 4C 50 43 42 4C .........^.LPCBL
+ 14D0: 4E 4B 41 00 12 12 04 0B FF FF 0A 03 5E 2E 4C 50 NKA.........^.LP
+ 14E0: 43 42 4C 4E 4B 42 00 08 49 51 44 41 12 2C 04 12 CBLNKB..IQDA.,..
+ 14F0: 09 04 0B FF FF 00 00 0A 13 12 09 04 0B FF FF 01 ................
+ 1500: 00 0A 10 12 0A 04 0B FF FF 0A 02 00 0A 11 12 0A ................
+ 1510: 04 0B FF FF 0A 03 00 0A 12 08 49 51 44 50 12 4D ..........IQDP.M
+ 1520: 04 04 12 11 04 0B FF FF 00 5E 2E 4C 50 43 42 4C .........^.LPCBL
+ 1530: 4E 4B 44 00 12 11 04 0B FF FF 01 5E 2E 4C 50 43 NKD........^.LPC
+ 1540: 42 4C 4E 4B 41 00 12 12 04 0B FF FF 0A 02 5E 2E BLNKA.........^.
+ 1550: 4C 50 43 42 4C 4E 4B 42 00 12 12 04 0B FF FF 0A LPCBLNKB........
+ 1560: 03 5E 2E 4C 50 43 42 4C 4E 4B 43 00 A2 43 0C 01 .^.LPCBLNKC..C..
+ 1570: 70 99 68 00 5F 54 5F 30 A0 25 92 93 89 12 05 02 p.h._T_0.%......
+ 1580: 01 0A 05 01 5F 54 5F 30 00 00 00 FF A0 0A 50 49 ...._T_0......PI
+ 1590: 43 4D A4 49 51 41 41 A1 06 A4 49 51 41 50 A1 40 CM.IQAA...IQAP.@
+ 15A0: 09 A0 26 92 93 89 12 06 02 0A 02 0A 06 01 5F 54 ..&..........._T
+ 15B0: 5F 30 00 00 00 FF A0 0A 50 49 43 4D A4 49 51 42 _0......PICM.IQB
+ 15C0: 41 A1 06 A4 49 51 42 50 A1 46 06 A0 26 92 93 89 A...IQBP.F..&...
+ 15D0: 12 06 02 0A 03 0A 07 01 5F 54 5F 30 00 00 00 FF ........_T_0....
+ 15E0: A0 0A 50 49 43 4D A4 49 51 43 41 A1 06 A4 49 51 ..PICM.IQCA...IQ
+ 15F0: 43 50 A1 3C A0 26 92 93 89 12 06 02 0A 04 0A 08 CP.<.&..........
+ 1600: 01 5F 54 5F 30 00 00 00 FF A0 0A 50 49 43 4D A4 ._T_0......PICM.
+ 1610: 49 51 44 41 A1 06 A4 49 51 44 50 A1 13 A0 0A 50 IQDA...IQDP....P
+ 1620: 49 43 4D A4 49 51 44 41 A1 06 A4 49 51 44 50 A5 ICM.IQDA...IQDP.
+ 1630: 5B 82 40 05 52 50 30 31 08 5F 41 44 52 0C 00 00 [.@.RP01._ADR...
+ 1640: 1C 00 5B 80 52 50 43 53 02 00 0A FF 5B 81 24 52 ..[.RPCS....[.$R
+ 1650: 50 43 53 00 00 40 26 00 18 52 50 50 4E 08 00 40 PCS..@&..RPPN..@
+ 1660: 05 00 03 50 44 43 5F 01 00 44 42 00 06 48 50 43 ...PDC_..DB..HPC
+ 1670: 53 01 14 0F 5F 50 52 54 00 A4 49 52 51 4D 52 50 S..._PRT..IRQMRP
+ 1680: 50 4E 5B 82 40 05 52 50 30 32 08 5F 41 44 52 0C PN[.@.RP02._ADR.
+ 1690: 01 00 1C 00 5B 80 52 50 43 53 02 00 0A FF 5B 81 ....[.RPCS....[.
+ 16A0: 24 52 50 43 53 00 00 40 26 00 18 52 50 50 4E 08 $RPCS..@&..RPPN.
+ 16B0: 00 40 05 00 03 50 44 43 5F 01 00 44 42 00 06 48 .@...PDC_..DB..H
+ 16C0: 50 43 53 01 14 0F 5F 50 52 54 00 A4 49 52 51 4D PCS..._PRT..IRQM
+ 16D0: 52 50 50 4E 5B 82 40 05 52 50 30 33 08 5F 41 44 RPPN[.@.RP03._AD
+ 16E0: 52 0C 02 00 1C 00 5B 80 52 50 43 53 02 00 0A FF R.....[.RPCS....
+ 16F0: 5B 81 24 52 50 43 53 00 00 40 26 00 18 52 50 50 [.$RPCS..@&..RPP
+ 1700: 4E 08 00 40 05 00 03 50 44 43 5F 01 00 44 42 00 N..@...PDC_..DB.
+ 1710: 06 48 50 43 53 01 14 0F 5F 50 52 54 00 A4 49 52 .HPCS..._PRT..IR
+ 1720: 51 4D 52 50 50 4E 5B 82 40 05 52 50 30 34 08 5F QMRPPN[.@.RP04._
+ 1730: 41 44 52 0C 03 00 1C 00 5B 80 52 50 43 53 02 00 ADR.....[.RPCS..
+ 1740: 0A FF 5B 81 24 52 50 43 53 00 00 40 26 00 18 52 ..[.$RPCS..@&..R
+ 1750: 50 50 4E 08 00 40 05 00 03 50 44 43 5F 01 00 44 PPN..@...PDC_..D
+ 1760: 42 00 06 48 50 43 53 01 14 0F 5F 50 52 54 00 A4 B..HPCS..._PRT..
+ 1770: 49 52 51 4D 52 50 50 4E 5B 82 40 05 52 50 30 35 IRQMRPPN[.@.RP05
+ 1780: 08 5F 41 44 52 0C 04 00 1C 00 5B 80 52 50 43 53 ._ADR.....[.RPCS
+ 1790: 02 00 0A FF 5B 81 24 52 50 43 53 00 00 40 26 00 ....[.$RPCS..@&.
+ 17A0: 18 52 50 50 4E 08 00 40 05 00 03 50 44 43 5F 01 .RPPN..@...PDC_.
+ 17B0: 00 44 42 00 06 48 50 43 53 01 14 0F 5F 50 52 54 .DB..HPCS..._PRT
+ 17C0: 00 A4 49 52 51 4D 52 50 50 4E 5B 82 40 05 52 50 ..IRQMRPPN[.@.RP
+ 17D0: 30 36 08 5F 41 44 52 0C 05 00 1C 00 5B 80 52 50 06._ADR.....[.RP
+ 17E0: 43 53 02 00 0A FF 5B 81 24 52 50 43 53 00 00 40 CS....[.$RPCS..@
+ 17F0: 26 00 18 52 50 50 4E 08 00 40 05 00 03 50 44 43 &..RPPN..@...PDC
+ 1800: 5F 01 00 44 42 00 06 48 50 43 53 01 14 0F 5F 50 _..DB..HPCS..._P
+ 1810: 52 54 00 A4 49 52 51 4D 52 50 50 4E 5B 82 40 05 RT..IRQMRPPN[.@.
+ 1820: 52 50 30 37 08 5F 41 44 52 0C 06 00 1C 00 5B 80 RP07._ADR.....[.
+ 1830: 52 50 43 53 02 00 0A FF 5B 81 24 52 50 43 53 00 RPCS....[.$RPCS.
+ 1840: 00 40 26 00 18 52 50 50 4E 08 00 40 05 00 03 50 .@&..RPPN..@...P
+ 1850: 44 43 5F 01 00 44 42 00 06 48 50 43 53 01 14 0F DC_..DB..HPCS...
+ 1860: 5F 50 52 54 00 A4 49 52 51 4D 52 50 50 4E 5B 82 _PRT..IRQMRPPN[.
+ 1870: 40 05 52 50 30 38 08 5F 41 44 52 0C 07 00 1C 00 @.RP08._ADR.....
+ 1880: 5B 80 52 50 43 53 02 00 0A FF 5B 81 24 52 50 43 [.RPCS....[.$RPC
+ 1890: 53 00 00 40 26 00 18 52 50 50 4E 08 00 40 05 00 S..@&..RPPN..@..
+ 18A0: 03 50 44 43 5F 01 00 44 42 00 06 48 50 43 53 01 .PDC_..DB..HPCS.
+ 18B0: 14 0F 5F 50 52 54 00 A4 49 52 51 4D 52 50 50 4E .._PRT..IRQMRPPN
+ 18C0: 5B 82 41 09 45 48 43 31 08 5F 41 44 52 0C 00 00 [.A.EHC1._ADR...
+ 18D0: 1D 00 08 5F 50 52 57 12 06 02 0A 0D 0A 04 14 09 ..._PRW.........
+ 18E0: 5F 53 33 44 00 A4 0A 02 14 09 5F 53 34 44 00 A4 _S3D......_S4D..
+ 18F0: 0A 02 5B 82 4F 05 48 55 42 37 08 5F 41 44 52 00 ..[.O.HUB7._ADR.
+ 1900: 5B 82 0B 50 52 54 31 08 5F 41 44 52 01 5B 82 0C [..PRT1._ADR.[..
+ 1910: 50 52 54 32 08 5F 41 44 52 0A 02 5B 82 0C 50 52 PRT2._ADR..[..PR
+ 1920: 54 33 08 5F 41 44 52 0A 03 5B 82 0C 50 52 54 34 T3._ADR..[..PRT4
+ 1930: 08 5F 41 44 52 0A 04 5B 82 0C 50 52 54 35 08 5F ._ADR..[..PRT5._
+ 1940: 41 44 52 0A 05 5B 82 0C 50 52 54 36 08 5F 41 44 ADR..[..PRT6._AD
+ 1950: 52 0A 06 5B 82 41 09 45 48 43 32 08 5F 41 44 52 R..[.A.EHC2._ADR
+ 1960: 0C 00 00 1A 00 08 5F 50 52 57 12 06 02 0A 0D 0A ......_PRW......
+ 1970: 04 14 09 5F 53 33 44 00 A4 0A 02 14 09 5F 53 34 ..._S3D......_S4
+ 1980: 44 00 A4 0A 02 5B 82 4F 05 48 55 42 37 08 5F 41 D....[.O.HUB7._A
+ 1990: 44 52 00 5B 82 0B 50 52 54 31 08 5F 41 44 52 01 DR.[..PRT1._ADR.
+ 19A0: 5B 82 0C 50 52 54 32 08 5F 41 44 52 0A 02 5B 82 [..PRT2._ADR..[.
+ 19B0: 0C 50 52 54 33 08 5F 41 44 52 0A 03 5B 82 0C 50 .PRT3._ADR..[..P
+ 19C0: 52 54 34 08 5F 41 44 52 0A 04 5B 82 0C 50 52 54 RT4._ADR..[..PRT
+ 19D0: 35 08 5F 41 44 52 0A 05 5B 82 0C 50 52 54 36 08 5._ADR..[..PRT6.
+ 19E0: 5F 41 44 52 0A 06 5B 82 46 13 58 48 43 5F 08 5F _ADR..[.F.XHC_._
+ 19F0: 41 44 52 0C 00 00 14 00 5B 80 58 44 45 56 02 00 ADR.....[.XDEV..
+ 1A00: 0B 00 01 5B 81 22 58 44 45 56 03 00 40 68 58 32 ...[."XDEV..@hX2
+ 1A10: 50 52 20 50 52 4D 32 20 53 53 45 4E 20 52 50 4D PR PRM2 SSEN RPM
+ 1A20: 33 20 58 50 52 54 20 08 5F 50 52 57 12 06 02 0A 3 XPRT ._PRW....
+ 1A30: 0D 0A 04 14 46 0D 50 4F 53 43 0B 8A 6A 00 43 44 ....F.POSC..j.CD
+ 1A40: 57 31 A0 10 92 93 69 01 7D 43 44 57 31 0A 08 43 W1....i.}CDW1..C
+ 1A50: 44 57 31 A0 12 93 58 48 43 49 00 7D 43 44 57 31 DW1...XHCI.}CDW1
+ 1A60: 0A 02 43 44 57 31 A0 41 0A 90 92 7B 43 44 57 31 ..CDW1.A...{CDW1
+ 1A70: 01 00 91 93 58 48 43 49 0A 02 93 58 48 43 49 0A ....XHCI...XHCI.
+ 1A80: 03 70 0D 58 48 43 49 20 53 77 69 74 63 68 00 5B .p.XHCI Switch.[
+ 1A90: 31 70 00 60 7B 58 50 52 54 0A 03 60 A0 0C 91 93 1p.`{XPRT..`....
+ 1AA0: 60 00 93 60 01 70 0A 0F 61 A1 16 A0 09 93 60 0A `..`.p..a.....`.
+ 1AB0: 02 70 0A 03 61 A1 0A A0 08 93 60 0A 03 70 00 61 .p..a.....`..p.a
+ 1AC0: 7B 52 50 4D 33 0C F0 FF FF FF 60 7D 60 61 52 50 {RPM3.....`}`aRP
+ 1AD0: 4D 33 7B 50 52 4D 32 0C F0 FF FF FF 60 7D 60 61 M3{PRM2.....`}`a
+ 1AE0: 50 52 4D 32 7B 53 53 45 4E 0C F0 FF FF FF 60 7D PRM2{SSEN.....`}
+ 1AF0: 60 61 53 53 45 4E 7B 58 32 50 52 0C F0 FF FF FF `aSSEN{X2PR.....
+ 1B00: 60 7D 60 61 58 32 50 52 A4 6A 14 09 5F 53 33 44 `}`aX2PR.j.._S3D
+ 1B10: 00 A4 0A 02 14 09 5F 53 34 44 00 A4 0A 02 5B 82 ......_S4D....[.
+ 1B20: 48 89 4C 50 43 42 08 5F 41 44 52 0C 00 00 1F 00 H.LPCB._ADR.....
+ 1B30: 5B 80 4C 50 43 30 02 00 0B 00 01 5B 81 4B 0A 4C [.LPC0.....[.K.L
+ 1B40: 50 43 30 00 00 40 20 50 4D 42 53 10 00 40 0F 50 PC0..@ PMBS..@.P
+ 1B50: 52 54 41 08 50 52 54 42 08 50 52 54 43 08 50 52 RTA.PRTB.PRTC.PR
+ 1B60: 54 44 08 00 20 50 52 54 45 08 50 52 54 46 08 50 TD.. PRTE.PRTF.P
+ 1B70: 52 54 47 08 50 52 54 48 08 00 40 0A 49 4F 44 30 RTG.PRTH..@.IOD0
+ 1B80: 08 49 4F 44 31 08 00 40 1B 47 52 30 30 02 47 52 .IOD1..@.GR00.GR
+ 1B90: 30 31 02 47 52 30 32 02 47 52 30 33 02 47 52 30 01.GR02.GR03.GR0
+ 1BA0: 34 02 47 52 30 35 02 47 52 30 36 02 47 52 30 37 4.GR05.GR06.GR07
+ 1BB0: 02 47 52 30 38 02 47 52 30 39 02 47 52 31 30 02 .GR08.GR09.GR10.
+ 1BC0: 47 52 31 31 02 47 52 31 32 02 47 52 31 33 02 47 GR11.GR12.GR13.G
+ 1BD0: 52 31 34 02 47 52 31 35 02 00 40 1A 52 43 45 4E R14.GR15..@.RCEN
+ 1BE0: 01 00 0D 52 43 42 41 12 5B 82 41 0A 4C 4E 4B 41 ...RCBA.[.A.LNKA
+ 1BF0: 08 5F 48 49 44 0C 41 D0 0C 0F 08 5F 55 49 44 01 ._HID.A...._UID.
+ 1C00: 14 0D 5F 44 49 53 08 70 0A 80 50 52 54 41 08 5F .._DIS.p..PRTA._
+ 1C10: 50 52 53 11 09 0A 06 23 F8 D4 18 79 00 14 38 5F PRS....#...y..8_
+ 1C20: 43 52 53 08 08 52 54 4C 41 11 09 0A 06 23 00 00 CRS..RTLA....#..
+ 1C30: 18 79 00 8B 52 54 4C 41 01 49 52 51 30 70 00 49 .y..RTLA.IRQ0p.I
+ 1C40: 52 51 30 79 01 7B 50 52 54 41 0A 0F 00 49 52 51 RQ0y.{PRTA...IRQ
+ 1C50: 30 A4 52 54 4C 41 14 1B 5F 53 52 53 09 8B 68 01 0.RTLA.._SRS..h.
+ 1C60: 49 52 51 30 82 49 52 51 30 60 76 60 70 60 50 52 IRQ0.IRQ0`v`p`PR
+ 1C70: 54 41 14 18 5F 53 54 41 08 A0 0C 7B 50 52 54 41 TA.._STA...{PRTA
+ 1C80: 0A 80 00 A4 0A 09 A1 04 A4 0A 0B 5B 82 42 0A 4C ...........[.B.L
+ 1C90: 4E 4B 42 08 5F 48 49 44 0C 41 D0 0C 0F 08 5F 55 NKB._HID.A...._U
+ 1CA0: 49 44 0A 02 14 0D 5F 44 49 53 08 70 0A 80 50 52 ID...._DIS.p..PR
+ 1CB0: 54 42 08 5F 50 52 53 11 09 0A 06 23 F8 D8 18 79 TB._PRS....#...y
+ 1CC0: 00 14 38 5F 43 52 53 08 08 52 54 4C 42 11 09 0A ..8_CRS..RTLB...
+ 1CD0: 06 23 00 00 18 79 00 8B 52 54 4C 42 01 49 52 51 .#...y..RTLB.IRQ
+ 1CE0: 30 70 00 49 52 51 30 79 01 7B 50 52 54 42 0A 0F 0p.IRQ0y.{PRTB..
+ 1CF0: 00 49 52 51 30 A4 52 54 4C 42 14 1B 5F 53 52 53 .IRQ0.RTLB.._SRS
+ 1D00: 09 8B 68 01 49 52 51 30 82 49 52 51 30 60 76 60 ..h.IRQ0.IRQ0`v`
+ 1D10: 70 60 50 52 54 42 14 18 5F 53 54 41 08 A0 0C 7B p`PRTB.._STA...{
+ 1D20: 50 52 54 42 0A 80 00 A4 0A 09 A1 04 A4 0A 0B 5B PRTB...........[
+ 1D30: 82 42 0A 4C 4E 4B 43 08 5F 48 49 44 0C 41 D0 0C .B.LNKC._HID.A..
+ 1D40: 0F 08 5F 55 49 44 0A 03 14 0D 5F 44 49 53 08 70 .._UID...._DIS.p
+ 1D50: 0A 80 50 52 54 43 08 5F 50 52 53 11 09 0A 06 23 ..PRTC._PRS....#
+ 1D60: F8 D4 18 79 00 14 38 5F 43 52 53 08 08 52 54 4C ...y..8_CRS..RTL
+ 1D70: 43 11 09 0A 06 23 00 00 18 79 00 8B 52 54 4C 43 C....#...y..RTLC
+ 1D80: 01 49 52 51 30 70 00 49 52 51 30 79 01 7B 50 52 .IRQ0p.IRQ0y.{PR
+ 1D90: 54 43 0A 0F 00 49 52 51 30 A4 52 54 4C 43 14 1B TC...IRQ0.RTLC..
+ 1DA0: 5F 53 52 53 09 8B 68 01 49 52 51 30 82 49 52 51 _SRS..h.IRQ0.IRQ
+ 1DB0: 30 60 76 60 70 60 50 52 54 43 14 18 5F 53 54 41 0`v`p`PRTC.._STA
+ 1DC0: 08 A0 0C 7B 50 52 54 43 0A 80 00 A4 0A 09 A1 04 ...{PRTC........
+ 1DD0: A4 0A 0B 5B 82 42 0A 4C 4E 4B 44 08 5F 48 49 44 ...[.B.LNKD._HID
+ 1DE0: 0C 41 D0 0C 0F 08 5F 55 49 44 0A 04 14 0D 5F 44 .A...._UID...._D
+ 1DF0: 49 53 08 70 0A 80 50 52 54 44 08 5F 50 52 53 11 IS.p..PRTD._PRS.
+ 1E00: 09 0A 06 23 F8 D8 18 79 00 14 38 5F 43 52 53 08 ...#...y..8_CRS.
+ 1E10: 08 52 54 4C 44 11 09 0A 06 23 00 00 18 79 00 8B .RTLD....#...y..
+ 1E20: 52 54 4C 44 01 49 52 51 30 70 00 49 52 51 30 79 RTLD.IRQ0p.IRQ0y
+ 1E30: 01 7B 50 52 54 44 0A 0F 00 49 52 51 30 A4 52 54 .{PRTD...IRQ0.RT
+ 1E40: 4C 44 14 1B 5F 53 52 53 09 8B 68 01 49 52 51 30 LD.._SRS..h.IRQ0
+ 1E50: 82 49 52 51 30 60 76 60 70 60 50 52 54 44 14 18 .IRQ0`v`p`PRTD..
+ 1E60: 5F 53 54 41 08 A0 0C 7B 50 52 54 44 0A 80 00 A4 _STA...{PRTD....
+ 1E70: 0A 09 A1 04 A4 0A 0B 5B 82 42 0A 4C 4E 4B 45 08 .......[.B.LNKE.
+ 1E80: 5F 48 49 44 0C 41 D0 0C 0F 08 5F 55 49 44 0A 05 _HID.A...._UID..
+ 1E90: 14 0D 5F 44 49 53 08 70 0A 80 50 52 54 45 08 5F .._DIS.p..PRTE._
+ 1EA0: 50 52 53 11 09 0A 06 23 F8 D4 18 79 00 14 38 5F PRS....#...y..8_
+ 1EB0: 43 52 53 08 08 52 54 4C 45 11 09 0A 06 23 00 00 CRS..RTLE....#..
+ 1EC0: 18 79 00 8B 52 54 4C 45 01 49 52 51 30 70 00 49 .y..RTLE.IRQ0p.I
+ 1ED0: 52 51 30 79 01 7B 50 52 54 45 0A 0F 00 49 52 51 RQ0y.{PRTE...IRQ
+ 1EE0: 30 A4 52 54 4C 45 14 1B 5F 53 52 53 09 8B 68 01 0.RTLE.._SRS..h.
+ 1EF0: 49 52 51 30 82 49 52 51 30 60 76 60 70 60 50 52 IRQ0.IRQ0`v`p`PR
+ 1F00: 54 45 14 18 5F 53 54 41 08 A0 0C 7B 50 52 54 45 TE.._STA...{PRTE
+ 1F10: 0A 80 00 A4 0A 09 A1 04 A4 0A 0B 5B 82 42 0A 4C ...........[.B.L
+ 1F20: 4E 4B 46 08 5F 48 49 44 0C 41 D0 0C 0F 08 5F 55 NKF._HID.A...._U
+ 1F30: 49 44 0A 06 14 0D 5F 44 49 53 08 70 0A 80 50 52 ID...._DIS.p..PR
+ 1F40: 54 46 08 5F 50 52 53 11 09 0A 06 23 F8 D8 18 79 TF._PRS....#...y
+ 1F50: 00 14 38 5F 43 52 53 08 08 52 54 4C 46 11 09 0A ..8_CRS..RTLF...
+ 1F60: 06 23 00 00 18 79 00 8B 52 54 4C 46 01 49 52 51 .#...y..RTLF.IRQ
+ 1F70: 30 70 00 49 52 51 30 79 01 7B 50 52 54 46 0A 0F 0p.IRQ0y.{PRTF..
+ 1F80: 00 49 52 51 30 A4 52 54 4C 46 14 1B 5F 53 52 53 .IRQ0.RTLF.._SRS
+ 1F90: 09 8B 68 01 49 52 51 30 82 49 52 51 30 60 76 60 ..h.IRQ0.IRQ0`v`
+ 1FA0: 70 60 50 52 54 46 14 18 5F 53 54 41 08 A0 0C 7B p`PRTF.._STA...{
+ 1FB0: 50 52 54 46 0A 80 00 A4 0A 09 A1 04 A4 0A 0B 5B PRTF...........[
+ 1FC0: 82 42 0A 4C 4E 4B 47 08 5F 48 49 44 0C 41 D0 0C .B.LNKG._HID.A..
+ 1FD0: 0F 08 5F 55 49 44 0A 07 14 0D 5F 44 49 53 08 70 .._UID...._DIS.p
+ 1FE0: 0A 80 50 52 54 47 08 5F 50 52 53 11 09 0A 06 23 ..PRTG._PRS....#
+ 1FF0: F8 D4 18 79 00 14 38 5F 43 52 53 08 08 52 54 4C ...y..8_CRS..RTL
+ 2000: 47 11 09 0A 06 23 00 00 18 79 00 8B 52 54 4C 47 G....#...y..RTLG
+ 2010: 01 49 52 51 30 70 00 49 52 51 30 79 01 7B 50 52 .IRQ0p.IRQ0y.{PR
+ 2020: 54 47 0A 0F 00 49 52 51 30 A4 52 54 4C 47 14 1B TG...IRQ0.RTLG..
+ 2030: 5F 53 52 53 09 8B 68 01 49 52 51 30 82 49 52 51 _SRS..h.IRQ0.IRQ
+ 2040: 30 60 76 60 70 60 50 52 54 47 14 18 5F 53 54 41 0`v`p`PRTG.._STA
+ 2050: 08 A0 0C 7B 50 52 54 47 0A 80 00 A4 0A 09 A1 04 ...{PRTG........
+ 2060: A4 0A 0B 5B 82 42 0A 4C 4E 4B 48 08 5F 48 49 44 ...[.B.LNKH._HID
+ 2070: 0C 41 D0 0C 0F 08 5F 55 49 44 0A 08 14 0D 5F 44 .A...._UID...._D
+ 2080: 49 53 08 70 0A 80 50 52 54 48 08 5F 50 52 53 11 IS.p..PRTH._PRS.
+ 2090: 09 0A 06 23 F8 D8 18 79 00 14 38 5F 43 52 53 08 ...#...y..8_CRS.
+ 20A0: 08 52 54 4C 48 11 09 0A 06 23 00 00 18 79 00 8B .RTLH....#...y..
+ 20B0: 52 54 4C 48 01 49 52 51 30 70 00 49 52 51 30 79 RTLH.IRQ0p.IRQ0y
+ 20C0: 01 7B 50 52 54 48 0A 0F 00 49 52 51 30 A4 52 54 .{PRTH...IRQ0.RT
+ 20D0: 4C 48 14 1B 5F 53 52 53 09 8B 68 01 49 52 51 30 LH.._SRS..h.IRQ0
+ 20E0: 82 49 52 51 30 60 76 60 70 60 50 52 54 48 14 18 .IRQ0`v`p`PRTH..
+ 20F0: 5F 53 54 41 08 A0 0C 7B 50 52 54 48 0A 80 00 A4 _STA...{PRTH....
+ 2100: 0A 09 A1 04 A4 0A 0B 5B 82 3D 44 4D 41 43 08 5F .......[.=DMAC._
+ 2110: 48 49 44 0C 41 D0 02 00 08 5F 43 52 53 11 28 0A HID.A...._CRS.(.
+ 2120: 25 47 01 00 00 00 00 01 20 47 01 81 00 81 00 01 %G...... G......
+ 2130: 11 47 01 93 00 93 00 01 0D 47 01 C0 00 C0 00 01 .G.......G......
+ 2140: 20 2A 10 01 79 00 5B 82 26 46 57 48 5F 08 5F 48 *..y.[.&FWH_._H
+ 2150: 49 44 0C 25 D4 08 00 08 5F 43 52 53 11 11 0A 0E ID.%...._CRS....
+ 2160: 86 09 00 00 00 00 00 FF 00 00 00 01 79 00 5B 82 ............y.[.
+ 2170: 4A 0A 48 50 45 54 08 5F 48 49 44 0C 41 D0 01 03 J.HPET._HID.A...
+ 2180: 08 5F 43 49 44 0C 41 D0 0C 01 08 42 55 46 30 11 ._CID.A....BUF0.
+ 2190: 11 0A 0E 86 09 00 00 00 00 D0 FE 00 04 00 00 79 ...............y
+ 21A0: 00 14 21 5F 53 54 41 00 A0 18 48 50 54 45 A0 0D ..!_STA...HPTE..
+ 21B0: 92 95 4F 53 59 53 0B D1 07 A4 0A 0F A1 04 A4 0A ..OSYS..........
+ 21C0: 0B A4 00 14 46 05 5F 43 52 53 08 A0 49 04 48 50 ....F._CRS..I.HP
+ 21D0: 54 45 8A 42 55 46 30 0A 04 48 50 54 30 A0 11 93 TE.BUF0..HPT0...
+ 21E0: 48 50 41 53 01 70 0C 00 10 D0 FE 48 50 54 30 A0 HPAS.p.....HPT0.
+ 21F0: 12 93 48 50 41 53 0A 02 70 0C 00 20 D0 FE 48 50 ..HPAS..p.. ..HP
+ 2200: 54 30 A0 12 93 48 50 41 53 0A 03 70 0C 00 30 D0 T0...HPAS..p..0.
+ 2210: FE 48 50 54 30 A4 42 55 46 30 5B 82 45 0A 50 49 .HPT0.BUF0[.E.PI
+ 2220: 43 5F 08 5F 48 49 44 0B 41 D0 08 5F 43 52 53 11 C_._HID.A.._CRS.
+ 2230: 41 09 0A 8D 47 01 20 00 20 00 01 02 47 01 24 00 A...G. . ...G.$.
+ 2240: 24 00 01 02 47 01 28 00 28 00 01 02 47 01 2C 00 $...G.(.(...G.,.
+ 2250: 2C 00 01 02 47 01 30 00 30 00 01 02 47 01 34 00 ,...G.0.0...G.4.
+ 2260: 34 00 01 02 47 01 38 00 38 00 01 02 47 01 3C 00 4...G.8.8...G.<.
+ 2270: 3C 00 01 02 47 01 A0 00 A0 00 01 02 47 01 A4 00 <...G.......G...
+ 2280: A4 00 01 02 47 01 A8 00 A8 00 01 02 47 01 AC 00 ....G.......G...
+ 2290: AC 00 01 02 47 01 B0 00 B0 00 01 02 47 01 B4 00 ....G.......G...
+ 22A0: B4 00 01 02 47 01 B8 00 B8 00 01 02 47 01 BC 00 ....G.......G...
+ 22B0: BC 00 01 02 47 01 D0 04 D0 04 01 02 22 04 00 79 ....G......."..y
+ 22C0: 00 5B 82 25 4D 41 54 48 08 5F 48 49 44 0C 41 D0 .[.%MATH._HID.A.
+ 22D0: 0C 04 08 5F 43 52 53 11 10 0A 0D 47 01 F0 00 F0 ..._CRS....G....
+ 22E0: 00 01 01 22 00 20 79 00 5B 82 4B 07 4C 44 52 43 ...". y.[.K.LDRC
+ 22F0: 08 5F 48 49 44 0C 41 D0 0C 02 08 5F 55 49 44 0A ._HID.A...._UID.
+ 2300: 02 08 5F 43 52 53 11 4E 05 0A 5A 47 01 2E 00 2E .._CRS.N..ZG....
+ 2310: 00 01 02 47 01 4E 00 4E 00 01 02 47 01 61 00 61 ...G.N.N...G.a.a
+ 2320: 00 01 01 47 01 63 00 63 00 01 01 47 01 65 00 65 ...G.c.c...G.e.e
+ 2330: 00 01 01 47 01 67 00 67 00 01 01 47 01 80 00 80 ...G.g.g...G....
+ 2340: 00 01 01 47 01 92 00 92 00 01 01 47 01 B2 00 B2 ...G.......G....
+ 2350: 00 01 02 47 01 00 05 00 05 01 80 47 01 80 04 80 ...G.......G....
+ 2360: 04 01 40 79 00 5B 82 22 52 54 43 5F 08 5F 48 49 ..@y.[."RTC_._HI
+ 2370: 44 0C 41 D0 0B 00 08 5F 43 52 53 11 0D 0A 0A 47 D.A...._CRS....G
+ 2380: 01 70 00 70 00 01 08 79 00 5B 82 2D 54 49 4D 52 .p.p...y.[.-TIMR
+ 2390: 08 5F 48 49 44 0C 41 D0 01 00 08 5F 43 52 53 11 ._HID.A...._CRS.
+ 23A0: 18 0A 15 47 01 40 00 40 00 01 04 47 01 50 00 50 ...G.@.@...G.P.P
+ 23B0: 00 10 04 22 01 00 79 00 5B 82 0F 53 41 54 41 08 ..."..y.[..SATA.
+ 23C0: 5F 41 44 52 0C 02 00 1F 00 5B 82 0F 53 42 55 53 _ADR.....[..SBUS
+ 23D0: 08 5F 41 44 52 0C 03 00 1F 00 14 4B 05 5F 4F 53 ._ADR......K._OS
+ 23E0: 43 04 A0 25 93 68 11 13 0A 10 A9 12 95 7C 05 17 C..%.h.......|..
+ 23F0: B4 4C AF 7D 50 6A 24 23 AB 71 A4 5E 2E 58 48 43 .L.}Pj$#.q.^.XHC
+ 2400: 5F 50 4F 53 43 69 6A 6B A0 19 93 68 11 13 0A 10 _POSCijk...h....
+ 2410: 5B 4D DB 33 F7 1F 1C 40 96 57 74 41 C0 3D D7 66 [M.3...@.WtA.=.f
+ 2420: A4 6B 8A 6B 00 43 44 57 31 7D 43 44 57 31 0A 04 .k.k.CDW1}CDW1..
+ 2430: 43 44 57 31 A4 6B 14 43 1C 5F 50 52 54 00 A0 4B CDW1.k.C._PRT..K
+ 2440: 0A 50 49 43 4D A4 12 43 0A 0D 12 0B 04 0C FF FF .PICM..C........
+ 2450: 02 00 00 00 0A 10 12 0B 04 0C FF FF 14 00 00 00 ................
+ 2460: 0A 13 12 0B 04 0C FF FF 1B 00 00 00 0A 10 12 0B ................
+ 2470: 04 0C FF FF 1C 00 00 00 0A 11 12 0B 04 0C FF FF ................
+ 2480: 1C 00 01 00 0A 15 12 0C 04 0C FF FF 1C 00 0A 02 ................
+ 2490: 00 0A 13 12 0C 04 0C FF FF 1C 00 0A 03 00 0A 14 ................
+ 24A0: 12 0B 04 0C FF FF 1D 00 00 00 0A 13 12 0B 04 0C ................
+ 24B0: FF FF 1A 00 00 00 0A 15 12 0B 04 0C FF FF 1F 00 ................
+ 24C0: 00 00 0A 11 12 0B 04 0C FF FF 1F 00 01 00 0A 17 ................
+ 24D0: 12 0C 04 0C FF FF 1F 00 0A 02 00 0A 10 12 0C 04 ................
+ 24E0: 0C FF FF 1F 00 0A 03 00 0A 12 A1 4F 10 A4 12 4B ...........O...K
+ 24F0: 10 0D 12 13 04 0C FF FF 02 00 00 5E 2E 4C 50 43 ...........^.LPC
+ 2500: 42 4C 4E 4B 41 00 12 13 04 0C FF FF 14 00 00 5E BLNKA..........^
+ 2510: 2E 4C 50 43 42 4C 4E 4B 44 00 12 13 04 0C FF FF .LPCBLNKD.......
+ 2520: 1B 00 00 5E 2E 4C 50 43 42 4C 4E 4B 41 00 12 13 ...^.LPCBLNKA...
+ 2530: 04 0C FF FF 1C 00 00 5E 2E 4C 50 43 42 4C 4E 4B .......^.LPCBLNK
+ 2540: 42 00 12 13 04 0C FF FF 1C 00 01 5E 2E 4C 50 43 B..........^.LPC
+ 2550: 42 4C 4E 4B 46 00 12 14 04 0C FF FF 1C 00 0A 02 BLNKF...........
+ 2560: 5E 2E 4C 50 43 42 4C 4E 4B 44 00 12 14 04 0C FF ^.LPCBLNKD......
+ 2570: FF 1C 00 0A 03 5E 2E 4C 50 43 42 4C 4E 4B 45 00 .....^.LPCBLNKE.
+ 2580: 12 13 04 0C FF FF 1D 00 00 5E 2E 4C 50 43 42 4C .........^.LPCBL
+ 2590: 4E 4B 44 00 12 13 04 0C FF FF 1A 00 00 5E 2E 4C NKD..........^.L
+ 25A0: 50 43 42 4C 4E 4B 46 00 12 13 04 0C FF FF 1F 00 PCBLNKF.........
+ 25B0: 00 5E 2E 4C 50 43 42 4C 4E 4B 42 00 12 13 04 0C .^.LPCBLNKB.....
+ 25C0: FF FF 1F 00 01 5E 2E 4C 50 43 42 4C 4E 4B 48 00 .....^.LPCBLNKH.
+ 25D0: 12 14 04 0C FF FF 1F 00 0A 02 5E 2E 4C 50 43 42 ..........^.LPCB
+ 25E0: 4C 4E 4B 41 00 12 14 04 0C FF FF 1F 00 0A 03 5E LNKA...........^
+ 25F0: 2E 4C 50 43 42 4C 4E 4B 43 00 10 31 47 46 58 30 .LPCBLNKC..1GFX0
+ 2600: 08 42 52 49 47 12 26 12 0A 64 0A 64 0A 02 0A 04 .BRIG.&..d.d....
+ 2610: 0A 05 0A 07 0A 09 0A 0B 0A 0D 0A 12 0A 14 0A 18 ................
+ 2620: 0A 1D 0A 21 0A 28 0A 32 0A 43 0A 64 ...!.(.2.C.d
+
+FACS @ 0x00000000BFEB9240
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
+
+FACP @ 0x00000000BFEBB8B0
+ 0000: 46 41 43 50 F4 00 00 00 04 7B 43 4F 52 45 20 20 FACP.....{CORE
+ 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 COREBOOT....CORE
+ 0020: 00 00 00 00 40 92 EB BF 80 92 EB BF 01 01 09 00 ....@...........
+ 0030: B2 00 00 00 E1 1E 00 00 00 05 00 00 00 00 00 00 ................
+ 0040: 04 05 00 00 00 00 00 00 50 05 00 00 08 05 00 00 ........P.......
+ 0050: 20 05 00 00 00 00 00 00 04 02 01 04 10 00 00 00 ...............
+ 0060: 65 00 57 00 00 04 10 00 01 00 0D 00 00 03 00 00 e.W.............
+ 0070: A5 8C 00 00 01 08 00 01 F9 0C 00 00 00 00 00 00 ................
+ 0080: 06 00 00 00 40 92 EB BF 00 00 00 00 80 92 EB BF ....@...........
+ 0090: 00 00 00 00 01 20 00 03 00 05 00 00 00 00 00 00 ..... ..........
+ 00A0: 01 00 00 00 00 00 00 00 00 00 00 00 01 10 00 02 ................
+ 00B0: 04 05 00 00 00 00 00 00 01 00 00 00 00 00 00 00 ................
+ 00C0: 00 00 00 00 01 08 00 01 50 05 00 00 00 00 00 00 ........P.......
+ 00D0: 01 20 00 03 08 05 00 00 00 00 00 00 01 80 00 03 . ..............
+ 00E0: 20 05 00 00 00 00 00 00 01 00 00 00 00 00 00 00 ...............
+ 00F0: 00 00 00 00 ....
+
+SSDT @ 0x00000000BFEBB9B0
+ 0000: 53 53 44 54 7D 27 00 00 02 CE 43 4F 52 45 20 20 SSDT}'....CORE
+ 0010: 43 4F 52 45 42 4F 4F 54 2A 00 00 00 43 4F 52 45 COREBOOT*...CORE
+ 0020: 2A 00 00 00 5B 83 81 4B 00 5C 2E 5F 50 52 5F 43 *...[..K.\._PR_C
+ 0030: 50 30 30 00 10 05 00 00 06 08 5F 50 43 54 12 2C P00......._PCT.,
+ 0040: 02 11 14 0A 11 82 0C 00 7F 00 00 00 00 00 00 00 ................
+ 0050: 00 00 00 00 79 00 11 14 0A 11 82 0C 00 7F 00 00 ....y...........
+ 0060: 00 00 00 00 00 00 00 00 00 79 00 14 8D 00 00 5F .........y....._
+ 0070: 50 50 43 00 A4 50 50 43 4D 08 5F 50 53 44 12 8C PPC..PPCM._PSD..
+ 0080: 01 00 01 12 87 01 00 05 0A 05 0A 00 0C 00 00 00 ................
+ 0090: 00 0C FE 00 00 00 0C 08 00 00 00 08 5F 50 53 53 ............_PSS
+ 00A0: 12 86 0D 00 06 12 82 02 00 06 0C 49 0D 00 00 0C ...........I....
+ 00B0: C8 2C 01 00 0C 0A 00 00 00 0C 0A 00 00 00 0C 00 .,..............
+ 00C0: 27 00 00 0C 00 27 00 00 12 82 02 00 06 0C 48 0D '....'........H.
+ 00D0: 00 00 0C C8 2C 01 00 0C 0A 00 00 00 0C 0A 00 00 ....,...........
+ 00E0: 00 0C 00 22 00 00 0C 00 22 00 00 12 82 02 00 06 ..."....".......
+ 00F0: 0C F0 0A 00 00 0C B5 E6 00 00 0C 0A 00 00 00 0C ................
+ 0100: 0A 00 00 00 0C 00 1C 00 00 0C 00 1C 00 00 12 82 ................
+ 0110: 02 00 06 0C 60 09 00 00 0C 83 BC 00 00 0C 0A 00 ....`...........
+ 0120: 00 00 0C 0A 00 00 00 0C 00 18 00 00 0C 00 18 00 ................
+ 0130: 00 12 82 02 00 06 0C D0 07 00 00 0C CC 95 00 00 ................
+ 0140: 0C 0A 00 00 00 0C 0A 00 00 00 0C 00 14 00 00 0C ................
+ 0150: 00 14 00 00 12 82 02 00 06 0C 40 06 00 00 0C CC ..........@.....
+ 0160: 71 00 00 0C 0A 00 00 00 0C 0A 00 00 00 0C 00 10 q...............
+ 0170: 00 00 0C 00 10 00 00 14 88 12 00 5F 43 53 54 00 ..........._CST.
+ 0180: A0 83 09 00 50 57 52 53 A4 12 8A 08 00 04 0A 03 ....PWRS........
+ 0190: 12 8B 02 00 04 11 87 01 00 0B 13 00 82 0C 00 7F ................
+ 01A0: 01 02 01 00 00 00 00 00 00 00 00 79 00 0C 01 00 ...........y....
+ 01B0: 00 00 0C 01 00 00 00 0C E8 03 00 00 12 8B 02 00 ................
+ 01C0: 04 11 87 01 00 0B 13 00 82 0C 00 7F 01 02 01 10 ................
+ 01D0: 00 00 00 00 00 00 00 79 00 0C 02 00 00 00 0C 3F .......y.......?
+ 01E0: 00 00 00 0C F4 01 00 00 12 8B 02 00 04 11 87 01 ................
+ 01F0: 00 0B 13 00 82 0C 00 7F 01 02 01 30 00 00 00 00 ...........0....
+ 0200: 00 00 00 79 00 0C 03 00 00 00 0C 5A 00 00 00 0C ...y.......Z....
+ 0210: C8 00 00 00 A4 12 8A 08 00 04 0A 03 12 8B 02 00 ................
+ 0220: 04 11 87 01 00 0B 13 00 82 0C 00 7F 01 02 01 00 ................
+ 0230: 00 00 00 00 00 00 00 79 00 0C 01 00 00 00 0C 01 .......y........
+ 0240: 00 00 00 0C E8 03 00 00 12 8B 02 00 04 11 87 01 ................
+ 0250: 00 0B 13 00 82 0C 00 7F 01 02 01 10 00 00 00 00 ................
+ 0260: 00 00 00 79 00 0C 02 00 00 00 0C 3F 00 00 00 0C ...y.......?....
+ 0270: F4 01 00 00 12 8B 02 00 04 11 87 01 00 0B 13 00 ................
+ 0280: 82 0C 00 7F 01 02 01 30 00 00 00 00 00 00 00 79 .......0.......y
+ 0290: 00 0C 03 00 00 00 0C 5A 00 00 00 0C C8 00 00 00 .......Z........
+ 02A0: 08 5F 54 53 44 12 8C 01 00 01 12 87 01 00 05 0A ._TSD...........
+ 02B0: 05 0A 00 0C 00 00 00 00 0C FC 00 00 00 0C 08 00 ................
+ 02C0: 00 00 08 5F 50 54 43 12 84 03 00 02 11 87 01 00 ..._PTC.........
+ 02D0: 0B 13 00 82 0C 00 7F 00 00 00 00 00 00 00 00 00 ................
+ 02E0: 00 00 79 00 11 87 01 00 0B 13 00 82 0C 00 7F 00 ..y.............
+ 02F0: 00 00 00 00 00 00 00 00 00 00 79 00 14 8E 00 00 ..........y.....
+ 0300: 5F 54 50 43 00 A4 5C 54 4C 56 4C 08 5F 54 53 53 _TPC..\TLVL._TSS
+ 0310: 12 86 1C 00 0F 12 8D 01 00 05 0C 64 00 00 00 0C ...........d....
+ 0320: E8 03 00 00 0C 00 00 00 00 0C 00 00 00 00 0C 00 ................
+ 0330: 00 00 00 12 8D 01 00 05 0C 5E 00 00 00 0C AC 03 .........^......
+ 0340: 00 00 0C 00 00 00 00 0C 1F 00 00 00 0C 00 00 00 ................
+ 0350: 00 12 8D 01 00 05 0C 58 00 00 00 0C 70 03 00 00 .......X....p...
+ 0360: 0C 00 00 00 00 0C 1E 00 00 00 0C 00 00 00 00 12 ................
+ 0370: 8D 01 00 05 0C 52 00 00 00 0C 34 03 00 00 0C 00 .....R....4.....
+ 0380: 00 00 00 0C 1D 00 00 00 0C 00 00 00 00 12 8D 01 ................
+ 0390: 00 05 0C 4B 00 00 00 0C F8 02 00 00 0C 00 00 00 ...K............
+ 03A0: 00 0C 1C 00 00 00 0C 00 00 00 00 12 8D 01 00 05 ................
+ 03B0: 0C 45 00 00 00 0C BC 02 00 00 0C 00 00 00 00 0C .E..............
+ 03C0: 1B 00 00 00 0C 00 00 00 00 12 8D 01 00 05 0C 3F ...............?
+ 03D0: 00 00 00 0C 80 02 00 00 0C 00 00 00 00 0C 1A 00 ................
+ 03E0: 00 00 0C 00 00 00 00 12 8D 01 00 05 0C 39 00 00 .............9..
+ 03F0: 00 0C 44 02 00 00 0C 00 00 00 00 0C 19 00 00 00 ..D.............
+ 0400: 0C 00 00 00 00 12 8D 01 00 05 0C 32 00 00 00 0C ...........2....
+ 0410: 08 02 00 00 0C 00 00 00 00 0C 18 00 00 00 0C 00 ................
+ 0420: 00 00 00 12 8D 01 00 05 0C 2C 00 00 00 0C CC 01 .........,......
+ 0430: 00 00 0C 00 00 00 00 0C 17 00 00 00 0C 00 00 00 ................
+ 0440: 00 12 8D 01 00 05 0C 26 00 00 00 0C 90 01 00 00 .......&........
+ 0450: 0C 00 00 00 00 0C 16 00 00 00 0C 00 00 00 00 12 ................
+ 0460: 8D 01 00 05 0C 20 00 00 00 0C 54 01 00 00 0C 00 ..... ....T.....
+ 0470: 00 00 00 0C 15 00 00 00 0C 00 00 00 00 12 8D 01 ................
+ 0480: 00 05 0C 19 00 00 00 0C 18 01 00 00 0C 00 00 00 ................
+ 0490: 00 0C 14 00 00 00 0C 00 00 00 00 12 8D 01 00 05 ................
+ 04A0: 0C 13 00 00 00 0C DC 00 00 00 0C 00 00 00 00 0C ................
+ 04B0: 13 00 00 00 0C 00 00 00 00 12 8D 01 00 05 0C 0D ................
+ 04C0: 00 00 00 0C A0 00 00 00 0C 00 00 00 00 0C 12 00 ................
+ 04D0: 00 00 0C 00 00 00 00 5B 83 81 4B 00 5C 2E 5F 50 .......[..K.\._P
+ 04E0: 52 5F 43 50 30 31 01 00 00 00 00 00 08 5F 50 43 R_CP01......._PC
+ 04F0: 54 12 2C 02 11 14 0A 11 82 0C 00 7F 00 00 00 00 T.,.............
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+ 0510: 7F 00 00 00 00 00 00 00 00 00 00 00 79 00 14 8D ............y...
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+ 2690: 00 00 14 8F 00 00 5F 42 43 4C 00 A4 5E 5E 58 42 ......_BCL..^^XB
+ 26A0: 43 4C 14 8F 00 00 5F 42 43 4D 01 5E 5E 58 42 43 CL...._BCM.^^XBC
+ 26B0: 4D 68 14 8F 00 00 5F 42 51 43 00 A4 5E 5E 58 42 Mh...._BQC..^^XB
+ 26C0: 51 43 14 81 01 00 5F 44 43 53 00 A4 5E 5E 58 44 QC...._DCS..^^XD
+ 26D0: 43 53 0A 02 14 81 01 00 5F 44 47 53 00 A4 5E 5E CS......_DGS..^^
+ 26E0: 58 44 47 53 0A 02 14 81 01 00 5F 44 53 53 00 5E XDGS......_DSS.^
+ 26F0: 5E 58 44 53 53 0A 02 68 10 84 08 00 5C 2F 03 5F ^XDSS..h....\/._
+ 2700: 53 42 5F 50 43 49 30 53 41 54 41 5B 82 81 01 00 SB_PCI0SATA[....
+ 2710: 50 52 30 30 08 5F 41 44 52 0C FF FF 00 00 5B 82 PR00._ADR.....[.
+ 2720: 81 01 00 50 52 30 31 08 5F 41 44 52 0C FF FF 01 ...PR01._ADR....
+ 2730: 00 5B 82 81 01 00 50 52 30 32 08 5F 41 44 52 0C .[....PR02._ADR.
+ 2740: FF FF 02 00 5B 82 81 01 00 50 52 30 33 08 5F 41 ....[....PR03._A
+ 2750: 44 52 0C FF FF 03 00 5B 82 81 01 00 50 52 30 34 DR.....[....PR04
+ 2760: 08 5F 41 44 52 0C FF FF 04 00 5B 82 81 01 00 50 ._ADR.....[....P
+ 2770: 52 30 35 08 5F 41 44 52 0C FF FF 05 00 R05._ADR.....
+
+TCPA @ 0x00000000BFEBE130
+ 0000: 54 43 50 41 32 00 00 00 02 AB 43 4F 52 45 20 20 TCPA2.....CORE
+ 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 COREBOOT....CORE
+ 0020: 00 00 00 00 00 00 00 00 01 00 00 60 EA BF 00 00 ...........`....
+ 0030: 00 00 ..
+
+APIC @ 0x00000000BFEBE170
+ 0000: 41 50 49 43 8C 00 00 00 01 02 43 4F 52 45 20 20 APIC......CORE
+ 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 COREBOOT....CORE
+ 0020: 00 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 ................
+ 0030: 01 00 00 00 00 08 01 01 01 00 00 00 00 08 02 02 ................
+ 0040: 01 00 00 00 00 08 03 03 01 00 00 00 00 08 04 04 ................
+ 0050: 01 00 00 00 00 08 05 05 01 00 00 00 00 08 06 06 ................
+ 0060: 01 00 00 00 00 08 07 07 01 00 00 00 01 0C 02 00 ................
+ 0070: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 ................
+ 0080: 00 00 02 0A 00 09 09 00 00 00 0D 00 ............
+
+DMAR @ 0x00000000BFEBE200
+ 0000: 44 4D 41 52 A8 00 00 00 01 E4 43 4F 52 45 20 20 DMAR......CORE
+ 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 COREBOOT....CORE
+ 0020: 00 00 00 00 27 01 00 00 00 00 00 00 00 00 00 00 ....'...........
+ 0030: 00 00 20 00 00 00 00 00 00 00 D9 FE 00 00 00 00 .. .............
+ 0040: 01 08 00 00 00 00 02 00 01 08 00 00 00 00 02 01 ................
+ 0050: 00 00 58 00 01 00 00 00 00 10 D9 FE 00 00 00 00 ..X.............
+ 0060: 03 08 00 00 02 FA 1F 00 04 08 00 00 00 FA 0F 00 ................
+ 0070: 04 08 00 00 00 FA 0F 01 04 08 00 00 00 FA 0F 02 ................
+ 0080: 04 08 00 00 00 FA 0F 03 04 08 00 00 00 FA 0F 04 ................
+ 0090: 04 08 00 00 00 FA 0F 05 04 08 00 00 00 FA 0F 06 ................
+ 00A0: 04 08 00 00 00 FA 0F 07 ........
+
+HPET @ 0x00000000BFEBE2B0
+ 0000: 48 50 45 54 38 00 00 00 01 6B 43 4F 52 45 20 20 HPET8....kCORE
+ 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 COREBOOT....CORE
+ 0020: 00 00 00 00 01 A7 86 80 00 40 00 00 00 00 D0 FE .........@......
+ 0030: 00 00 00 00 00 80 00 00 ........
+
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/apic.dat b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/apic.dat
new file mode 100644
index 0000000..fe353b1
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/apic.dat
Binary files differ
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/apic.dsl b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/apic.dsl
new file mode 100644
index 0000000..ff15a83
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/apic.dsl
@@ -0,0 +1,118 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML Disassembler version 20140214-64 [Mar 29 2014]
+ * Copyright (c) 2000 - 2014 Intel Corporation
+ *
+ * Disassembly of ./apic.dat, Sun Dec 27 13:15:45 2015
+ *
+ * ACPI Data Table [APIC]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)]
+[004h 0004 4] Table Length : 0000008C
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 02
+[00Ah 0010 6] Oem ID : "CORE "
+[010h 0016 8] Oem Table ID : "COREBOOT"
+[018h 0024 4] Oem Revision : 00000000
+[01Ch 0028 4] Asl Compiler ID : "CORE"
+[020h 0032 4] Asl Compiler Revision : 00000000
+
+[024h 0036 4] Local Apic Address : FEE00000
+[028h 0040 4] Flags (decoded below) : 00000001
+ PC-AT Compatibility : 1
+
+[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC]
+[02Dh 0045 1] Length : 08
+[02Eh 0046 1] Processor ID : 00
+[02Fh 0047 1] Local Apic ID : 00
+[030h 0048 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+
+[034h 0052 1] Subtable Type : 00 [Processor Local APIC]
+[035h 0053 1] Length : 08
+[036h 0054 1] Processor ID : 01
+[037h 0055 1] Local Apic ID : 01
+[038h 0056 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+
+[03Ch 0060 1] Subtable Type : 00 [Processor Local APIC]
+[03Dh 0061 1] Length : 08
+[03Eh 0062 1] Processor ID : 02
+[03Fh 0063 1] Local Apic ID : 02
+[040h 0064 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+
+[044h 0068 1] Subtable Type : 00 [Processor Local APIC]
+[045h 0069 1] Length : 08
+[046h 0070 1] Processor ID : 03
+[047h 0071 1] Local Apic ID : 03
+[048h 0072 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+
+[04Ch 0076 1] Subtable Type : 00 [Processor Local APIC]
+[04Dh 0077 1] Length : 08
+[04Eh 0078 1] Processor ID : 04
+[04Fh 0079 1] Local Apic ID : 04
+[050h 0080 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+
+[054h 0084 1] Subtable Type : 00 [Processor Local APIC]
+[055h 0085 1] Length : 08
+[056h 0086 1] Processor ID : 05
+[057h 0087 1] Local Apic ID : 05
+[058h 0088 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+
+[05Ch 0092 1] Subtable Type : 00 [Processor Local APIC]
+[05Dh 0093 1] Length : 08
+[05Eh 0094 1] Processor ID : 06
+[05Fh 0095 1] Local Apic ID : 06
+[060h 0096 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+
+[064h 0100 1] Subtable Type : 00 [Processor Local APIC]
+[065h 0101 1] Length : 08
+[066h 0102 1] Processor ID : 07
+[067h 0103 1] Local Apic ID : 07
+[068h 0104 4] Flags (decoded below) : 00000001
+ Processor Enabled : 1
+
+[06Ch 0108 1] Subtable Type : 01 [I/O APIC]
+[06Dh 0109 1] Length : 0C
+[06Eh 0110 1] I/O Apic ID : 02
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Address : FEC00000
+[074h 0116 4] Interrupt : 00000000
+
+[078h 0120 1] Subtable Type : 02 [Interrupt Source Override]
+[079h 0121 1] Length : 0A
+[07Ah 0122 1] Bus : 00
+[07Bh 0123 1] Source : 00
+[07Ch 0124 4] Interrupt : 00000002
+[080h 0128 2] Flags (decoded below) : 0000
+ Polarity : 0
+ Trigger Mode : 0
+
+[082h 0130 1] Subtable Type : 02 [Interrupt Source Override]
+[083h 0131 1] Length : 0A
+[084h 0132 1] Bus : 00
+[085h 0133 1] Source : 09
+[086h 0134 4] Interrupt : 00000009
+[08Ah 0138 2] Flags (decoded below) : 000D
+ Polarity : 1
+ Trigger Mode : 3
+
+Raw Table Data: Length 140 (0x8C)
+
+ 0000: 41 50 49 43 8C 00 00 00 01 02 43 4F 52 45 20 20 APIC......CORE
+ 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 COREBOOT....CORE
+ 0020: 00 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 ................
+ 0030: 01 00 00 00 00 08 01 01 01 00 00 00 00 08 02 02 ................
+ 0040: 01 00 00 00 00 08 03 03 01 00 00 00 00 08 04 04 ................
+ 0050: 01 00 00 00 00 08 05 05 01 00 00 00 00 08 06 06 ................
+ 0060: 01 00 00 00 00 08 07 07 01 00 00 00 01 0C 02 00 ................
+ 0070: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 ................
+ 0080: 00 00 02 0A 00 09 09 00 00 00 0D 00 ............
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/dmar.dat b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/dmar.dat
new file mode 100644
index 0000000..39d5f17
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/dmar.dat
Binary files differ
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/dmar.dsl b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/dmar.dsl
new file mode 100644
index 0000000..9f810af
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/dmar.dsl
@@ -0,0 +1,154 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML Disassembler version 20140214-64 [Mar 29 2014]
+ * Copyright (c) 2000 - 2014 Intel Corporation
+ *
+ * Disassembly of ./dmar.dat, Sun Dec 27 13:15:45 2015
+ *
+ * ACPI Data Table [DMAR]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "DMAR" [DMA Remapping table]
+[004h 0004 4] Table Length : 000000A8
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : E4
+[00Ah 0010 6] Oem ID : "CORE "
+[010h 0016 8] Oem Table ID : "COREBOOT"
+[018h 0024 4] Oem Revision : 00000000
+[01Ch 0028 4] Asl Compiler ID : "CORE"
+[020h 0032 4] Asl Compiler Revision : 00000000
+
+[024h 0036 1] Host Address Width : 27
+[025h 0037 1] Flags : 01
+[026h 0038 10] Reserved : 00 00 00 00 00 00 00 00 00 00
+
+[030h 0048 2] Subtable Type : 0000 [Hardware Unit Definition]
+[032h 0050 2] Length : 0020
+
+[034h 0052 1] Flags : 00
+[035h 0053 1] Reserved : 00
+[036h 0054 2] PCI Segment Number : 0000
+[038h 0056 8] Register Base Address : 00000000FED90000
+
+[040h 0064 1] Device Scope Entry Type : 01
+[041h 0065 1] Entry Length : 08
+[042h 0066 2] Reserved : 0000
+[044h 0068 1] Enumeration ID : 00
+[045h 0069 1] PCI Bus Number : 00
+
+[046h 0070 2] PCI Path : 02,00
+
+
+[048h 0072 1] Device Scope Entry Type : 01
+[049h 0073 1] Entry Length : 08
+[04Ah 0074 2] Reserved : 0000
+[04Ch 0076 1] Enumeration ID : 00
+[04Dh 0077 1] PCI Bus Number : 00
+
+[04Eh 0078 2] PCI Path : 02,01
+
+
+[050h 0080 2] Subtable Type : 0000 [Hardware Unit Definition]
+[052h 0082 2] Length : 0058
+
+[054h 0084 1] Flags : 01
+[055h 0085 1] Reserved : 00
+[056h 0086 2] PCI Segment Number : 0000
+[058h 0088 8] Register Base Address : 00000000FED91000
+
+[060h 0096 1] Device Scope Entry Type : 03
+[061h 0097 1] Entry Length : 08
+[062h 0098 2] Reserved : 0000
+[064h 0100 1] Enumeration ID : 02
+[065h 0101 1] PCI Bus Number : FA
+
+[066h 0102 2] PCI Path : 1F,00
+
+
+[068h 0104 1] Device Scope Entry Type : 04
+[069h 0105 1] Entry Length : 08
+[06Ah 0106 2] Reserved : 0000
+[06Ch 0108 1] Enumeration ID : 00
+[06Dh 0109 1] PCI Bus Number : FA
+
+[06Eh 0110 2] PCI Path : 0F,00
+
+
+[070h 0112 1] Device Scope Entry Type : 04
+[071h 0113 1] Entry Length : 08
+[072h 0114 2] Reserved : 0000
+[074h 0116 1] Enumeration ID : 00
+[075h 0117 1] PCI Bus Number : FA
+
+[076h 0118 2] PCI Path : 0F,01
+
+
+[078h 0120 1] Device Scope Entry Type : 04
+[079h 0121 1] Entry Length : 08
+[07Ah 0122 2] Reserved : 0000
+[07Ch 0124 1] Enumeration ID : 00
+[07Dh 0125 1] PCI Bus Number : FA
+
+[07Eh 0126 2] PCI Path : 0F,02
+
+
+[080h 0128 1] Device Scope Entry Type : 04
+[081h 0129 1] Entry Length : 08
+[082h 0130 2] Reserved : 0000
+[084h 0132 1] Enumeration ID : 00
+[085h 0133 1] PCI Bus Number : FA
+
+[086h 0134 2] PCI Path : 0F,03
+
+
+[088h 0136 1] Device Scope Entry Type : 04
+[089h 0137 1] Entry Length : 08
+[08Ah 0138 2] Reserved : 0000
+[08Ch 0140 1] Enumeration ID : 00
+[08Dh 0141 1] PCI Bus Number : FA
+
+[08Eh 0142 2] PCI Path : 0F,04
+
+
+[090h 0144 1] Device Scope Entry Type : 04
+[091h 0145 1] Entry Length : 08
+[092h 0146 2] Reserved : 0000
+[094h 0148 1] Enumeration ID : 00
+[095h 0149 1] PCI Bus Number : FA
+
+[096h 0150 2] PCI Path : 0F,05
+
+
+[098h 0152 1] Device Scope Entry Type : 04
+[099h 0153 1] Entry Length : 08
+[09Ah 0154 2] Reserved : 0000
+[09Ch 0156 1] Enumeration ID : 00
+[09Dh 0157 1] PCI Bus Number : FA
+
+[09Eh 0158 2] PCI Path : 0F,06
+
+
+[0A0h 0160 1] Device Scope Entry Type : 04
+[0A1h 0161 1] Entry Length : 08
+[0A2h 0162 2] Reserved : 0000
+[0A4h 0164 1] Enumeration ID : 00
+[0A5h 0165 1] PCI Bus Number : FA
+
+[0A6h 0166 2] PCI Path : 0F,07
+
+
+Raw Table Data: Length 168 (0xA8)
+
+ 0000: 44 4D 41 52 A8 00 00 00 01 E4 43 4F 52 45 20 20 DMAR......CORE
+ 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 COREBOOT....CORE
+ 0020: 00 00 00 00 27 01 00 00 00 00 00 00 00 00 00 00 ....'...........
+ 0030: 00 00 20 00 00 00 00 00 00 00 D9 FE 00 00 00 00 .. .............
+ 0040: 01 08 00 00 00 00 02 00 01 08 00 00 00 00 02 01 ................
+ 0050: 00 00 58 00 01 00 00 00 00 10 D9 FE 00 00 00 00 ..X.............
+ 0060: 03 08 00 00 02 FA 1F 00 04 08 00 00 00 FA 0F 00 ................
+ 0070: 04 08 00 00 00 FA 0F 01 04 08 00 00 00 FA 0F 02 ................
+ 0080: 04 08 00 00 00 FA 0F 03 04 08 00 00 00 FA 0F 04 ................
+ 0090: 04 08 00 00 00 FA 0F 05 04 08 00 00 00 FA 0F 06 ................
+ 00A0: 04 08 00 00 00 FA 0F 07 ........
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/dsdt.dat b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/dsdt.dat
new file mode 100644
index 0000000..0e943a5
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/dsdt.dat
Binary files differ
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/dsdt.dsl b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/dsdt.dsl
new file mode 100644
index 0000000..a003eee
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/dsdt.dsl
@@ -0,0 +1,2992 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML Disassembler version 20140214-64 [Mar 29 2014]
+ * Copyright (c) 2000 - 2014 Intel Corporation
+ *
+ * Disassembly of ./dsdt.dat, Sun Dec 27 13:15:45 2015
+ *
+ * Original Table Header:
+ * Signature "DSDT"
+ * Length 0x0000262C (9772)
+ * Revision 0x03
+ * Checksum 0x92
+ * OEM ID "COREv4"
+ * OEM Table ID "COREBOOT"
+ * OEM Revision 0x20141018 (538185752)
+ * Compiler ID "INTL"
+ * Compiler Version 0x20150619 (538248729)
+ */
+DefinitionBlock ("./dsdt.aml", "DSDT", 3, "COREv4", "COREBOOT", 0x20141018)
+{
+
+ External (_PR_.CP00)
+ External (_PR_.CP00._PSS)
+ External (_PR_.CP01)
+ External (_PR_.CP02)
+ External (_PR_.CP03)
+ External (_PR_.CP04)
+ External (_PR_.CP05)
+ External (_PR_.CP06)
+ External (_PR_.CP07)
+ External (_TZ_.SKIN)
+ External (_TZ_.THRM)
+ External (LCD0)
+
+ Scope (\)
+ {
+ Name (NVSA, 0xBFEB8000)
+ }
+
+ OperationRegion (APMP, SystemIO, 0xB2, 0x02)
+ Field (APMP, ByteAcc, NoLock, Preserve)
+ {
+ APMC, 8,
+ APMS, 8
+ }
+
+ OperationRegion (POST, SystemIO, 0x80, One)
+ Field (POST, ByteAcc, Lock, Preserve)
+ {
+ DBG0, 8
+ }
+
+ Method (TRAP, 1, Serialized)
+ {
+ Store (Arg0, SMIF)
+ Store (Zero, TRP0)
+ Return (SMIF)
+ }
+
+ Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model
+ {
+ Store (Arg0, PICM)
+ }
+
+ Method (_PTS, 1, NotSerialized) // _PTS: Prepare To Sleep
+ {
+ }
+
+ Method (_WAK, 1, NotSerialized) // _WAK: Wake
+ {
+ Return (Package (0x02)
+ {
+ Zero,
+ Zero
+ })
+ }
+
+ Method (PNOT, 0, NotSerialized)
+ {
+ If (LGreaterEqual (PCNT, 0x02))
+ {
+ Notify (\_PR.CP00, 0x81)
+ Notify (\_PR.CP01, 0x81)
+ }
+
+ If (LGreaterEqual (PCNT, 0x04))
+ {
+ Notify (\_PR.CP02, 0x81)
+ Notify (\_PR.CP03, 0x81)
+ }
+
+ If (LGreaterEqual (PCNT, 0x08))
+ {
+ Notify (\_PR.CP04, 0x81)
+ Notify (\_PR.CP05, 0x81)
+ Notify (\_PR.CP06, 0x81)
+ Notify (\_PR.CP07, 0x81)
+ }
+ }
+
+ Method (PPCN, 0, NotSerialized)
+ {
+ If (LGreaterEqual (PCNT, 0x02))
+ {
+ Notify (\_PR.CP00, 0x80)
+ Notify (\_PR.CP01, 0x80)
+ }
+
+ If (LGreaterEqual (PCNT, 0x04))
+ {
+ Notify (\_PR.CP02, 0x80)
+ Notify (\_PR.CP03, 0x80)
+ }
+
+ If (LGreaterEqual (PCNT, 0x08))
+ {
+ Notify (\_PR.CP04, 0x80)
+ Notify (\_PR.CP05, 0x80)
+ Notify (\_PR.CP06, 0x80)
+ Notify (\_PR.CP07, 0x80)
+ }
+ }
+
+ Method (TNOT, 0, NotSerialized)
+ {
+ If (LGreaterEqual (PCNT, 0x02))
+ {
+ Notify (\_PR.CP00, 0x82)
+ Notify (\_PR.CP01, 0x82)
+ }
+
+ If (LGreaterEqual (PCNT, 0x04))
+ {
+ Notify (\_PR.CP02, 0x82)
+ Notify (\_PR.CP03, 0x82)
+ }
+
+ If (LGreaterEqual (PCNT, 0x08))
+ {
+ Notify (\_PR.CP04, 0x82)
+ Notify (\_PR.CP05, 0x82)
+ Notify (\_PR.CP06, 0x82)
+ Notify (\_PR.CP07, 0x82)
+ }
+ }
+
+ Method (PPKG, 0, NotSerialized)
+ {
+ If (LGreaterEqual (PCNT, 0x08))
+ {
+ Return (Package (0x08)
+ {
+ \_PR.CP00,
+ \_PR.CP01,
+ \_PR.CP02,
+ \_PR.CP03,
+ \_PR.CP04,
+ \_PR.CP05,
+ \_PR.CP06,
+ \_PR.CP07
+ })
+ }
+ Else
+ {
+ If (LGreaterEqual (PCNT, 0x04))
+ {
+ Return (Package (0x04)
+ {
+ \_PR.CP00,
+ \_PR.CP01,
+ \_PR.CP02,
+ \_PR.CP03
+ })
+ }
+ Else
+ {
+ If (LGreaterEqual (PCNT, 0x02))
+ {
+ Return (Package (0x02)
+ {
+ \_PR.CP00,
+ \_PR.CP01
+ })
+ }
+ Else
+ {
+ Return (Package (0x01)
+ {
+ \_PR.CP00
+ })
+ }
+ }
+ }
+ }
+
+ Name (PICM, Zero)
+ Name (DSEN, One)
+ OperationRegion (GNVS, SystemMemory, NVSA, 0x0F00)
+ Field (GNVS, ByteAcc, NoLock, Preserve)
+ {
+ OSYS, 16,
+ SMIF, 8,
+ PRM0, 8,
+ PRM1, 8,
+ SCIF, 8,
+ PRM2, 8,
+ PRM3, 8,
+ LCKF, 8,
+ PRM4, 8,
+ PRM5, 8,
+ P80D, 32,
+ LIDS, 8,
+ PWRS, 8,
+ TLVL, 8,
+ FLVL, 8,
+ TCRT, 8,
+ TPSV, 8,
+ TMAX, 8,
+ F0OF, 8,
+ F0ON, 8,
+ F0PW, 8,
+ F1OF, 8,
+ F1ON, 8,
+ F1PW, 8,
+ F2OF, 8,
+ F2ON, 8,
+ F2PW, 8,
+ F3OF, 8,
+ F3ON, 8,
+ F3PW, 8,
+ F4OF, 8,
+ F4ON, 8,
+ F4PW, 8,
+ TMPS, 8,
+ Offset (0x28),
+ APIC, 8,
+ MPEN, 8,
+ PCP0, 8,
+ PCP1, 8,
+ PPCM, 8,
+ PCNT, 8,
+ Offset (0x32),
+ NATP, 8,
+ S5U0, 8,
+ S5U1, 8,
+ S3U0, 8,
+ S3U1, 8,
+ S33G, 8,
+ CMEM, 32,
+ IGDS, 8,
+ TLST, 8,
+ CADL, 8,
+ PADL, 8,
+ CSTE, 16,
+ NSTE, 16,
+ SSTE, 16,
+ NDID, 8,
+ DID1, 32,
+ DID2, 32,
+ DID3, 32,
+ DID4, 32,
+ DID5, 32,
+ Offset (0x64),
+ BLCS, 8,
+ BRTL, 8,
+ ODDS, 8,
+ Offset (0x6E),
+ ALSE, 8,
+ ALAF, 8,
+ LLOW, 8,
+ LHIH, 8,
+ Offset (0x78),
+ EMAE, 8,
+ EMAP, 16,
+ EMAL, 16,
+ Offset (0x82),
+ MEFE, 8,
+ Offset (0x8C),
+ TPMP, 8,
+ TPME, 8,
+ Offset (0x96),
+ GTF0, 56,
+ GTF1, 56,
+ GTF2, 56,
+ IDEM, 8,
+ IDET, 8,
+ Offset (0xB2),
+ XHCI, 8,
+ Offset (0xB4),
+ ASLB, 32,
+ IBTT, 8,
+ IPAT, 8,
+ ITVF, 8,
+ ITVM, 8,
+ IPSC, 8,
+ IBLC, 8,
+ IBIA, 8,
+ ISSC, 8,
+ I409, 8,
+ I509, 8,
+ I609, 8,
+ I709, 8,
+ IDMM, 8,
+ IDMS, 8,
+ IF1E, 8,
+ HVCO, 8,
+ NXD1, 32,
+ NXD2, 32,
+ NXD3, 32,
+ NXD4, 32,
+ NXD5, 32,
+ NXD6, 32,
+ NXD7, 32,
+ NXD8, 32,
+ ISCI, 8,
+ PAVP, 8,
+ Offset (0xEB),
+ OSCC, 8,
+ NPCE, 8,
+ PLFL, 8,
+ BREV, 8,
+ DPBM, 8,
+ DPCM, 8,
+ DPDM, 8,
+ ALFP, 8,
+ IMON, 8,
+ MMIO, 8,
+ Offset (0x100),
+ VBT0, 32,
+ VBT1, 32,
+ VBT2, 32,
+ VBT3, 16,
+ VBT4, 2048,
+ VBT5, 512,
+ VBT6, 512,
+ VBT7, 32,
+ VBT8, 32,
+ VBT9, 32,
+ CHVD, 24576,
+ VBTA, 32,
+ MEHH, 256,
+ RMOB, 32,
+ RMOL, 32
+ }
+
+ Method (S3UE, 0, NotSerialized)
+ {
+ Store (One, S3U0)
+ Store (One, S3U1)
+ }
+
+ Method (S3UD, 0, NotSerialized)
+ {
+ Store (Zero, S3U0)
+ Store (Zero, S3U1)
+ }
+
+ Method (S5UE, 0, NotSerialized)
+ {
+ Store (One, S5U0)
+ Store (One, S5U1)
+ }
+
+ Method (S5UD, 0, NotSerialized)
+ {
+ Store (Zero, S5U0)
+ Store (Zero, S5U1)
+ }
+
+ Method (S3GE, 0, NotSerialized)
+ {
+ Store (One, S33G)
+ }
+
+ Method (S3GD, 0, NotSerialized)
+ {
+ Store (Zero, S33G)
+ }
+
+ Method (XHCE, 0, NotSerialized)
+ {
+ Store (One, XHCI)
+ }
+
+ Method (XHCD, 0, NotSerialized)
+ {
+ Store (Zero, XHCI)
+ }
+
+ Method (TZUP, 0, NotSerialized)
+ {
+ If (CondRefOf (\_TZ.THRM))
+ {
+ Notify (\_TZ.THRM, 0x81)
+ }
+
+ If (CondRefOf (\_TZ.SKIN))
+ {
+ Notify (\_TZ.SKIN, 0x81)
+ }
+ }
+
+ Method (F0UT, 2, NotSerialized)
+ {
+ Store (Arg0, F0OF)
+ Store (Arg1, F0ON)
+ TZUP ()
+ }
+
+ Method (F1UT, 2, NotSerialized)
+ {
+ Store (Arg0, F1OF)
+ Store (Arg1, F1ON)
+ TZUP ()
+ }
+
+ Method (F2UT, 2, NotSerialized)
+ {
+ Store (Arg0, F2OF)
+ Store (Arg1, F2ON)
+ TZUP ()
+ }
+
+ Method (F3UT, 2, NotSerialized)
+ {
+ Store (Arg0, F3OF)
+ Store (Arg1, F3ON)
+ TZUP ()
+ }
+
+ Method (F4UT, 2, NotSerialized)
+ {
+ Store (Arg0, F4OF)
+ Store (Arg1, F4ON)
+ TZUP ()
+ }
+
+ Method (TMPU, 1, NotSerialized)
+ {
+ Store (Arg0, TMPS)
+ TZUP ()
+ }
+
+ Name (_S0, Package (0x04) // _S0_: S0 System State
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+ Name (_S3, Package (0x04) // _S3_: S3 System State
+ {
+ 0x05,
+ 0x05,
+ Zero,
+ Zero
+ })
+ Name (_S4, Package (0x04) // _S4_: S4 System State
+ {
+ 0x06,
+ 0x06,
+ Zero,
+ Zero
+ })
+ Name (_S5, Package (0x04) // _S5_: S5 System State
+ {
+ 0x07,
+ 0x07,
+ Zero,
+ Zero
+ })
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08")) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A03")) // _CID: Compatible ID
+ Name (_ADR, Zero) // _ADR: Address
+ Name (_BBN, Zero) // _BBN: BIOS Bus Number
+ Device (MCHC)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ OperationRegion (MCHP, PCI_Config, Zero, 0x0100)
+ Field (MCHP, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x40),
+ EPEN, 1,
+ , 11,
+ EPBR, 24,
+ Offset (0x48),
+ MHEN, 1,
+ , 13,
+ MHBR, 22,
+ Offset (0x60),
+ PXEN, 1,
+ PXSZ, 2,
+ , 23,
+ PXBR, 10,
+ Offset (0x68),
+ DMEN, 1,
+ , 11,
+ DMBR, 24,
+ Offset (0x70),
+ MEBA, 64,
+ Offset (0x80),
+ , 4,
+ PM0H, 2,
+ Offset (0x81),
+ PM1L, 2,
+ , 2,
+ PM1H, 2,
+ Offset (0x82),
+ PM2L, 2,
+ , 2,
+ PM2H, 2,
+ Offset (0x83),
+ PM3L, 2,
+ , 2,
+ PM3H, 2,
+ Offset (0x84),
+ PM4L, 2,
+ , 2,
+ PM4H, 2,
+ Offset (0x85),
+ PM5L, 2,
+ , 2,
+ PM5H, 2,
+ Offset (0x86),
+ PM6L, 2,
+ , 2,
+ PM6H, 2,
+ Offset (0x87),
+ Offset (0xA0),
+ TOM, 64,
+ Offset (0xBC),
+ TLUD, 32
+ }
+
+ Mutex (CTCM, 0x01)
+ Name (CTCC, Zero)
+ Name (CTCN, Zero)
+ Name (CTCD, One)
+ Name (CTCU, 0x02)
+ OperationRegion (MCHB, SystemMemory, 0xFED10000, 0x8000)
+ Field (MCHB, DWordAcc, Lock, Preserve)
+ {
+ Offset (0x5930),
+ CTDN, 15,
+ Offset (0x59A0),
+ PL1V, 15,
+ PL1E, 1,
+ PL1C, 1,
+ PL1T, 7,
+ Offset (0x59A4),
+ PL2V, 15,
+ PL2E, 1,
+ PL2C, 1,
+ PL2T, 7,
+ Offset (0x5F3C),
+ TARN, 8,
+ Offset (0x5F40),
+ CTDD, 15,
+ Offset (0x5F42),
+ TARD, 8,
+ Offset (0x5F48),
+ CTDU, 15,
+ Offset (0x5F4A),
+ TARU, 8,
+ Offset (0x5F50),
+ CTCS, 2,
+ Offset (0x5F54),
+ TARS, 8
+ }
+
+ Method (PSSS, 1, NotSerialized)
+ {
+ Store (One, Local0)
+ Store (SizeOf (\_PR.CP00._PSS), Local1)
+ While (LLess (Local0, Local1))
+ {
+ ShiftRight (DerefOf (Index (DerefOf (Index (\_PR.CP00._PSS, Local0)), 0x04)),
+ 0x08, Local2)
+ If (LEqual (Local2, Arg0))
+ {
+ Return (Subtract (Local0, One))
+ }
+
+ Increment (Local0)
+ }
+
+ Return (Zero)
+ }
+
+ Method (STND, 0, Serialized)
+ {
+ If (Acquire (CTCM, 0x0064))
+ {
+ Return (Zero)
+ }
+
+ If (LEqual (CTCD, CTCC))
+ {
+ Release (CTCM)
+ Return (Zero)
+ }
+
+ Store ("Set TDP Down", Debug)
+ Store (CTCD, CTCS)
+ Store (TARD, TARS)
+ Store (PSSS (TARD), PPCM)
+ PPCN ()
+ Divide (Multiply (CTDD, 0x7D), 0x64, , PL2V)
+ Store (CTDD, PL1V)
+ Store (CTCD, CTCC)
+ Release (CTCM)
+ Return (One)
+ }
+
+ Method (STDN, 0, Serialized)
+ {
+ If (Acquire (CTCM, 0x0064))
+ {
+ Return (Zero)
+ }
+
+ If (LEqual (CTCN, CTCC))
+ {
+ Release (CTCM)
+ Return (Zero)
+ }
+
+ Store ("Set TDP Nominal", Debug)
+ Store (CTDN, PL1V)
+ Divide (Multiply (CTDN, 0x7D), 0x64, , PL2V)
+ Store (PSSS (TARN), PPCM)
+ PPCN ()
+ Store (TARN, TARS)
+ Store (CTCN, CTCS)
+ Store (CTCN, CTCC)
+ Release (CTCM)
+ Return (One)
+ }
+ }
+
+ Name (MCRS, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Granularity
+ 0x0000, // Range Minimum
+ 0x00FF, // Range Maximum
+ 0x0000, // Translation Offset
+ 0x0100, // Length
+ ,, )
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0x00000CF7, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00000CF8, // Length
+ ,, , TypeStatic)
+ IO (Decode16,
+ 0x0CF8, // Range Minimum
+ 0x0CF8, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Granularity
+ 0x00000D00, // Range Minimum
+ 0x0000FFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x0000F300, // Length
+ ,, , TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000A0000, // Range Minimum
+ 0x000BFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00020000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000C0000, // Range Minimum
+ 0x000C3FFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00004000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000C4000, // Range Minimum
+ 0x000C7FFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00004000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000C8000, // Range Minimum
+ 0x000CBFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00004000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000CC000, // Range Minimum
+ 0x000CFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00004000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000D0000, // Range Minimum
+ 0x000D3FFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00004000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000D4000, // Range Minimum
+ 0x000D7FFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00004000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000D8000, // Range Minimum
+ 0x000DBFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00004000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000DC000, // Range Minimum
+ 0x000DFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00004000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000E0000, // Range Minimum
+ 0x000E3FFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00004000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000E4000, // Range Minimum
+ 0x000E7FFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00004000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000E8000, // Range Minimum
+ 0x000EBFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00004000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000EC000, // Range Minimum
+ 0x000EFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00004000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x000F0000, // Range Minimum
+ 0x000FFFFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00010000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0x00000000, // Range Minimum
+ 0x00000000, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00000000, // Length
+ ,, _Y00, AddressRangeMemory, TypeStatic)
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Granularity
+ 0xFED40000, // Range Minimum
+ 0xFED44FFF, // Range Maximum
+ 0x00000000, // Translation Offset
+ 0x00005000, // Length
+ ,, , AddressRangeMemory, TypeStatic)
+ })
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ CreateDWordField (MCRS, \_SB.PCI0._Y00._MIN, PMIN) // _MIN: Minimum Base Address
+ CreateDWordField (MCRS, \_SB.PCI0._Y00._MAX, PMAX) // _MAX: Maximum Base Address
+ CreateDWordField (MCRS, \_SB.PCI0._Y00._LEN, PLEN) // _LEN: Length
+ Store (^MCHC.TLUD, Local0)
+ Store (^MCHC.MEBA, Local1)
+ If (LEqual (Local0, Local1))
+ {
+ Store (^MCHC.TOM, Local0)
+ }
+
+ Store (Local0, PMIN)
+ Store (0xEFFFFFFF, PMAX)
+ Add (Subtract (PMAX, PMIN), One, PLEN)
+ Return (MCRS)
+ }
+
+ Device (PDRC)
+ {
+ Name (_HID, EisaId ("PNP0C02")) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Name (PDRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite,
+ 0xFED1C000, // Address Base
+ 0x00004000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xFED10000, // Address Base
+ 0x00008000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xFED18000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xFED19000, // Address Base
+ 0x00001000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xF0000000, // Address Base
+ 0x04000000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xFED20000, // Address Base
+ 0x00020000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xFED40000, // Address Base
+ 0x00005000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0xFED45000, // Address Base
+ 0x0004B000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0x20000000, // Address Base
+ 0x00200000, // Address Length
+ )
+ Memory32Fixed (ReadWrite,
+ 0x40000000, // Address Base
+ 0x00200000, // Address Length
+ )
+ })
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Return (PDRS)
+ }
+ }
+
+ Device (GFX0)
+ {
+ Name (_ADR, 0x00020000) // _ADR: Address
+ OperationRegion (GFXC, PCI_Config, Zero, 0x0100)
+ Field (GFXC, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x10),
+ BAR0, 64
+ }
+
+ OperationRegion (GFRG, SystemMemory, And (BAR0, 0xFFFFFFFFFFFFFFF0), 0x00400000)
+ Field (GFRG, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0x48254),
+ BCLV, 16,
+ Offset (0xC8256),
+ BCLM, 16
+ }
+
+ Method (XBCM, 1, NotSerialized)
+ {
+ Store (Divide (Multiply (Arg0, BCLM), 0x64, ), BCLV)
+ }
+
+ Method (XBQC, 0, NotSerialized)
+ {
+ Store (BCLV, Local0)
+ Store (BCLM, Local1)
+ Store (0x02, Local2)
+ While (LLess (Local2, Subtract (SizeOf (BRIG), One)))
+ {
+ Store (DerefOf (Index (BRIG, Local2)), Local3)
+ Store (Divide (Multiply (Local3, Local1), 0x64, ), Local3)
+ If (LLessEqual (Local0, Local3))
+ {
+ Return (DerefOf (Index (BRIG, Local2)))
+ }
+
+ Add (Local2, One, Local2)
+ }
+
+ Return (DerefOf (Index (BRIG, Local2)))
+ }
+
+ Name (BRCT, Zero)
+ Method (BRID, 1, NotSerialized)
+ {
+ Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 0x02), Local0)
+ If (LEqual (Local0, Ones))
+ {
+ Return (Subtract (SizeOf (BRIG), One))
+ }
+
+ Return (Local0)
+ }
+
+ Method (XBCL, 0, NotSerialized)
+ {
+ Store (One, BRCT)
+ Return (BRIG)
+ }
+
+ Method (_DOS, 1, NotSerialized) // _DOS: Disable Output Switching
+ {
+ Store (And (Arg0, 0x07), DSEN)
+ }
+
+ Method (DECB, 0, NotSerialized)
+ {
+ If (BRCT)
+ {
+ Notify (LCD0, 0x87)
+ }
+ Else
+ {
+ Store (BRID (XBQC ()), Local0)
+ If (LNotEqual (Local0, 0x02))
+ {
+ Decrement (Local0)
+ }
+
+ XBCM (DerefOf (Index (BRIG, Local0)))
+ }
+ }
+
+ Method (INCB, 0, NotSerialized)
+ {
+ If (BRCT)
+ {
+ Notify (LCD0, 0x86)
+ }
+ Else
+ {
+ Store (BRID (XBQC ()), Local0)
+ If (LNotEqual (Local0, Subtract (SizeOf (BRIG), One)))
+ {
+ Increment (Local0)
+ }
+
+ XBCM (DerefOf (Index (BRIG, Local0)))
+ }
+ }
+
+ Method (XDCS, 1, NotSerialized)
+ {
+ TRAP (One)
+ If (And (CSTE, ShiftLeft (One, Arg0)))
+ {
+ Return (0x1F)
+ }
+
+ Return (0x1D)
+ }
+
+ Method (XDGS, 1, NotSerialized)
+ {
+ If (And (NSTE, ShiftLeft (One, Arg0)))
+ {
+ Return (One)
+ }
+
+ Return (Zero)
+ }
+
+ Method (XDSS, 2, NotSerialized)
+ {
+ If (LEqual (And (Arg0, 0xC0000000), 0xC0000000))
+ {
+ Store (NSTE, CSTE)
+ }
+ }
+ }
+
+ Scope (\)
+ {
+ OperationRegion (IO_T, SystemIO, 0x0800, 0x10)
+ Field (IO_T, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x08),
+ TRP0, 8
+ }
+
+ OperationRegion (PMIO, SystemIO, 0x0500, 0x80)
+ Field (PMIO, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x20),
+ Offset (0x22),
+ GS00, 1,
+ GS01, 1,
+ GS02, 1,
+ GS03, 1,
+ GS04, 1,
+ GS05, 1,
+ GS06, 1,
+ GS07, 1,
+ GS08, 1,
+ GS09, 1,
+ GS10, 1,
+ GS11, 1,
+ GS12, 1,
+ GS13, 1,
+ GS14, 1,
+ GS15, 1,
+ Offset (0x28),
+ Offset (0x2A),
+ GE00, 1,
+ GE01, 1,
+ GE02, 1,
+ GE03, 1,
+ GE04, 1,
+ GE05, 1,
+ GE06, 1,
+ GE07, 1,
+ GE08, 1,
+ GE09, 1,
+ GE10, 1,
+ GE11, 1,
+ GE12, 1,
+ GE13, 1,
+ GE14, 1,
+ GE15, 1,
+ Offset (0x42),
+ , 1,
+ GPEC, 1
+ }
+
+ OperationRegion (GPIO, SystemIO, 0x0480, 0x6C)
+ Field (GPIO, ByteAcc, NoLock, Preserve)
+ {
+ GU00, 8,
+ GU01, 8,
+ GU02, 8,
+ GU03, 8,
+ GIO0, 8,
+ GIO1, 8,
+ GIO2, 8,
+ GIO3, 8,
+ Offset (0x0C),
+ GL00, 1,
+ GP01, 1,
+ GP02, 1,
+ GP03, 1,
+ GP04, 1,
+ GP05, 1,
+ GP06, 1,
+ GP07, 1,
+ GP08, 1,
+ GP09, 1,
+ GP10, 1,
+ GP11, 1,
+ GP12, 1,
+ GP13, 1,
+ GP14, 1,
+ GP15, 1,
+ GP16, 1,
+ GP17, 1,
+ GP18, 1,
+ GP19, 1,
+ GP20, 1,
+ GP21, 1,
+ GP22, 1,
+ GP23, 1,
+ GP24, 1,
+ GP25, 1,
+ GP26, 1,
+ GP27, 1,
+ GP28, 1,
+ GP29, 1,
+ GP30, 1,
+ GP31, 1,
+ Offset (0x18),
+ GB00, 8,
+ GB01, 8,
+ GB02, 8,
+ GB03, 8,
+ Offset (0x2C),
+ GIV0, 8,
+ GIV1, 8,
+ GIV2, 8,
+ GIV3, 8,
+ GU04, 8,
+ GU05, 8,
+ GU06, 8,
+ GU07, 8,
+ GIO4, 8,
+ GIO5, 8,
+ GIO6, 8,
+ GIO7, 8,
+ GP32, 1,
+ GP33, 1,
+ GP34, 1,
+ GP35, 1,
+ GP36, 1,
+ GP37, 1,
+ GP38, 1,
+ GP39, 1,
+ GP40, 1,
+ GP41, 1,
+ GP42, 1,
+ GP43, 1,
+ GP44, 1,
+ GP45, 1,
+ GP46, 1,
+ GP47, 1,
+ GP48, 1,
+ GP49, 1,
+ GP50, 1,
+ GP51, 1,
+ GP52, 1,
+ GP53, 1,
+ GP54, 1,
+ GP55, 1,
+ GP56, 1,
+ GP57, 1,
+ GP58, 1,
+ GP59, 1,
+ GP60, 1,
+ GP61, 1,
+ GP62, 1,
+ GP63, 1,
+ Offset (0x40),
+ GU08, 8,
+ GU09, 4,
+ Offset (0x44),
+ GIO8, 8,
+ GIO9, 4,
+ Offset (0x48),
+ GP64, 1,
+ GP65, 1,
+ GP66, 1,
+ GP67, 1,
+ GP68, 1,
+ GP69, 1,
+ GP70, 1,
+ GP71, 1,
+ GP72, 1,
+ GP73, 1,
+ GP74, 1,
+ GP75, 1
+ }
+
+ OperationRegion (RCRB, SystemMemory, 0xFED1C000, 0x4000)
+ Field (RCRB, DWordAcc, Lock, Preserve)
+ {
+ Offset (0x1000),
+ Offset (0x3000),
+ Offset (0x3404),
+ HPAS, 2,
+ , 5,
+ HPTE, 1,
+ Offset (0x3418),
+ , 1,
+ PCID, 1,
+ SA1D, 1,
+ SMBD, 1,
+ HDAD, 1,
+ , 8,
+ EH2D, 1,
+ LPBD, 1,
+ EH1D, 1,
+ RP1D, 1,
+ RP2D, 1,
+ RP3D, 1,
+ RP4D, 1,
+ RP5D, 1,
+ RP6D, 1,
+ RP7D, 1,
+ RP8D, 1,
+ TTRD, 1,
+ SA2D, 1,
+ Offset (0x3428),
+ BDFD, 1,
+ ME1D, 1,
+ ME2D, 1,
+ IDRD, 1,
+ KTCT, 1
+ }
+ }
+
+ Device (HDEF)
+ {
+ Name (_ADR, 0x001B0000) // _ADR: Address
+ Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
+ {
+ 0x0D,
+ 0x04
+ })
+ }
+
+ Method (IRQM, 1, Serialized)
+ {
+ Name (_T_0, Zero) // _T_x: Emitted by ASL Compiler
+ Name (IQAA, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ Zero,
+ 0x13
+ }
+ })
+ Name (IQAP, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ ^LPCB.LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ ^LPCB.LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ ^LPCB.LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ ^LPCB.LNKD,
+ Zero
+ }
+ })
+ Name (IQBA, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ Zero,
+ 0x10
+ }
+ })
+ Name (IQBP, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ ^LPCB.LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ ^LPCB.LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ ^LPCB.LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ ^LPCB.LNKA,
+ Zero
+ }
+ })
+ Name (IQCA, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ Zero,
+ 0x12
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ Zero,
+ 0x11
+ }
+ })
+ Name (IQCP, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ ^LPCB.LNKC,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ ^LPCB.LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ ^LPCB.LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ ^LPCB.LNKB,
+ Zero
+ }
+ })
+ Name (IQDA, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ Zero,
+ 0x12
+ }
+ })
+ Name (IQDP, Package (0x04)
+ {
+ Package (0x04)
+ {
+ 0xFFFF,
+ Zero,
+ ^LPCB.LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ One,
+ ^LPCB.LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x02,
+ ^LPCB.LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0xFFFF,
+ 0x03,
+ ^LPCB.LNKC,
+ Zero
+ }
+ })
+ While (One)
+ {
+ Store (ToInteger (Arg0), _T_0)
+ If (LNotEqual (Match (Package (0x02)
+ {
+ One,
+ 0x05
+ }, MEQ, _T_0, MTR, Zero, Zero), Ones))
+ {
+ If (PICM)
+ {
+ Return (IQAA)
+ }
+ Else
+ {
+ Return (IQAP)
+ }
+ }
+ Else
+ {
+ If (LNotEqual (Match (Package (0x02)
+ {
+ 0x02,
+ 0x06
+ }, MEQ, _T_0, MTR, Zero, Zero), Ones))
+ {
+ If (PICM)
+ {
+ Return (IQBA)
+ }
+ Else
+ {
+ Return (IQBP)
+ }
+ }
+ Else
+ {
+ If (LNotEqual (Match (Package (0x02)
+ {
+ 0x03,
+ 0x07
+ }, MEQ, _T_0, MTR, Zero, Zero), Ones))
+ {
+ If (PICM)
+ {
+ Return (IQCA)
+ }
+ Else
+ {
+ Return (IQCP)
+ }
+ }
+ Else
+ {
+ If (LNotEqual (Match (Package (0x02)
+ {
+ 0x04,
+ 0x08
+ }, MEQ, _T_0, MTR, Zero, Zero), Ones))
+ {
+ If (PICM)
+ {
+ Return (IQDA)
+ }
+ Else
+ {
+ Return (IQDP)
+ }
+ }
+ Else
+ {
+ If (PICM)
+ {
+ Return (IQDA)
+ }
+ Else
+ {
+ Return (IQDP)
+ }
+ }
+ }
+ }
+ }
+
+ Break
+ }
+ }
+
+ Device (RP01)
+ {
+ Name (_ADR, 0x001C0000) // _ADR: Address
+ OperationRegion (RPCS, PCI_Config, Zero, 0xFF)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x4C),
+ Offset (0x4F),
+ RPPN, 8,
+ Offset (0x5A),
+ , 3,
+ PDC, 1,
+ Offset (0xDF),
+ , 6,
+ HPCS, 1
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Return (IRQM (RPPN))
+ }
+ }
+
+ Device (RP02)
+ {
+ Name (_ADR, 0x001C0001) // _ADR: Address
+ OperationRegion (RPCS, PCI_Config, Zero, 0xFF)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x4C),
+ Offset (0x4F),
+ RPPN, 8,
+ Offset (0x5A),
+ , 3,
+ PDC, 1,
+ Offset (0xDF),
+ , 6,
+ HPCS, 1
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Return (IRQM (RPPN))
+ }
+ }
+
+ Device (RP03)
+ {
+ Name (_ADR, 0x001C0002) // _ADR: Address
+ OperationRegion (RPCS, PCI_Config, Zero, 0xFF)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x4C),
+ Offset (0x4F),
+ RPPN, 8,
+ Offset (0x5A),
+ , 3,
+ PDC, 1,
+ Offset (0xDF),
+ , 6,
+ HPCS, 1
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Return (IRQM (RPPN))
+ }
+ }
+
+ Device (RP04)
+ {
+ Name (_ADR, 0x001C0003) // _ADR: Address
+ OperationRegion (RPCS, PCI_Config, Zero, 0xFF)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x4C),
+ Offset (0x4F),
+ RPPN, 8,
+ Offset (0x5A),
+ , 3,
+ PDC, 1,
+ Offset (0xDF),
+ , 6,
+ HPCS, 1
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Return (IRQM (RPPN))
+ }
+ }
+
+ Device (RP05)
+ {
+ Name (_ADR, 0x001C0004) // _ADR: Address
+ OperationRegion (RPCS, PCI_Config, Zero, 0xFF)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x4C),
+ Offset (0x4F),
+ RPPN, 8,
+ Offset (0x5A),
+ , 3,
+ PDC, 1,
+ Offset (0xDF),
+ , 6,
+ HPCS, 1
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Return (IRQM (RPPN))
+ }
+ }
+
+ Device (RP06)
+ {
+ Name (_ADR, 0x001C0005) // _ADR: Address
+ OperationRegion (RPCS, PCI_Config, Zero, 0xFF)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x4C),
+ Offset (0x4F),
+ RPPN, 8,
+ Offset (0x5A),
+ , 3,
+ PDC, 1,
+ Offset (0xDF),
+ , 6,
+ HPCS, 1
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Return (IRQM (RPPN))
+ }
+ }
+
+ Device (RP07)
+ {
+ Name (_ADR, 0x001C0006) // _ADR: Address
+ OperationRegion (RPCS, PCI_Config, Zero, 0xFF)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x4C),
+ Offset (0x4F),
+ RPPN, 8,
+ Offset (0x5A),
+ , 3,
+ PDC, 1,
+ Offset (0xDF),
+ , 6,
+ HPCS, 1
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Return (IRQM (RPPN))
+ }
+ }
+
+ Device (RP08)
+ {
+ Name (_ADR, 0x001C0007) // _ADR: Address
+ OperationRegion (RPCS, PCI_Config, Zero, 0xFF)
+ Field (RPCS, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x4C),
+ Offset (0x4F),
+ RPPN, 8,
+ Offset (0x5A),
+ , 3,
+ PDC, 1,
+ Offset (0xDF),
+ , 6,
+ HPCS, 1
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ Return (IRQM (RPPN))
+ }
+ }
+
+ Device (EHC1)
+ {
+ Name (_ADR, 0x001D0000) // _ADR: Address
+ Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
+ {
+ 0x0D,
+ 0x04
+ })
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (0x02)
+ }
+
+ Method (_S4D, 0, NotSerialized) // _S4D: S4 Device State
+ {
+ Return (0x02)
+ }
+
+ Device (HUB7)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Device (PRT1)
+ {
+ Name (_ADR, One) // _ADR: Address
+ }
+
+ Device (PRT2)
+ {
+ Name (_ADR, 0x02) // _ADR: Address
+ }
+
+ Device (PRT3)
+ {
+ Name (_ADR, 0x03) // _ADR: Address
+ }
+
+ Device (PRT4)
+ {
+ Name (_ADR, 0x04) // _ADR: Address
+ }
+
+ Device (PRT5)
+ {
+ Name (_ADR, 0x05) // _ADR: Address
+ }
+
+ Device (PRT6)
+ {
+ Name (_ADR, 0x06) // _ADR: Address
+ }
+ }
+ }
+
+ Device (EHC2)
+ {
+ Name (_ADR, 0x001A0000) // _ADR: Address
+ Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
+ {
+ 0x0D,
+ 0x04
+ })
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (0x02)
+ }
+
+ Method (_S4D, 0, NotSerialized) // _S4D: S4 Device State
+ {
+ Return (0x02)
+ }
+
+ Device (HUB7)
+ {
+ Name (_ADR, Zero) // _ADR: Address
+ Device (PRT1)
+ {
+ Name (_ADR, One) // _ADR: Address
+ }
+
+ Device (PRT2)
+ {
+ Name (_ADR, 0x02) // _ADR: Address
+ }
+
+ Device (PRT3)
+ {
+ Name (_ADR, 0x03) // _ADR: Address
+ }
+
+ Device (PRT4)
+ {
+ Name (_ADR, 0x04) // _ADR: Address
+ }
+
+ Device (PRT5)
+ {
+ Name (_ADR, 0x05) // _ADR: Address
+ }
+
+ Device (PRT6)
+ {
+ Name (_ADR, 0x06) // _ADR: Address
+ }
+ }
+ }
+
+ Device (XHC)
+ {
+ Name (_ADR, 0x00140000) // _ADR: Address
+ OperationRegion (XDEV, PCI_Config, Zero, 0x0100)
+ Field (XDEV, DWordAcc, NoLock, Preserve)
+ {
+ Offset (0xD0),
+ X2PR, 32,
+ PRM2, 32,
+ SSEN, 32,
+ RPM3, 32,
+ XPRT, 32
+ }
+
+ Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
+ {
+ 0x0D,
+ 0x04
+ })
+ Method (POSC, 3, Serialized)
+ {
+ CreateDWordField (Arg2, Zero, CDW1)
+ If (LNotEqual (Arg1, One))
+ {
+ Or (CDW1, 0x08, CDW1)
+ }
+
+ If (LEqual (XHCI, Zero))
+ {
+ Or (CDW1, 0x02, CDW1)
+ }
+
+ If (LAnd (LNot (And (CDW1, One)), LOr (LEqual (XHCI,
+ 0x02), LEqual (XHCI, 0x03))))
+ {
+ Store ("XHCI Switch", Debug)
+ Store (Zero, Local0)
+ And (XPRT, 0x03, Local0)
+ If (LOr (LEqual (Local0, Zero), LEqual (Local0, One)))
+ {
+ Store (0x0F, Local1)
+ }
+ Else
+ {
+ If (LEqual (Local0, 0x02))
+ {
+ Store (0x03, Local1)
+ }
+ Else
+ {
+ If (LEqual (Local0, 0x03))
+ {
+ Store (Zero, Local1)
+ }
+ }
+ }
+
+ And (RPM3, 0xFFFFFFF0, Local0)
+ Or (Local0, Local1, RPM3)
+ And (PRM2, 0xFFFFFFF0, Local0)
+ Or (Local0, Local1, PRM2)
+ And (SSEN, 0xFFFFFFF0, Local0)
+ Or (Local0, Local1, SSEN)
+ And (X2PR, 0xFFFFFFF0, Local0)
+ Or (Local0, Local1, X2PR)
+ }
+
+ Return (Arg2)
+ }
+
+ Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State
+ {
+ Return (0x02)
+ }
+
+ Method (_S4D, 0, NotSerialized) // _S4D: S4 Device State
+ {
+ Return (0x02)
+ }
+ }
+
+ Device (LPCB)
+ {
+ Name (_ADR, 0x001F0000) // _ADR: Address
+ OperationRegion (LPC0, PCI_Config, Zero, 0x0100)
+ Field (LPC0, AnyAcc, NoLock, Preserve)
+ {
+ Offset (0x40),
+ PMBS, 16,
+ Offset (0x60),
+ PRTA, 8,
+ PRTB, 8,
+ PRTC, 8,
+ PRTD, 8,
+ Offset (0x68),
+ PRTE, 8,
+ PRTF, 8,
+ PRTG, 8,
+ PRTH, 8,
+ Offset (0x80),
+ IOD0, 8,
+ IOD1, 8,
+ Offset (0xB8),
+ GR00, 2,
+ GR01, 2,
+ GR02, 2,
+ GR03, 2,
+ GR04, 2,
+ GR05, 2,
+ GR06, 2,
+ GR07, 2,
+ GR08, 2,
+ GR09, 2,
+ GR10, 2,
+ GR11, 2,
+ GR12, 2,
+ GR13, 2,
+ GR14, 2,
+ GR15, 2,
+ Offset (0xF0),
+ RCEN, 1,
+ , 13,
+ RCBA, 18
+ }
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
+ Name (_UID, One) // _UID: Unique ID
+ Method (_DIS, 0, Serialized) // _DIS: Disable Device
+ {
+ Store (0x80, PRTA)
+ }
+
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {3,4,5,6,7,10,12,14,15}
+ })
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RTLA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {}
+ })
+ CreateWordField (RTLA, One, IRQ0)
+ Store (Zero, IRQ0)
+ ShiftLeft (One, And (PRTA, 0x0F), IRQ0)
+ Return (RTLA)
+ }
+
+ Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings
+ {
+ CreateWordField (Arg0, One, IRQ0)
+ FindSetRightBit (IRQ0, Local0)
+ Decrement (Local0)
+ Store (Local0, PRTA)
+ }
+
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ If (And (PRTA, 0x80))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Method (_DIS, 0, Serialized) // _DIS: Disable Device
+ {
+ Store (0x80, PRTB)
+ }
+
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {3,4,5,6,7,11,12,14,15}
+ })
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RTLB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {}
+ })
+ CreateWordField (RTLB, One, IRQ0)
+ Store (Zero, IRQ0)
+ ShiftLeft (One, And (PRTB, 0x0F), IRQ0)
+ Return (RTLB)
+ }
+
+ Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings
+ {
+ CreateWordField (Arg0, One, IRQ0)
+ FindSetRightBit (IRQ0, Local0)
+ Decrement (Local0)
+ Store (Local0, PRTB)
+ }
+
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ If (And (PRTB, 0x80))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
+ Name (_UID, 0x03) // _UID: Unique ID
+ Method (_DIS, 0, Serialized) // _DIS: Disable Device
+ {
+ Store (0x80, PRTC)
+ }
+
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {3,4,5,6,7,10,12,14,15}
+ })
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RTLC, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {}
+ })
+ CreateWordField (RTLC, One, IRQ0)
+ Store (Zero, IRQ0)
+ ShiftLeft (One, And (PRTC, 0x0F), IRQ0)
+ Return (RTLC)
+ }
+
+ Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings
+ {
+ CreateWordField (Arg0, One, IRQ0)
+ FindSetRightBit (IRQ0, Local0)
+ Decrement (Local0)
+ Store (Local0, PRTC)
+ }
+
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ If (And (PRTC, 0x80))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
+ Name (_UID, 0x04) // _UID: Unique ID
+ Method (_DIS, 0, Serialized) // _DIS: Disable Device
+ {
+ Store (0x80, PRTD)
+ }
+
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {3,4,5,6,7,11,12,14,15}
+ })
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RTLD, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {}
+ })
+ CreateWordField (RTLD, One, IRQ0)
+ Store (Zero, IRQ0)
+ ShiftLeft (One, And (PRTD, 0x0F), IRQ0)
+ Return (RTLD)
+ }
+
+ Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings
+ {
+ CreateWordField (Arg0, One, IRQ0)
+ FindSetRightBit (IRQ0, Local0)
+ Decrement (Local0)
+ Store (Local0, PRTD)
+ }
+
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ If (And (PRTD, 0x80))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+ }
+
+ Device (LNKE)
+ {
+ Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
+ Name (_UID, 0x05) // _UID: Unique ID
+ Method (_DIS, 0, Serialized) // _DIS: Disable Device
+ {
+ Store (0x80, PRTE)
+ }
+
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {3,4,5,6,7,10,12,14,15}
+ })
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RTLE, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {}
+ })
+ CreateWordField (RTLE, One, IRQ0)
+ Store (Zero, IRQ0)
+ ShiftLeft (One, And (PRTE, 0x0F), IRQ0)
+ Return (RTLE)
+ }
+
+ Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings
+ {
+ CreateWordField (Arg0, One, IRQ0)
+ FindSetRightBit (IRQ0, Local0)
+ Decrement (Local0)
+ Store (Local0, PRTE)
+ }
+
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ If (And (PRTE, 0x80))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+ }
+
+ Device (LNKF)
+ {
+ Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
+ Name (_UID, 0x06) // _UID: Unique ID
+ Method (_DIS, 0, Serialized) // _DIS: Disable Device
+ {
+ Store (0x80, PRTF)
+ }
+
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {3,4,5,6,7,11,12,14,15}
+ })
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RTLF, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {}
+ })
+ CreateWordField (RTLF, One, IRQ0)
+ Store (Zero, IRQ0)
+ ShiftLeft (One, And (PRTF, 0x0F), IRQ0)
+ Return (RTLF)
+ }
+
+ Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings
+ {
+ CreateWordField (Arg0, One, IRQ0)
+ FindSetRightBit (IRQ0, Local0)
+ Decrement (Local0)
+ Store (Local0, PRTF)
+ }
+
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ If (And (PRTF, 0x80))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+ }
+
+ Device (LNKG)
+ {
+ Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
+ Name (_UID, 0x07) // _UID: Unique ID
+ Method (_DIS, 0, Serialized) // _DIS: Disable Device
+ {
+ Store (0x80, PRTG)
+ }
+
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {3,4,5,6,7,10,12,14,15}
+ })
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RTLG, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {}
+ })
+ CreateWordField (RTLG, One, IRQ0)
+ Store (Zero, IRQ0)
+ ShiftLeft (One, And (PRTG, 0x0F), IRQ0)
+ Return (RTLG)
+ }
+
+ Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings
+ {
+ CreateWordField (Arg0, One, IRQ0)
+ FindSetRightBit (IRQ0, Local0)
+ Decrement (Local0)
+ Store (Local0, PRTG)
+ }
+
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ If (And (PRTG, 0x80))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+ }
+
+ Device (LNKH)
+ {
+ Name (_HID, EisaId ("PNP0C0F")) // _HID: Hardware ID
+ Name (_UID, 0x08) // _UID: Unique ID
+ Method (_DIS, 0, Serialized) // _DIS: Disable Device
+ {
+ Store (0x80, PRTH)
+ }
+
+ Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {3,4,5,6,7,11,12,14,15}
+ })
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ Name (RTLH, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {}
+ })
+ CreateWordField (RTLH, One, IRQ0)
+ Store (Zero, IRQ0)
+ ShiftLeft (One, And (PRTH, 0x0F), IRQ0)
+ Return (RTLH)
+ }
+
+ Method (_SRS, 1, Serialized) // _SRS: Set Resource Settings
+ {
+ CreateWordField (Arg0, One, IRQ0)
+ FindSetRightBit (IRQ0, Local0)
+ Decrement (Local0)
+ Store (Local0, PRTH)
+ }
+
+ Method (_STA, 0, Serialized) // _STA: Status
+ {
+ If (And (PRTH, 0x80))
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+ }
+
+ Device (DMAC)
+ {
+ Name (_HID, EisaId ("PNP0200")) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0000, // Range Minimum
+ 0x0000, // Range Maximum
+ 0x01, // Alignment
+ 0x20, // Length
+ )
+ IO (Decode16,
+ 0x0081, // Range Minimum
+ 0x0081, // Range Maximum
+ 0x01, // Alignment
+ 0x11, // Length
+ )
+ IO (Decode16,
+ 0x0093, // Range Minimum
+ 0x0093, // Range Maximum
+ 0x01, // Alignment
+ 0x0D, // Length
+ )
+ IO (Decode16,
+ 0x00C0, // Range Minimum
+ 0x00C0, // Range Maximum
+ 0x01, // Alignment
+ 0x20, // Length
+ )
+ DMA (Compatibility, NotBusMaster, Transfer8_16, )
+ {4}
+ })
+ }
+
+ Device (FWH)
+ {
+ Name (_HID, EisaId ("INT0800")) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFF000000, // Address Base
+ 0x01000000, // Address Length
+ )
+ })
+ }
+
+ Device (HPET)
+ {
+ Name (_HID, EisaId ("PNP0103")) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0C01")) // _CID: Compatible ID
+ Name (BUF0, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadOnly,
+ 0xFED00000, // Address Base
+ 0x00000400, // Address Length
+ _Y01)
+ })
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ If (HPTE)
+ {
+ If (LGreaterEqual (OSYS, 0x07D1))
+ {
+ Return (0x0F)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Return (Zero)
+ }
+
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settings
+ {
+ If (HPTE)
+ {
+ CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET._Y01._BAS, HPT0) // _BAS: Base Address
+ If (LEqual (HPAS, One))
+ {
+ Store (0xFED01000, HPT0)
+ }
+
+ If (LEqual (HPAS, 0x02))
+ {
+ Store (0xFED02000, HPT0)
+ }
+
+ If (LEqual (HPAS, 0x03))
+ {
+ Store (0xFED03000, HPT0)
+ }
+ }
+
+ Return (BUF0)
+ }
+ }
+
+ Device (PIC)
+ {
+ Name (_HID, EisaId ("PNP0000")) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0020, // Range Minimum
+ 0x0020, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x0024, // Range Minimum
+ 0x0024, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x0028, // Range Minimum
+ 0x0028, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x002C, // Range Minimum
+ 0x002C, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x0030, // Range Minimum
+ 0x0030, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x0034, // Range Minimum
+ 0x0034, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x0038, // Range Minimum
+ 0x0038, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x003C, // Range Minimum
+ 0x003C, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x00A0, // Range Minimum
+ 0x00A0, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x00A4, // Range Minimum
+ 0x00A4, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x00A8, // Range Minimum
+ 0x00A8, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x00AC, // Range Minimum
+ 0x00AC, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x00B0, // Range Minimum
+ 0x00B0, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x00B4, // Range Minimum
+ 0x00B4, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x00B8, // Range Minimum
+ 0x00B8, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x00BC, // Range Minimum
+ 0x00BC, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x04D0, // Range Minimum
+ 0x04D0, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IRQNoFlags ()
+ {2}
+ })
+ }
+
+ Device (MATH)
+ {
+ Name (_HID, EisaId ("PNP0C04")) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x00F0, // Range Minimum
+ 0x00F0, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IRQNoFlags ()
+ {13}
+ })
+ }
+
+ Device (LDRC)
+ {
+ Name (_HID, EisaId ("PNP0C02")) // _HID: Hardware ID
+ Name (_UID, 0x02) // _UID: Unique ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x002E, // Range Minimum
+ 0x002E, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x004E, // Range Minimum
+ 0x004E, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x0061, // Range Minimum
+ 0x0061, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0063, // Range Minimum
+ 0x0063, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0065, // Range Minimum
+ 0x0065, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0067, // Range Minimum
+ 0x0067, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0080, // Range Minimum
+ 0x0080, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x0092, // Range Minimum
+ 0x0092, // Range Maximum
+ 0x01, // Alignment
+ 0x01, // Length
+ )
+ IO (Decode16,
+ 0x00B2, // Range Minimum
+ 0x00B2, // Range Maximum
+ 0x01, // Alignment
+ 0x02, // Length
+ )
+ IO (Decode16,
+ 0x0500, // Range Minimum
+ 0x0500, // Range Maximum
+ 0x01, // Alignment
+ 0x80, // Length
+ )
+ IO (Decode16,
+ 0x0480, // Range Minimum
+ 0x0480, // Range Maximum
+ 0x01, // Alignment
+ 0x40, // Length
+ )
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00")) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0070, // Range Minimum
+ 0x0070, // Range Maximum
+ 0x01, // Alignment
+ 0x08, // Length
+ )
+ })
+ }
+
+ Device (TIMR)
+ {
+ Name (_HID, EisaId ("PNP0100")) // _HID: Hardware ID
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
+ {
+ IO (Decode16,
+ 0x0040, // Range Minimum
+ 0x0040, // Range Maximum
+ 0x01, // Alignment
+ 0x04, // Length
+ )
+ IO (Decode16,
+ 0x0050, // Range Minimum
+ 0x0050, // Range Maximum
+ 0x10, // Alignment
+ 0x04, // Length
+ )
+ IRQNoFlags ()
+ {0}
+ })
+ }
+ }
+
+ Device (SATA)
+ {
+ Name (_ADR, 0x001F0002) // _ADR: Address
+ }
+
+ Device (SBUS)
+ {
+ Name (_ADR, 0x001F0003) // _ADR: Address
+ }
+
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities
+ {
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0xA9, 0x12, 0x95, 0x7C, 0x05, 0x17, 0xB4, 0x4C,
+ /* 0008 */ 0xAF, 0x7D, 0x50, 0x6A, 0x24, 0x23, 0xAB, 0x71
+ }))
+ {
+ Return (^XHC.POSC (Arg1, Arg2, Arg3))
+ }
+
+ If (LEqual (Arg0, Buffer (0x10)
+ {
+ /* 0000 */ 0x5B, 0x4D, 0xDB, 0x33, 0xF7, 0x1F, 0x1C, 0x40,
+ /* 0008 */ 0x96, 0x57, 0x74, 0x41, 0xC0, 0x3D, 0xD7, 0x66
+ }))
+ {
+ Return (Arg3)
+ }
+
+ CreateDWordField (Arg3, Zero, CDW1)
+ Or (CDW1, 0x04, CDW1)
+ Return (Arg3)
+ }
+
+ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
+ {
+ If (PICM)
+ {
+ Return (Package (0x0D)
+ {
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ Zero,
+ 0x15
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ Zero,
+ 0x14
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ Zero,
+ 0x13
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ Zero,
+ 0x15
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ Zero,
+ 0x11
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ Zero,
+ 0x17
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ Zero,
+ 0x10
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ Zero,
+ 0x12
+ }
+ })
+ }
+ Else
+ {
+ Return (Package (0x0D)
+ {
+ Package (0x04)
+ {
+ 0x0002FFFF,
+ Zero,
+ ^LPCB.LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x0014FFFF,
+ Zero,
+ ^LPCB.LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001BFFFF,
+ Zero,
+ ^LPCB.LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ Zero,
+ ^LPCB.LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ One,
+ ^LPCB.LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x02,
+ ^LPCB.LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001CFFFF,
+ 0x03,
+ ^LPCB.LNKE,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001DFFFF,
+ Zero,
+ ^LPCB.LNKD,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001AFFFF,
+ Zero,
+ ^LPCB.LNKF,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ Zero,
+ ^LPCB.LNKB,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ One,
+ ^LPCB.LNKH,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x02,
+ ^LPCB.LNKA,
+ Zero
+ },
+
+ Package (0x04)
+ {
+ 0x001FFFFF,
+ 0x03,
+ ^LPCB.LNKC,
+ Zero
+ }
+ })
+ }
+ }
+
+ Scope (GFX0)
+ {
+ Name (BRIG, Package (0x12)
+ {
+ 0x64,
+ 0x64,
+ 0x02,
+ 0x04,
+ 0x05,
+ 0x07,
+ 0x09,
+ 0x0B,
+ 0x0D,
+ 0x12,
+ 0x14,
+ 0x18,
+ 0x1D,
+ 0x21,
+ 0x28,
+ 0x32,
+ 0x43,
+ 0x64
+ })
+ }
+ }
+ }
+}
+
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/facp.dat b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/facp.dat
new file mode 100644
index 0000000..03f29a1
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/facp.dat
Binary files differ
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/facp.dsl b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/facp.dsl
new file mode 100644
index 0000000..0a98f7e
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/facp.dsl
@@ -0,0 +1,175 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML Disassembler version 20140214-64 [Mar 29 2014]
+ * Copyright (c) 2000 - 2014 Intel Corporation
+ *
+ * Disassembly of ./facp.dat, Sun Dec 27 13:15:45 2015
+ *
+ * ACPI Data Table [FACP]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)]
+[004h 0004 4] Table Length : 000000F4
+[008h 0008 1] Revision : 04
+[009h 0009 1] Checksum : 7B
+[00Ah 0010 6] Oem ID : "CORE "
+[010h 0016 8] Oem Table ID : "COREBOOT"
+[018h 0024 4] Oem Revision : 00000000
+[01Ch 0028 4] Asl Compiler ID : "CORE"
+[020h 0032 4] Asl Compiler Revision : 00000000
+
+[024h 0036 4] FACS Address : BFEB9240
+[028h 0040 4] DSDT Address : BFEB9280
+[02Ch 0044 1] Model : 01
+[02Dh 0045 1] PM Profile : 01 [Desktop]
+[02Eh 0046 2] SCI Interrupt : 0009
+[030h 0048 4] SMI Command Port : 000000B2
+[034h 0052 1] ACPI Enable Value : E1
+[035h 0053 1] ACPI Disable Value : 1E
+[036h 0054 1] S4BIOS Command : 00
+[037h 0055 1] P-State Control : 00
+[038h 0056 4] PM1A Event Block Address : 00000500
+[03Ch 0060 4] PM1B Event Block Address : 00000000
+[040h 0064 4] PM1A Control Block Address : 00000504
+[044h 0068 4] PM1B Control Block Address : 00000000
+[048h 0072 4] PM2 Control Block Address : 00000550
+[04Ch 0076 4] PM Timer Block Address : 00000508
+[050h 0080 4] GPE0 Block Address : 00000520
+[054h 0084 4] GPE1 Block Address : 00000000
+[058h 0088 1] PM1 Event Block Length : 04
+[059h 0089 1] PM1 Control Block Length : 02
+[05Ah 0090 1] PM2 Control Block Length : 01
+[05Bh 0091 1] PM Timer Block Length : 04
+[05Ch 0092 1] GPE0 Block Length : 10
+[05Dh 0093 1] GPE1 Block Length : 00
+[05Eh 0094 1] GPE1 Base Offset : 00
+[05Fh 0095 1] _CST Support : 00
+[060h 0096 2] C2 Latency : 0065
+[062h 0098 2] C3 Latency : 0057
+[064h 0100 2] CPU Cache Size : 0400
+[066h 0102 2] Cache Flush Stride : 0010
+[068h 0104 1] Duty Cycle Offset : 01
+[069h 0105 1] Duty Cycle Width : 00
+[06Ah 0106 1] RTC Day Alarm Index : 0D
+[06Bh 0107 1] RTC Month Alarm Index : 00
+[06Ch 0108 1] RTC Century Index : 00
+[06Dh 0109 2] Boot Flags (decoded below) : 0003
+ Legacy Devices Supported (V2) : 1
+ 8042 Present on ports 60/64 (V2) : 1
+ VGA Not Present (V4) : 0
+ MSI Not Supported (V4) : 0
+ PCIe ASPM Not Supported (V4) : 0
+ CMOS RTC Not Present (V5) : 0
+[06Fh 0111 1] Reserved : 00
+[070h 0112 4] Flags (decoded below) : 00008CA5
+ WBINVD instruction is operational (V1) : 1
+ WBINVD flushes all caches (V1) : 0
+ All CPUs support C1 (V1) : 1
+ C2 works on MP system (V1) : 0
+ Control Method Power Button (V1) : 0
+ Control Method Sleep Button (V1) : 1
+ RTC wake not in fixed reg space (V1) : 0
+ RTC can wake system from S4 (V1) : 1
+ 32-bit PM Timer (V1) : 0
+ Docking Supported (V1) : 0
+ Reset Register Supported (V2) : 1
+ Sealed Case (V3) : 1
+ Headless - No Video (V3) : 0
+ Use native instr after SLP_TYPx (V3) : 0
+ PCIEXP_WAK Bits Supported (V4) : 0
+ Use Platform Timer (V4) : 1
+ RTC_STS valid on S4 wake (V4) : 0
+ Remote Power-on capable (V4) : 0
+ Use APIC Cluster Model (V4) : 0
+ Use APIC Physical Destination Mode (V4) : 0
+ Hardware Reduced (V5) : 0
+ Low Power S0 Idle (V5) : 0
+
+[074h 0116 12] Reset Register : [Generic Address Structure]
+[074h 0116 1] Space ID : 01 [SystemIO]
+[075h 0117 1] Bit Width : 08
+[076h 0118 1] Bit Offset : 00
+[077h 0119 1] Encoded Access Width : 01 [Byte Access:8]
+[078h 0120 8] Address : 0000000000000CF9
+
+[080h 0128 1] Value to cause reset : 06
+[081h 0129 3] Reserved : 000000
+[084h 0132 8] FACS Address : 00000000BFEB9240
+[08Ch 0140 8] DSDT Address : 00000000BFEB9280
+[094h 0148 12] PM1A Event Block : [Generic Address Structure]
+[094h 0148 1] Space ID : 01 [SystemIO]
+[095h 0149 1] Bit Width : 20
+[096h 0150 1] Bit Offset : 00
+[097h 0151 1] Encoded Access Width : 03 [DWord Access:32]
+[098h 0152 8] Address : 0000000000000500
+
+[0A0h 0160 12] PM1B Event Block : [Generic Address Structure]
+[0A0h 0160 1] Space ID : 01 [SystemIO]
+[0A1h 0161 1] Bit Width : 00
+[0A2h 0162 1] Bit Offset : 00
+[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0A4h 0164 8] Address : 0000000000000000
+
+[0ACh 0172 12] PM1A Control Block : [Generic Address Structure]
+[0ACh 0172 1] Space ID : 01 [SystemIO]
+[0ADh 0173 1] Bit Width : 10
+[0AEh 0174 1] Bit Offset : 00
+[0AFh 0175 1] Encoded Access Width : 02 [Word Access:16]
+[0B0h 0176 8] Address : 0000000000000504
+
+[0B8h 0184 12] PM1B Control Block : [Generic Address Structure]
+[0B8h 0184 1] Space ID : 01 [SystemIO]
+[0B9h 0185 1] Bit Width : 00
+[0BAh 0186 1] Bit Offset : 00
+[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0BCh 0188 8] Address : 0000000000000000
+
+[0C4h 0196 12] PM2 Control Block : [Generic Address Structure]
+[0C4h 0196 1] Space ID : 01 [SystemIO]
+[0C5h 0197 1] Bit Width : 08
+[0C6h 0198 1] Bit Offset : 00
+[0C7h 0199 1] Encoded Access Width : 01 [Byte Access:8]
+[0C8h 0200 8] Address : 0000000000000550
+
+[0D0h 0208 12] PM Timer Block : [Generic Address Structure]
+[0D0h 0208 1] Space ID : 01 [SystemIO]
+[0D1h 0209 1] Bit Width : 20
+[0D2h 0210 1] Bit Offset : 00
+[0D3h 0211 1] Encoded Access Width : 03 [DWord Access:32]
+[0D4h 0212 8] Address : 0000000000000508
+
+[0DCh 0220 12] GPE0 Block : [Generic Address Structure]
+[0DCh 0220 1] Space ID : 01 [SystemIO]
+[0DDh 0221 1] Bit Width : 80
+[0DEh 0222 1] Bit Offset : 00
+[0DFh 0223 1] Encoded Access Width : 03 [DWord Access:32]
+[0E0h 0224 8] Address : 0000000000000520
+
+[0E8h 0232 12] GPE1 Block : [Generic Address Structure]
+[0E8h 0232 1] Space ID : 01 [SystemIO]
+[0E9h 0233 1] Bit Width : 00
+[0EAh 0234 1] Bit Offset : 00
+[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy]
+[0ECh 0236 8] Address : 0000000000000000
+
+
+Raw Table Data: Length 244 (0xF4)
+
+ 0000: 46 41 43 50 F4 00 00 00 04 7B 43 4F 52 45 20 20 FACP.....{CORE
+ 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 COREBOOT....CORE
+ 0020: 00 00 00 00 40 92 EB BF 80 92 EB BF 01 01 09 00 ....@...........
+ 0030: B2 00 00 00 E1 1E 00 00 00 05 00 00 00 00 00 00 ................
+ 0040: 04 05 00 00 00 00 00 00 50 05 00 00 08 05 00 00 ........P.......
+ 0050: 20 05 00 00 00 00 00 00 04 02 01 04 10 00 00 00 ...............
+ 0060: 65 00 57 00 00 04 10 00 01 00 0D 00 00 03 00 00 e.W.............
+ 0070: A5 8C 00 00 01 08 00 01 F9 0C 00 00 00 00 00 00 ................
+ 0080: 06 00 00 00 40 92 EB BF 00 00 00 00 80 92 EB BF ....@...........
+ 0090: 00 00 00 00 01 20 00 03 00 05 00 00 00 00 00 00 ..... ..........
+ 00A0: 01 00 00 00 00 00 00 00 00 00 00 00 01 10 00 02 ................
+ 00B0: 04 05 00 00 00 00 00 00 01 00 00 00 00 00 00 00 ................
+ 00C0: 00 00 00 00 01 08 00 01 50 05 00 00 00 00 00 00 ........P.......
+ 00D0: 01 20 00 03 08 05 00 00 00 00 00 00 01 80 00 03 . ..............
+ 00E0: 20 05 00 00 00 00 00 00 01 00 00 00 00 00 00 00 ...............
+ 00F0: 00 00 00 00 ....
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/facs.dat b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/facs.dat
new file mode 100644
index 0000000..63282ea
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/facs.dat
Binary files differ
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/facs.dsl b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/facs.dsl
new file mode 100644
index 0000000..828602a
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/facs.dsl
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML Disassembler version 20140214-64 [Mar 29 2014]
+ * Copyright (c) 2000 - 2014 Intel Corporation
+ *
+ * Disassembly of ./facs.dat, Sun Dec 27 13:15:45 2015
+ *
+ * ACPI Data Table [FACS]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "FACS"
+[004h 0004 4] Length : 00000040
+[008h 0008 4] Hardware Signature : 00000000
+[00Ch 0012 4] 32 Firmware Waking Vector : 00000000
+[010h 0016 4] Global Lock : 00000000
+[014h 0020 4] Flags (decoded below) : 00000000
+ S4BIOS Support Present : 0
+ 64-bit Wake Supported (V2) : 0
+[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000
+[020h 0032 1] Version : 01
+[021h 0033 3] Reserved : 000000
+[024h 0036 4] OspmFlags (decoded below) : 00000000
+ 64-bit Wake Env Required (V2) : 0
+
+Raw Table Data: Length 64 (0x40)
+
+ 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 FACS@...........
+ 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
+ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
+ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/hpet.dat b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/hpet.dat
new file mode 100644
index 0000000..487acb0
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/hpet.dat
Binary files differ
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/hpet.dsl b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/hpet.dsl
new file mode 100644
index 0000000..404422b
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/hpet.dsl
@@ -0,0 +1,43 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML Disassembler version 20140214-64 [Mar 29 2014]
+ * Copyright (c) 2000 - 2014 Intel Corporation
+ *
+ * Disassembly of ./hpet.dat, Sun Dec 27 13:15:45 2015
+ *
+ * ACPI Data Table [HPET]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "HPET" [High Precision Event Timer table]
+[004h 0004 4] Table Length : 00000038
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : 6B
+[00Ah 0010 6] Oem ID : "CORE "
+[010h 0016 8] Oem Table ID : "COREBOOT"
+[018h 0024 4] Oem Revision : 00000000
+[01Ch 0028 4] Asl Compiler ID : "CORE"
+[020h 0032 4] Asl Compiler Revision : 00000000
+
+[024h 0036 4] Hardware Block ID : 8086A701
+
+[028h 0040 12] Timer Block Register : [Generic Address Structure]
+[028h 0040 1] Space ID : 00 [SystemMemory]
+[029h 0041 1] Bit Width : 40
+[02Ah 0042 1] Bit Offset : 00
+[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy]
+[02Ch 0044 8] Address : 00000000FED00000
+
+[034h 0052 1] Sequence Number : 00
+[035h 0053 2] Minimum Clock Ticks : 0080
+[037h 0055 1] Flags (decoded below) : 00
+ 4K Page Protect : 0
+ 64K Page Protect : 0
+
+Raw Table Data: Length 56 (0x38)
+
+ 0000: 48 50 45 54 38 00 00 00 01 6B 43 4F 52 45 20 20 HPET8....kCORE
+ 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 COREBOOT....CORE
+ 0020: 00 00 00 00 01 A7 86 80 00 40 00 00 00 00 D0 FE .........@......
+ 0030: 00 00 00 00 00 80 00 00 ........
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/rsdp.dat b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/rsdp.dat
new file mode 100644
index 0000000..92f4afc
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/rsdp.dat
Binary files differ
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/rsdp.dsl b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/rsdp.dsl
new file mode 100644
index 0000000..363a52b
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/rsdp.dsl
@@ -0,0 +1,27 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML Disassembler version 20140214-64 [Mar 29 2014]
+ * Copyright (c) 2000 - 2014 Intel Corporation
+ *
+ * Disassembly of ./rsdp.dat, Sun Dec 27 13:15:45 2015
+ *
+ * ACPI Data Table [RSD ]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 8] Signature : "RSD PTR "
+[008h 0008 1] Checksum : 0C
+[009h 0009 6] Oem ID : "CORE "
+[00Fh 0015 1] Revision : 02
+[010h 0016 4] RSDT Address : BFEB9030
+[014h 0020 4] Length : 00000024
+[018h 0024 8] XSDT Address : 00000000BFEB90E0
+[020h 0032 1] Extended Checksum : C2
+[021h 0033 3] Reserved : 000000
+
+Raw Table Data: Length 36 (0x24)
+
+ 0000: 52 53 44 20 50 54 52 20 0C 43 4F 52 45 20 20 02 RSD PTR .CORE .
+ 0010: 30 90 EB BF 24 00 00 00 E0 90 EB BF 00 00 00 00 0...$...........
+ 0020: C2 00 00 00 ....
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/rsdt.dat b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/rsdt.dat
new file mode 100644
index 0000000..3e72e0b
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/rsdt.dat
Binary files differ
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/rsdt.dsl b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/rsdt.dsl
new file mode 100644
index 0000000..46177e2
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/rsdt.dsl
@@ -0,0 +1,35 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML Disassembler version 20140214-64 [Mar 29 2014]
+ * Copyright (c) 2000 - 2014 Intel Corporation
+ *
+ * Disassembly of ./rsdt.dat, Sun Dec 27 13:15:45 2015
+ *
+ * ACPI Data Table [RSDT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "RSDT" [Root System Description Table]
+[004h 0004 4] Table Length : 0000003C
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : F4
+[00Ah 0010 6] Oem ID : "CORE "
+[010h 0016 8] Oem Table ID : "COREBOOT"
+[018h 0024 4] Oem Revision : 00000000
+[01Ch 0028 4] Asl Compiler ID : "CORE"
+[020h 0032 4] Asl Compiler Revision : 00000000
+
+[024h 0036 4] ACPI Table Address 0 : BFEBB8B0
+[028h 0040 4] ACPI Table Address 1 : BFEBB9B0
+[02Ch 0044 4] ACPI Table Address 2 : BFEBE130
+[030h 0048 4] ACPI Table Address 3 : BFEBE170
+[034h 0052 4] ACPI Table Address 4 : BFEBE200
+[038h 0056 4] ACPI Table Address 5 : BFEBE2B0
+
+Raw Table Data: Length 60 (0x3C)
+
+ 0000: 52 53 44 54 3C 00 00 00 01 F4 43 4F 52 45 20 20 RSDT<.....CORE
+ 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 COREBOOT....CORE
+ 0020: 00 00 00 00 B0 B8 EB BF B0 B9 EB BF 30 E1 EB BF ............0...
+ 0030: 70 E1 EB BF 00 E2 EB BF B0 E2 EB BF p...........
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/ssdt.dat b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/ssdt.dat
new file mode 100644
index 0000000..62a7f99
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/ssdt.dat
Binary files differ
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/ssdt.dsl b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/ssdt.dsl
new file mode 100644
index 0000000..a4bfdf1
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/ssdt.dsl
@@ -0,0 +1,3303 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML Disassembler version 20140214-64 [Mar 29 2014]
+ * Copyright (c) 2000 - 2014 Intel Corporation
+ *
+ * Disassembly of ./ssdt.dat, Sun Dec 27 13:15:45 2015
+ *
+ * Original Table Header:
+ * Signature "SSDT"
+ * Length 0x0000277D (10109)
+ * Revision 0x02
+ * Checksum 0xCE
+ * OEM ID "CORE "
+ * OEM Table ID "COREBOOT"
+ * OEM Revision 0x0000002A (42)
+ * Compiler ID "CORE"
+ * Compiler Version 0x0000002A (42)
+ */
+DefinitionBlock ("./ssdt.aml", "SSDT", 2, "CORE ", "COREBOOT", 0x0000002A)
+{
+ /*
+ * iASL Warning: There were 2 external control methods found during
+ * disassembly, but additional ACPI tables to resolve these externals
+ * were not specified. This resulting disassembler output file may not
+ * compile because the disassembler did not know how many arguments
+ * to assign to these methods. To specify the tables needed to resolve
+ * external control method references, the -e option can be used to
+ * specify the filenames. Example iASL invocations:
+ * iasl -e ssdt1.aml ssdt2.aml ssdt3.aml -d dsdt.aml
+ * iasl -e dsdt.aml ssdt2.aml -d ssdt1.aml
+ * iasl -e ssdt*.aml -d dsdt.aml
+ *
+ * In addition, the -fe option can be used to specify a file containing
+ * control method external declarations with the associated method
+ * argument counts. Each line of the file must be of the form:
+ * External (<method pathname>, MethodObj, <argument count>)
+ */
+ External (_SB_.PCI0.GFX0.XBCM, MethodObj) // Warning: Unresolved Method, guessing 1 arguments (may be incorrect, see warning above)
+ External (_SB_.PCI0.GFX0.XDSS, MethodObj) // Warning: Unresolved Method, guessing 2 arguments (may be incorrect, see warning above)
+
+ External (_SB_.PCI0.GFX0, DeviceObj)
+ External (_SB_.PCI0.GFX0.XBCL, IntObj)
+ External (_SB_.PCI0.GFX0.XBQC, IntObj)
+ External (_SB_.PCI0.GFX0.XDCS, IntObj)
+ External (_SB_.PCI0.GFX0.XDGS, IntObj)
+ External (_SB_.PCI0.SATA, DeviceObj)
+ External (PPCM, IntObj)
+ External (PWRS, IntObj)
+ External (TLVL, IntObj)
+
+ Processor (\_PR.CP00, 0x00, 0x00000510, 0x06)
+ {
+ Name (_PCT, Package (0x02) // _PCT: Performance Control
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilites
+ {
+ Return (PPCM)
+ }
+
+ Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
+ {
+ Package (0x05)
+ {
+ 0x05,
+ 0x00,
+ 0x00000000,
+ 0x000000FE,
+ 0x00000008
+ }
+ })
+ Name (_PSS, Package (0x06) // _PSS: Performance Supported States
+ {
+ Package (0x06)
+ {
+ 0x00000D49,
+ 0x00012CC8,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00002700,
+ 0x00002700
+ },
+
+ Package (0x06)
+ {
+ 0x00000D48,
+ 0x00012CC8,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00002200,
+ 0x00002200
+ },
+
+ Package (0x06)
+ {
+ 0x00000AF0,
+ 0x0000E6B5,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001C00,
+ 0x00001C00
+ },
+
+ Package (0x06)
+ {
+ 0x00000960,
+ 0x0000BC83,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001800,
+ 0x00001800
+ },
+
+ Package (0x06)
+ {
+ 0x000007D0,
+ 0x000095CC,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001400,
+ 0x00001400
+ },
+
+ Package (0x06)
+ {
+ 0x00000640,
+ 0x000071CC,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001000,
+ 0x00001000
+ }
+ })
+ Method (_CST, 0, NotSerialized) // _CST: C-States
+ {
+ If (PWRS)
+ {
+ Return (Package (0x04)
+ {
+ 0x03,
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000000, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000001,
+ 0x00000001,
+ 0x000003E8
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000010, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000002,
+ 0x0000003F,
+ 0x000001F4
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000030, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000003,
+ 0x0000005A,
+ 0x000000C8
+ }
+ })
+ }
+
+ Return (Package (0x04)
+ {
+ 0x03,
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000000, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000001,
+ 0x00000001,
+ 0x000003E8
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000010, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000002,
+ 0x0000003F,
+ 0x000001F4
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000030, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000003,
+ 0x0000005A,
+ 0x000000C8
+ }
+ })
+ }
+
+ Name (_TSD, Package (0x01) // _TSD: Throttling State Dependencies
+ {
+ Package (0x05)
+ {
+ 0x05,
+ 0x00,
+ 0x00000000,
+ 0x000000FC,
+ 0x00000008
+ }
+ })
+ Name (_PTC, Package (0x02) // _PTC: Processor Throttling Control
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Method (_TPC, 0, NotSerialized) // _TPC: Throttling Present Capabilities
+ {
+ Return (\TLVL)
+ }
+
+ Name (_TSS, Package (0x0F) // _TSS: Throttling Supported States
+ {
+ Package (0x05)
+ {
+ 0x00000064,
+ 0x000003E8,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000005E,
+ 0x000003AC,
+ 0x00000000,
+ 0x0000001F,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000058,
+ 0x00000370,
+ 0x00000000,
+ 0x0000001E,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000052,
+ 0x00000334,
+ 0x00000000,
+ 0x0000001D,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000004B,
+ 0x000002F8,
+ 0x00000000,
+ 0x0000001C,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000045,
+ 0x000002BC,
+ 0x00000000,
+ 0x0000001B,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000003F,
+ 0x00000280,
+ 0x00000000,
+ 0x0000001A,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000039,
+ 0x00000244,
+ 0x00000000,
+ 0x00000019,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000032,
+ 0x00000208,
+ 0x00000000,
+ 0x00000018,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000002C,
+ 0x000001CC,
+ 0x00000000,
+ 0x00000017,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000026,
+ 0x00000190,
+ 0x00000000,
+ 0x00000016,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000020,
+ 0x00000154,
+ 0x00000000,
+ 0x00000015,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000019,
+ 0x00000118,
+ 0x00000000,
+ 0x00000014,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000013,
+ 0x000000DC,
+ 0x00000000,
+ 0x00000013,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000000D,
+ 0x000000A0,
+ 0x00000000,
+ 0x00000012,
+ 0x00000000
+ }
+ })
+ }
+
+ Processor (\_PR.CP01, 0x01, 0x00000000, 0x00)
+ {
+ Name (_PCT, Package (0x02) // _PCT: Performance Control
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilites
+ {
+ Return (PPCM)
+ }
+
+ Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
+ {
+ Package (0x05)
+ {
+ 0x05,
+ 0x00,
+ 0x00000000,
+ 0x000000FE,
+ 0x00000008
+ }
+ })
+ Name (_PSS, Package (0x06) // _PSS: Performance Supported States
+ {
+ Package (0x06)
+ {
+ 0x00000D49,
+ 0x00012CC8,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00002700,
+ 0x00002700
+ },
+
+ Package (0x06)
+ {
+ 0x00000D48,
+ 0x00012CC8,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00002200,
+ 0x00002200
+ },
+
+ Package (0x06)
+ {
+ 0x00000AF0,
+ 0x0000E6B5,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001C00,
+ 0x00001C00
+ },
+
+ Package (0x06)
+ {
+ 0x00000960,
+ 0x0000BC83,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001800,
+ 0x00001800
+ },
+
+ Package (0x06)
+ {
+ 0x000007D0,
+ 0x000095CC,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001400,
+ 0x00001400
+ },
+
+ Package (0x06)
+ {
+ 0x00000640,
+ 0x000071CC,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001000,
+ 0x00001000
+ }
+ })
+ Method (_CST, 0, NotSerialized) // _CST: C-States
+ {
+ If (PWRS)
+ {
+ Return (Package (0x04)
+ {
+ 0x03,
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000000, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000001,
+ 0x00000001,
+ 0x000003E8
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000010, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000002,
+ 0x0000003F,
+ 0x000001F4
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000030, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000003,
+ 0x0000005A,
+ 0x000000C8
+ }
+ })
+ }
+
+ Return (Package (0x04)
+ {
+ 0x03,
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000000, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000001,
+ 0x00000001,
+ 0x000003E8
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000010, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000002,
+ 0x0000003F,
+ 0x000001F4
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000030, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000003,
+ 0x0000005A,
+ 0x000000C8
+ }
+ })
+ }
+
+ Name (_TSD, Package (0x01) // _TSD: Throttling State Dependencies
+ {
+ Package (0x05)
+ {
+ 0x05,
+ 0x00,
+ 0x00000000,
+ 0x000000FC,
+ 0x00000008
+ }
+ })
+ Name (_PTC, Package (0x02) // _PTC: Processor Throttling Control
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Method (_TPC, 0, NotSerialized) // _TPC: Throttling Present Capabilities
+ {
+ Return (\TLVL)
+ }
+
+ Name (_TSS, Package (0x0F) // _TSS: Throttling Supported States
+ {
+ Package (0x05)
+ {
+ 0x00000064,
+ 0x000003E8,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000005E,
+ 0x000003AC,
+ 0x00000000,
+ 0x0000001F,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000058,
+ 0x00000370,
+ 0x00000000,
+ 0x0000001E,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000052,
+ 0x00000334,
+ 0x00000000,
+ 0x0000001D,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000004B,
+ 0x000002F8,
+ 0x00000000,
+ 0x0000001C,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000045,
+ 0x000002BC,
+ 0x00000000,
+ 0x0000001B,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000003F,
+ 0x00000280,
+ 0x00000000,
+ 0x0000001A,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000039,
+ 0x00000244,
+ 0x00000000,
+ 0x00000019,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000032,
+ 0x00000208,
+ 0x00000000,
+ 0x00000018,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000002C,
+ 0x000001CC,
+ 0x00000000,
+ 0x00000017,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000026,
+ 0x00000190,
+ 0x00000000,
+ 0x00000016,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000020,
+ 0x00000154,
+ 0x00000000,
+ 0x00000015,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000019,
+ 0x00000118,
+ 0x00000000,
+ 0x00000014,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000013,
+ 0x000000DC,
+ 0x00000000,
+ 0x00000013,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000000D,
+ 0x000000A0,
+ 0x00000000,
+ 0x00000012,
+ 0x00000000
+ }
+ })
+ }
+
+ Processor (\_PR.CP02, 0x02, 0x00000000, 0x00)
+ {
+ Name (_PCT, Package (0x02) // _PCT: Performance Control
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilites
+ {
+ Return (PPCM)
+ }
+
+ Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
+ {
+ Package (0x05)
+ {
+ 0x05,
+ 0x00,
+ 0x00000000,
+ 0x000000FE,
+ 0x00000008
+ }
+ })
+ Name (_PSS, Package (0x06) // _PSS: Performance Supported States
+ {
+ Package (0x06)
+ {
+ 0x00000D49,
+ 0x00012CC8,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00002700,
+ 0x00002700
+ },
+
+ Package (0x06)
+ {
+ 0x00000D48,
+ 0x00012CC8,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00002200,
+ 0x00002200
+ },
+
+ Package (0x06)
+ {
+ 0x00000AF0,
+ 0x0000E6B5,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001C00,
+ 0x00001C00
+ },
+
+ Package (0x06)
+ {
+ 0x00000960,
+ 0x0000BC83,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001800,
+ 0x00001800
+ },
+
+ Package (0x06)
+ {
+ 0x000007D0,
+ 0x000095CC,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001400,
+ 0x00001400
+ },
+
+ Package (0x06)
+ {
+ 0x00000640,
+ 0x000071CC,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001000,
+ 0x00001000
+ }
+ })
+ Method (_CST, 0, NotSerialized) // _CST: C-States
+ {
+ If (PWRS)
+ {
+ Return (Package (0x04)
+ {
+ 0x03,
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000000, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000001,
+ 0x00000001,
+ 0x000003E8
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000010, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000002,
+ 0x0000003F,
+ 0x000001F4
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000030, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000003,
+ 0x0000005A,
+ 0x000000C8
+ }
+ })
+ }
+
+ Return (Package (0x04)
+ {
+ 0x03,
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000000, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000001,
+ 0x00000001,
+ 0x000003E8
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000010, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000002,
+ 0x0000003F,
+ 0x000001F4
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000030, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000003,
+ 0x0000005A,
+ 0x000000C8
+ }
+ })
+ }
+
+ Name (_TSD, Package (0x01) // _TSD: Throttling State Dependencies
+ {
+ Package (0x05)
+ {
+ 0x05,
+ 0x00,
+ 0x00000000,
+ 0x000000FC,
+ 0x00000008
+ }
+ })
+ Name (_PTC, Package (0x02) // _PTC: Processor Throttling Control
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Method (_TPC, 0, NotSerialized) // _TPC: Throttling Present Capabilities
+ {
+ Return (\TLVL)
+ }
+
+ Name (_TSS, Package (0x0F) // _TSS: Throttling Supported States
+ {
+ Package (0x05)
+ {
+ 0x00000064,
+ 0x000003E8,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000005E,
+ 0x000003AC,
+ 0x00000000,
+ 0x0000001F,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000058,
+ 0x00000370,
+ 0x00000000,
+ 0x0000001E,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000052,
+ 0x00000334,
+ 0x00000000,
+ 0x0000001D,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000004B,
+ 0x000002F8,
+ 0x00000000,
+ 0x0000001C,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000045,
+ 0x000002BC,
+ 0x00000000,
+ 0x0000001B,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000003F,
+ 0x00000280,
+ 0x00000000,
+ 0x0000001A,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000039,
+ 0x00000244,
+ 0x00000000,
+ 0x00000019,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000032,
+ 0x00000208,
+ 0x00000000,
+ 0x00000018,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000002C,
+ 0x000001CC,
+ 0x00000000,
+ 0x00000017,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000026,
+ 0x00000190,
+ 0x00000000,
+ 0x00000016,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000020,
+ 0x00000154,
+ 0x00000000,
+ 0x00000015,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000019,
+ 0x00000118,
+ 0x00000000,
+ 0x00000014,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000013,
+ 0x000000DC,
+ 0x00000000,
+ 0x00000013,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000000D,
+ 0x000000A0,
+ 0x00000000,
+ 0x00000012,
+ 0x00000000
+ }
+ })
+ }
+
+ Processor (\_PR.CP03, 0x03, 0x00000000, 0x00)
+ {
+ Name (_PCT, Package (0x02) // _PCT: Performance Control
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilites
+ {
+ Return (PPCM)
+ }
+
+ Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
+ {
+ Package (0x05)
+ {
+ 0x05,
+ 0x00,
+ 0x00000000,
+ 0x000000FE,
+ 0x00000008
+ }
+ })
+ Name (_PSS, Package (0x06) // _PSS: Performance Supported States
+ {
+ Package (0x06)
+ {
+ 0x00000D49,
+ 0x00012CC8,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00002700,
+ 0x00002700
+ },
+
+ Package (0x06)
+ {
+ 0x00000D48,
+ 0x00012CC8,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00002200,
+ 0x00002200
+ },
+
+ Package (0x06)
+ {
+ 0x00000AF0,
+ 0x0000E6B5,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001C00,
+ 0x00001C00
+ },
+
+ Package (0x06)
+ {
+ 0x00000960,
+ 0x0000BC83,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001800,
+ 0x00001800
+ },
+
+ Package (0x06)
+ {
+ 0x000007D0,
+ 0x000095CC,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001400,
+ 0x00001400
+ },
+
+ Package (0x06)
+ {
+ 0x00000640,
+ 0x000071CC,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001000,
+ 0x00001000
+ }
+ })
+ Method (_CST, 0, NotSerialized) // _CST: C-States
+ {
+ If (PWRS)
+ {
+ Return (Package (0x04)
+ {
+ 0x03,
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000000, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000001,
+ 0x00000001,
+ 0x000003E8
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000010, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000002,
+ 0x0000003F,
+ 0x000001F4
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000030, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000003,
+ 0x0000005A,
+ 0x000000C8
+ }
+ })
+ }
+
+ Return (Package (0x04)
+ {
+ 0x03,
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000000, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000001,
+ 0x00000001,
+ 0x000003E8
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000010, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000002,
+ 0x0000003F,
+ 0x000001F4
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000030, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000003,
+ 0x0000005A,
+ 0x000000C8
+ }
+ })
+ }
+
+ Name (_TSD, Package (0x01) // _TSD: Throttling State Dependencies
+ {
+ Package (0x05)
+ {
+ 0x05,
+ 0x00,
+ 0x00000000,
+ 0x000000FC,
+ 0x00000008
+ }
+ })
+ Name (_PTC, Package (0x02) // _PTC: Processor Throttling Control
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Method (_TPC, 0, NotSerialized) // _TPC: Throttling Present Capabilities
+ {
+ Return (\TLVL)
+ }
+
+ Name (_TSS, Package (0x0F) // _TSS: Throttling Supported States
+ {
+ Package (0x05)
+ {
+ 0x00000064,
+ 0x000003E8,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000005E,
+ 0x000003AC,
+ 0x00000000,
+ 0x0000001F,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000058,
+ 0x00000370,
+ 0x00000000,
+ 0x0000001E,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000052,
+ 0x00000334,
+ 0x00000000,
+ 0x0000001D,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000004B,
+ 0x000002F8,
+ 0x00000000,
+ 0x0000001C,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000045,
+ 0x000002BC,
+ 0x00000000,
+ 0x0000001B,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000003F,
+ 0x00000280,
+ 0x00000000,
+ 0x0000001A,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000039,
+ 0x00000244,
+ 0x00000000,
+ 0x00000019,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000032,
+ 0x00000208,
+ 0x00000000,
+ 0x00000018,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000002C,
+ 0x000001CC,
+ 0x00000000,
+ 0x00000017,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000026,
+ 0x00000190,
+ 0x00000000,
+ 0x00000016,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000020,
+ 0x00000154,
+ 0x00000000,
+ 0x00000015,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000019,
+ 0x00000118,
+ 0x00000000,
+ 0x00000014,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000013,
+ 0x000000DC,
+ 0x00000000,
+ 0x00000013,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000000D,
+ 0x000000A0,
+ 0x00000000,
+ 0x00000012,
+ 0x00000000
+ }
+ })
+ }
+
+ Processor (\_PR.CP04, 0x04, 0x00000000, 0x00)
+ {
+ Name (_PCT, Package (0x02) // _PCT: Performance Control
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilites
+ {
+ Return (PPCM)
+ }
+
+ Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
+ {
+ Package (0x05)
+ {
+ 0x05,
+ 0x00,
+ 0x00000000,
+ 0x000000FE,
+ 0x00000008
+ }
+ })
+ Name (_PSS, Package (0x06) // _PSS: Performance Supported States
+ {
+ Package (0x06)
+ {
+ 0x00000D49,
+ 0x00012CC8,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00002700,
+ 0x00002700
+ },
+
+ Package (0x06)
+ {
+ 0x00000D48,
+ 0x00012CC8,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00002200,
+ 0x00002200
+ },
+
+ Package (0x06)
+ {
+ 0x00000AF0,
+ 0x0000E6B5,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001C00,
+ 0x00001C00
+ },
+
+ Package (0x06)
+ {
+ 0x00000960,
+ 0x0000BC83,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001800,
+ 0x00001800
+ },
+
+ Package (0x06)
+ {
+ 0x000007D0,
+ 0x000095CC,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001400,
+ 0x00001400
+ },
+
+ Package (0x06)
+ {
+ 0x00000640,
+ 0x000071CC,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001000,
+ 0x00001000
+ }
+ })
+ Method (_CST, 0, NotSerialized) // _CST: C-States
+ {
+ If (PWRS)
+ {
+ Return (Package (0x04)
+ {
+ 0x03,
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000000, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000001,
+ 0x00000001,
+ 0x000003E8
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000010, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000002,
+ 0x0000003F,
+ 0x000001F4
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000030, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000003,
+ 0x0000005A,
+ 0x000000C8
+ }
+ })
+ }
+
+ Return (Package (0x04)
+ {
+ 0x03,
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000000, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000001,
+ 0x00000001,
+ 0x000003E8
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000010, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000002,
+ 0x0000003F,
+ 0x000001F4
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000030, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000003,
+ 0x0000005A,
+ 0x000000C8
+ }
+ })
+ }
+
+ Name (_TSD, Package (0x01) // _TSD: Throttling State Dependencies
+ {
+ Package (0x05)
+ {
+ 0x05,
+ 0x00,
+ 0x00000000,
+ 0x000000FC,
+ 0x00000008
+ }
+ })
+ Name (_PTC, Package (0x02) // _PTC: Processor Throttling Control
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Method (_TPC, 0, NotSerialized) // _TPC: Throttling Present Capabilities
+ {
+ Return (\TLVL)
+ }
+
+ Name (_TSS, Package (0x0F) // _TSS: Throttling Supported States
+ {
+ Package (0x05)
+ {
+ 0x00000064,
+ 0x000003E8,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000005E,
+ 0x000003AC,
+ 0x00000000,
+ 0x0000001F,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000058,
+ 0x00000370,
+ 0x00000000,
+ 0x0000001E,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000052,
+ 0x00000334,
+ 0x00000000,
+ 0x0000001D,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000004B,
+ 0x000002F8,
+ 0x00000000,
+ 0x0000001C,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000045,
+ 0x000002BC,
+ 0x00000000,
+ 0x0000001B,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000003F,
+ 0x00000280,
+ 0x00000000,
+ 0x0000001A,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000039,
+ 0x00000244,
+ 0x00000000,
+ 0x00000019,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000032,
+ 0x00000208,
+ 0x00000000,
+ 0x00000018,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000002C,
+ 0x000001CC,
+ 0x00000000,
+ 0x00000017,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000026,
+ 0x00000190,
+ 0x00000000,
+ 0x00000016,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000020,
+ 0x00000154,
+ 0x00000000,
+ 0x00000015,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000019,
+ 0x00000118,
+ 0x00000000,
+ 0x00000014,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000013,
+ 0x000000DC,
+ 0x00000000,
+ 0x00000013,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000000D,
+ 0x000000A0,
+ 0x00000000,
+ 0x00000012,
+ 0x00000000
+ }
+ })
+ }
+
+ Processor (\_PR.CP05, 0x05, 0x00000000, 0x00)
+ {
+ Name (_PCT, Package (0x02) // _PCT: Performance Control
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilites
+ {
+ Return (PPCM)
+ }
+
+ Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
+ {
+ Package (0x05)
+ {
+ 0x05,
+ 0x00,
+ 0x00000000,
+ 0x000000FE,
+ 0x00000008
+ }
+ })
+ Name (_PSS, Package (0x06) // _PSS: Performance Supported States
+ {
+ Package (0x06)
+ {
+ 0x00000D49,
+ 0x00012CC8,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00002700,
+ 0x00002700
+ },
+
+ Package (0x06)
+ {
+ 0x00000D48,
+ 0x00012CC8,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00002200,
+ 0x00002200
+ },
+
+ Package (0x06)
+ {
+ 0x00000AF0,
+ 0x0000E6B5,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001C00,
+ 0x00001C00
+ },
+
+ Package (0x06)
+ {
+ 0x00000960,
+ 0x0000BC83,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001800,
+ 0x00001800
+ },
+
+ Package (0x06)
+ {
+ 0x000007D0,
+ 0x000095CC,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001400,
+ 0x00001400
+ },
+
+ Package (0x06)
+ {
+ 0x00000640,
+ 0x000071CC,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001000,
+ 0x00001000
+ }
+ })
+ Method (_CST, 0, NotSerialized) // _CST: C-States
+ {
+ If (PWRS)
+ {
+ Return (Package (0x04)
+ {
+ 0x03,
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000000, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000001,
+ 0x00000001,
+ 0x000003E8
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000010, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000002,
+ 0x0000003F,
+ 0x000001F4
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000030, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000003,
+ 0x0000005A,
+ 0x000000C8
+ }
+ })
+ }
+
+ Return (Package (0x04)
+ {
+ 0x03,
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000000, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000001,
+ 0x00000001,
+ 0x000003E8
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000010, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000002,
+ 0x0000003F,
+ 0x000001F4
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000030, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000003,
+ 0x0000005A,
+ 0x000000C8
+ }
+ })
+ }
+
+ Name (_TSD, Package (0x01) // _TSD: Throttling State Dependencies
+ {
+ Package (0x05)
+ {
+ 0x05,
+ 0x00,
+ 0x00000000,
+ 0x000000FC,
+ 0x00000008
+ }
+ })
+ Name (_PTC, Package (0x02) // _PTC: Processor Throttling Control
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Method (_TPC, 0, NotSerialized) // _TPC: Throttling Present Capabilities
+ {
+ Return (\TLVL)
+ }
+
+ Name (_TSS, Package (0x0F) // _TSS: Throttling Supported States
+ {
+ Package (0x05)
+ {
+ 0x00000064,
+ 0x000003E8,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000005E,
+ 0x000003AC,
+ 0x00000000,
+ 0x0000001F,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000058,
+ 0x00000370,
+ 0x00000000,
+ 0x0000001E,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000052,
+ 0x00000334,
+ 0x00000000,
+ 0x0000001D,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000004B,
+ 0x000002F8,
+ 0x00000000,
+ 0x0000001C,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000045,
+ 0x000002BC,
+ 0x00000000,
+ 0x0000001B,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000003F,
+ 0x00000280,
+ 0x00000000,
+ 0x0000001A,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000039,
+ 0x00000244,
+ 0x00000000,
+ 0x00000019,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000032,
+ 0x00000208,
+ 0x00000000,
+ 0x00000018,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000002C,
+ 0x000001CC,
+ 0x00000000,
+ 0x00000017,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000026,
+ 0x00000190,
+ 0x00000000,
+ 0x00000016,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000020,
+ 0x00000154,
+ 0x00000000,
+ 0x00000015,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000019,
+ 0x00000118,
+ 0x00000000,
+ 0x00000014,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000013,
+ 0x000000DC,
+ 0x00000000,
+ 0x00000013,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000000D,
+ 0x000000A0,
+ 0x00000000,
+ 0x00000012,
+ 0x00000000
+ }
+ })
+ }
+
+ Processor (\_PR.CP06, 0x06, 0x00000000, 0x00)
+ {
+ Name (_PCT, Package (0x02) // _PCT: Performance Control
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilites
+ {
+ Return (PPCM)
+ }
+
+ Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
+ {
+ Package (0x05)
+ {
+ 0x05,
+ 0x00,
+ 0x00000000,
+ 0x000000FE,
+ 0x00000008
+ }
+ })
+ Name (_PSS, Package (0x06) // _PSS: Performance Supported States
+ {
+ Package (0x06)
+ {
+ 0x00000D49,
+ 0x00012CC8,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00002700,
+ 0x00002700
+ },
+
+ Package (0x06)
+ {
+ 0x00000D48,
+ 0x00012CC8,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00002200,
+ 0x00002200
+ },
+
+ Package (0x06)
+ {
+ 0x00000AF0,
+ 0x0000E6B5,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001C00,
+ 0x00001C00
+ },
+
+ Package (0x06)
+ {
+ 0x00000960,
+ 0x0000BC83,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001800,
+ 0x00001800
+ },
+
+ Package (0x06)
+ {
+ 0x000007D0,
+ 0x000095CC,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001400,
+ 0x00001400
+ },
+
+ Package (0x06)
+ {
+ 0x00000640,
+ 0x000071CC,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001000,
+ 0x00001000
+ }
+ })
+ Method (_CST, 0, NotSerialized) // _CST: C-States
+ {
+ If (PWRS)
+ {
+ Return (Package (0x04)
+ {
+ 0x03,
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000000, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000001,
+ 0x00000001,
+ 0x000003E8
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000010, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000002,
+ 0x0000003F,
+ 0x000001F4
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000030, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000003,
+ 0x0000005A,
+ 0x000000C8
+ }
+ })
+ }
+
+ Return (Package (0x04)
+ {
+ 0x03,
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000000, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000001,
+ 0x00000001,
+ 0x000003E8
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000010, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000002,
+ 0x0000003F,
+ 0x000001F4
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000030, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000003,
+ 0x0000005A,
+ 0x000000C8
+ }
+ })
+ }
+
+ Name (_TSD, Package (0x01) // _TSD: Throttling State Dependencies
+ {
+ Package (0x05)
+ {
+ 0x05,
+ 0x00,
+ 0x00000000,
+ 0x000000FC,
+ 0x00000008
+ }
+ })
+ Name (_PTC, Package (0x02) // _PTC: Processor Throttling Control
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Method (_TPC, 0, NotSerialized) // _TPC: Throttling Present Capabilities
+ {
+ Return (\TLVL)
+ }
+
+ Name (_TSS, Package (0x0F) // _TSS: Throttling Supported States
+ {
+ Package (0x05)
+ {
+ 0x00000064,
+ 0x000003E8,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000005E,
+ 0x000003AC,
+ 0x00000000,
+ 0x0000001F,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000058,
+ 0x00000370,
+ 0x00000000,
+ 0x0000001E,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000052,
+ 0x00000334,
+ 0x00000000,
+ 0x0000001D,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000004B,
+ 0x000002F8,
+ 0x00000000,
+ 0x0000001C,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000045,
+ 0x000002BC,
+ 0x00000000,
+ 0x0000001B,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000003F,
+ 0x00000280,
+ 0x00000000,
+ 0x0000001A,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000039,
+ 0x00000244,
+ 0x00000000,
+ 0x00000019,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000032,
+ 0x00000208,
+ 0x00000000,
+ 0x00000018,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000002C,
+ 0x000001CC,
+ 0x00000000,
+ 0x00000017,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000026,
+ 0x00000190,
+ 0x00000000,
+ 0x00000016,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000020,
+ 0x00000154,
+ 0x00000000,
+ 0x00000015,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000019,
+ 0x00000118,
+ 0x00000000,
+ 0x00000014,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000013,
+ 0x000000DC,
+ 0x00000000,
+ 0x00000013,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000000D,
+ 0x000000A0,
+ 0x00000000,
+ 0x00000012,
+ 0x00000000
+ }
+ })
+ }
+
+ Processor (\_PR.CP07, 0x07, 0x00000000, 0x00)
+ {
+ Name (_PCT, Package (0x02) // _PCT: Performance Control
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Method (_PPC, 0, NotSerialized) // _PPC: Performance Present Capabilites
+ {
+ Return (PPCM)
+ }
+
+ Name (_PSD, Package (0x01) // _PSD: Power State Dependencies
+ {
+ Package (0x05)
+ {
+ 0x05,
+ 0x00,
+ 0x00000000,
+ 0x000000FE,
+ 0x00000008
+ }
+ })
+ Name (_PSS, Package (0x06) // _PSS: Performance Supported States
+ {
+ Package (0x06)
+ {
+ 0x00000D49,
+ 0x00012CC8,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00002700,
+ 0x00002700
+ },
+
+ Package (0x06)
+ {
+ 0x00000D48,
+ 0x00012CC8,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00002200,
+ 0x00002200
+ },
+
+ Package (0x06)
+ {
+ 0x00000AF0,
+ 0x0000E6B5,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001C00,
+ 0x00001C00
+ },
+
+ Package (0x06)
+ {
+ 0x00000960,
+ 0x0000BC83,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001800,
+ 0x00001800
+ },
+
+ Package (0x06)
+ {
+ 0x000007D0,
+ 0x000095CC,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001400,
+ 0x00001400
+ },
+
+ Package (0x06)
+ {
+ 0x00000640,
+ 0x000071CC,
+ 0x0000000A,
+ 0x0000000A,
+ 0x00001000,
+ 0x00001000
+ }
+ })
+ Method (_CST, 0, NotSerialized) // _CST: C-States
+ {
+ If (PWRS)
+ {
+ Return (Package (0x04)
+ {
+ 0x03,
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000000, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000001,
+ 0x00000001,
+ 0x000003E8
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000010, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000002,
+ 0x0000003F,
+ 0x000001F4
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000030, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000003,
+ 0x0000005A,
+ 0x000000C8
+ }
+ })
+ }
+
+ Return (Package (0x04)
+ {
+ 0x03,
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000000, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000001,
+ 0x00000001,
+ 0x000003E8
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000010, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000002,
+ 0x0000003F,
+ 0x000001F4
+ },
+
+ Package (0x04)
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x01, // Bit Width
+ 0x02, // Bit Offset
+ 0x0000000000000030, // Address
+ 0x01, // Access Size
+ )
+ },
+
+ 0x00000003,
+ 0x0000005A,
+ 0x000000C8
+ }
+ })
+ }
+
+ Name (_TSD, Package (0x01) // _TSD: Throttling State Dependencies
+ {
+ Package (0x05)
+ {
+ 0x05,
+ 0x00,
+ 0x00000000,
+ 0x000000FC,
+ 0x00000008
+ }
+ })
+ Name (_PTC, Package (0x02) // _PTC: Processor Throttling Control
+ {
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ },
+
+ ResourceTemplate ()
+ {
+ Register (FFixedHW,
+ 0x00, // Bit Width
+ 0x00, // Bit Offset
+ 0x0000000000000000, // Address
+ ,)
+ }
+ })
+ Method (_TPC, 0, NotSerialized) // _TPC: Throttling Present Capabilities
+ {
+ Return (\TLVL)
+ }
+
+ Name (_TSS, Package (0x0F) // _TSS: Throttling Supported States
+ {
+ Package (0x05)
+ {
+ 0x00000064,
+ 0x000003E8,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000005E,
+ 0x000003AC,
+ 0x00000000,
+ 0x0000001F,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000058,
+ 0x00000370,
+ 0x00000000,
+ 0x0000001E,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000052,
+ 0x00000334,
+ 0x00000000,
+ 0x0000001D,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000004B,
+ 0x000002F8,
+ 0x00000000,
+ 0x0000001C,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000045,
+ 0x000002BC,
+ 0x00000000,
+ 0x0000001B,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000003F,
+ 0x00000280,
+ 0x00000000,
+ 0x0000001A,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000039,
+ 0x00000244,
+ 0x00000000,
+ 0x00000019,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000032,
+ 0x00000208,
+ 0x00000000,
+ 0x00000018,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000002C,
+ 0x000001CC,
+ 0x00000000,
+ 0x00000017,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000026,
+ 0x00000190,
+ 0x00000000,
+ 0x00000016,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000020,
+ 0x00000154,
+ 0x00000000,
+ 0x00000015,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000019,
+ 0x00000118,
+ 0x00000000,
+ 0x00000014,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x00000013,
+ 0x000000DC,
+ 0x00000000,
+ 0x00000013,
+ 0x00000000
+ },
+
+ Package (0x05)
+ {
+ 0x0000000D,
+ 0x000000A0,
+ 0x00000000,
+ 0x00000012,
+ 0x00000000
+ }
+ })
+ }
+
+ Scope (\_SB.PCI0.GFX0)
+ {
+ Method (_DOD, 0, NotSerialized) // _DOD: Display Output Devices
+ {
+ Return (Package (0x03)
+ {
+ 0x80010100,
+ 0x80010240,
+ 0x80010410
+ })
+ }
+
+ Device (VGA0)
+ {
+ Name (_ADR, 0x00000100) // _ADR: Address
+ Method (_DCS, 0, NotSerialized) // _DCS: Display Current Status
+ {
+ Return (^^XDCS)
+ 0x00
+ }
+
+ Method (_DGS, 0, NotSerialized) // _DGS: Display Graphics State
+ {
+ Return (^^XDGS)
+ 0x00
+ }
+
+ Method (_DSS, 0, NotSerialized) // _DSS: Device Set State
+ {
+ ^^XDSS (0x00, Arg0)
+ }
+ }
+
+ Device (TV0)
+ {
+ Name (_ADR, 0x00000240) // _ADR: Address
+ Method (_DCS, 0, NotSerialized) // _DCS: Display Current Status
+ {
+ Return (^^XDCS)
+ 0x01
+ }
+
+ Method (_DGS, 0, NotSerialized) // _DGS: Display Graphics State
+ {
+ Return (^^XDGS)
+ 0x01
+ }
+
+ Method (_DSS, 0, NotSerialized) // _DSS: Device Set State
+ {
+ ^^XDSS (0x01, Arg0)
+ }
+ }
+
+ Device (LCD0)
+ {
+ Name (_ADR, 0x00000410) // _ADR: Address
+ Method (_BCL, 0, NotSerialized) // _BCL: Brightness Control Levels
+ {
+ Return (^^XBCL)
+ }
+
+ Method (_BCM, 1, NotSerialized) // _BCM: Brightness Control Method
+ {
+ ^^XBCM (Arg0)
+ }
+
+ Method (_BQC, 0, NotSerialized) // _BQC: Brightness Query Current
+ {
+ Return (^^XBQC)
+ }
+
+ Method (_DCS, 0, NotSerialized) // _DCS: Display Current Status
+ {
+ Return (^^XDCS)
+ 0x02
+ }
+
+ Method (_DGS, 0, NotSerialized) // _DGS: Display Graphics State
+ {
+ Return (^^XDGS)
+ 0x02
+ }
+
+ Method (_DSS, 0, NotSerialized) // _DSS: Device Set State
+ {
+ ^^XDSS (0x02, Arg0)
+ }
+ }
+ }
+
+ Scope (\_SB.PCI0.SATA)
+ {
+ Device (PR00)
+ {
+ Name (_ADR, 0x0000FFFF) // _ADR: Address
+ }
+
+ Device (PR01)
+ {
+ Name (_ADR, 0x0001FFFF) // _ADR: Address
+ }
+
+ Device (PR02)
+ {
+ Name (_ADR, 0x0002FFFF) // _ADR: Address
+ }
+
+ Device (PR03)
+ {
+ Name (_ADR, 0x0003FFFF) // _ADR: Address
+ }
+
+ Device (PR04)
+ {
+ Name (_ADR, 0x0004FFFF) // _ADR: Address
+ }
+
+ Device (PR05)
+ {
+ Name (_ADR, 0x0005FFFF) // _ADR: Address
+ }
+ }
+}
+
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/tcpa.dat b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/tcpa.dat
new file mode 100644
index 0000000..161ab2b
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/tcpa.dat
Binary files differ
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/tcpa.dsl b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/tcpa.dsl
new file mode 100644
index 0000000..0300352
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/tcpa.dsl
@@ -0,0 +1,32 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML Disassembler version 20140214-64 [Mar 29 2014]
+ * Copyright (c) 2000 - 2014 Intel Corporation
+ *
+ * Disassembly of ./tcpa.dat, Sun Dec 27 13:15:45 2015
+ *
+ * ACPI Data Table [TCPA]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "TCPA" [Trusted Computing Platform Alliance table]
+[004h 0004 4] Table Length : 00000032
+[008h 0008 1] Revision : 02
+[009h 0009 1] Checksum : AB
+[00Ah 0010 6] Oem ID : "CORE "
+[010h 0016 8] Oem Table ID : "COREBOOT"
+[018h 0024 4] Oem Revision : 00000000
+[01Ch 0028 4] Asl Compiler ID : "CORE"
+[020h 0032 4] Asl Compiler Revision : 00000000
+
+[024h 0036 2] Reserved : 0000
+[026h 0038 4] Max Event Log Length : 00010000
+[02Ah 0042 8] Event Log Address : 00000000BFEA6000
+
+Raw Table Data: Length 50 (0x32)
+
+ 0000: 54 43 50 41 32 00 00 00 02 AB 43 4F 52 45 20 20 TCPA2.....CORE
+ 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 COREBOOT....CORE
+ 0020: 00 00 00 00 00 00 00 00 01 00 00 60 EA BF 00 00 ...........`....
+ 0030: 00 00 ..
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/xsdt.dat b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/xsdt.dat
new file mode 100644
index 0000000..6b2bd4f
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/xsdt.dat
Binary files differ
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/xsdt.dsl b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/xsdt.dsl
new file mode 100644
index 0000000..f49bc53
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/acpi/xsdt.dsl
@@ -0,0 +1,37 @@
+/*
+ * Intel ACPI Component Architecture
+ * AML Disassembler version 20140214-64 [Mar 29 2014]
+ * Copyright (c) 2000 - 2014 Intel Corporation
+ *
+ * Disassembly of ./xsdt.dat, Sun Dec 27 13:15:45 2015
+ *
+ * ACPI Data Table [XSDT]
+ *
+ * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
+ */
+
+[000h 0000 4] Signature : "XSDT" [Extended System Description Table]
+[004h 0004 4] Table Length : 00000054
+[008h 0008 1] Revision : 01
+[009h 0009 1] Checksum : D6
+[00Ah 0010 6] Oem ID : "CORE "
+[010h 0016 8] Oem Table ID : "COREBOOT"
+[018h 0024 4] Oem Revision : 00000000
+[01Ch 0028 4] Asl Compiler ID : "CORE"
+[020h 0032 4] Asl Compiler Revision : 00000000
+
+[024h 0036 8] ACPI Table Address 0 : 00000000BFEBB8B0
+[02Ch 0044 8] ACPI Table Address 1 : 00000000BFEBB9B0
+[034h 0052 8] ACPI Table Address 2 : 00000000BFEBE130
+[03Ch 0060 8] ACPI Table Address 3 : 00000000BFEBE170
+[044h 0068 8] ACPI Table Address 4 : 00000000BFEBE200
+[04Ch 0076 8] ACPI Table Address 5 : 00000000BFEBE2B0
+
+Raw Table Data: Length 84 (0x54)
+
+ 0000: 58 53 44 54 54 00 00 00 01 D6 43 4F 52 45 20 20 XSDTT.....CORE
+ 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 COREBOOT....CORE
+ 0020: 00 00 00 00 B0 B8 EB BF 00 00 00 00 B0 B9 EB BF ................
+ 0030: 00 00 00 00 30 E1 EB BF 00 00 00 00 70 E1 EB BF ....0.......p...
+ 0040: 00 00 00 00 00 E2 EB BF 00 00 00 00 B0 E2 EB BF ................
+ 0050: 00 00 00 00 ....
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/biosdecode.log b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/biosdecode.log
new file mode 100644
index 0000000..6ee1f1e
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/biosdecode.log
@@ -0,0 +1,19 @@
+# biosdecode 2.12
+ACPI 2.0 present.
+ OEM Identifier: CORE
+ RSD Table 32-bit Address: 0xBFEB9030
+ XSD Table 64-bit Address: 0x00000000BFEB90E0
+SMBIOS 2.7 present.
+ Structure Table Length: 323 bytes
+ Structure Table Address: 0xBFEA5020
+ Number Of Structures: 7
+ Maximum Structure Size: 104 bytes
+BIOS32 Service Directory present.
+ Revision: 0
+ Calling Interface Address: 0x000FD4D0
+PNP BIOS 1.0 present.
+ Event Notification: Not Supported
+ Real Mode 16-bit Code Address: F000:D3B8
+ Real Mode 16-bit Data Address: F000:0000
+ 16-bit Protected Mode Code Address: 0x000FD3B4
+ 16-bit Protected Mode Data Address: 0x000F0000
diff --git "a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/card0_codec\0432.log" "b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/card0_codec\0432.log"
new file mode 100644
index 0000000..7ca58a1
--- /dev/null
+++ "b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/card0_codec\0432.log"
@@ -0,0 +1,430 @@
+Codec: Realtek ALC887-VD
+Address: 2
+AFG Function Id: 0x1 (unsol 1)
+Vendor Id: 0x10ec0887
+Subsystem Id: 0x10ec0887
+Revision Id: 0x100302
+No Modem Function Group found
+Default PCM:
+ rates [0x5f0]: 32000 44100 48000 88200 96000 192000
+ bits [0xe]: 16 20 24
+ formats [0x1]: PCM
+Default Amp-In caps: N/A
+Default Amp-Out caps: N/A
+State of AFG node 0x01:
+ Power states: D0 D1 D2 D3 CLKSTOP EPSS
+ Power: setting=D0, actual=D0
+GPIO: io=2, o=0, i=0, unsolicited=1, wake=0
+ IO[0]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0
+ IO[1]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0
+Node 0x02 [Audio Output] wcaps 0x41d: Stereo Amp-Out
+ Control: name="Front Playback Volume", index=0, device=0
+ ControlAmp: chs=3, dir=Out, idx=0, ofs=0
+ Device: name="ALC887-VD Analog", type="Audio", device=0
+ Amp-Out caps: ofs=0x40, nsteps=0x40, stepsize=0x03, mute=0
+ Amp-Out vals: [0x2c 0x2c]
+ Converter: stream=8, channel=0
+ PCM:
+ rates [0x560]: 44100 48000 96000 192000
+ bits [0xe]: 16 20 24
+ formats [0x1]: PCM
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+Node 0x03 [Audio Output] wcaps 0x41d: Stereo Amp-Out
+ Control: name="Center Playback Volume", index=0, device=0
+ ControlAmp: chs=1, dir=Out, idx=0, ofs=0
+ Control: name="LFE Playback Volume", index=0, device=0
+ ControlAmp: chs=2, dir=Out, idx=0, ofs=0
+ Amp-Out caps: ofs=0x40, nsteps=0x40, stepsize=0x03, mute=0
+ Amp-Out vals: [0x2c 0x2c]
+ Converter: stream=8, channel=0
+ PCM:
+ rates [0x560]: 44100 48000 96000 192000
+ bits [0xe]: 16 20 24
+ formats [0x1]: PCM
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+Node 0x04 [Audio Output] wcaps 0x41d: Stereo Amp-Out
+ Control: name="Surround Playback Volume", index=0, device=0
+ ControlAmp: chs=3, dir=Out, idx=0, ofs=0
+ Amp-Out caps: ofs=0x40, nsteps=0x40, stepsize=0x03, mute=0
+ Amp-Out vals: [0x2c 0x2c]
+ Converter: stream=8, channel=0
+ PCM:
+ rates [0x560]: 44100 48000 96000 192000
+ bits [0xe]: 16 20 24
+ formats [0x1]: PCM
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+Node 0x05 [Audio Output] wcaps 0x41d: Stereo Amp-Out
+ Control: name="Side Playback Volume", index=0, device=0
+ ControlAmp: chs=3, dir=Out, idx=0, ofs=0
+ Amp-Out caps: ofs=0x40, nsteps=0x40, stepsize=0x03, mute=0
+ Amp-Out vals: [0x2c 0x2c]
+ Converter: stream=8, channel=0
+ PCM:
+ rates [0x560]: 44100 48000 96000 192000
+ bits [0xe]: 16 20 24
+ formats [0x1]: PCM
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+Node 0x06 [Audio Output] wcaps 0x611: Stereo Digital
+ Control: name="IEC958 Playback Con Mask", index=16, device=0
+ Control: name="IEC958 Playback Pro Mask", index=16, device=0
+ Control: name="IEC958 Playback Default", index=16, device=0
+ Control: name="IEC958 Playback Switch", index=16, device=0
+ Control: name="IEC958 Default PCM Playback Switch", index=0, device=0
+ Device: name="ALC887-VD Digital", type="SPDIF", device=1
+ Converter: stream=8, channel=0
+ Digital: Enabled
+ Digital category: 0x0
+ IEC Coding Type: 0x0
+ PCM:
+ rates [0x5f0]: 32000 44100 48000 88200 96000 192000
+ bits [0xe]: 16 20 24
+ formats [0x1]: PCM
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+Node 0x07 [Vendor Defined Widget] wcaps 0xf00000: Mono
+Node 0x08 [Audio Input] wcaps 0x10051b: Stereo Amp-In
+ Control: name="Capture Volume", index=0, device=0
+ ControlAmp: chs=3, dir=In, idx=0, ofs=0
+ Control: name="Capture Switch", index=0, device=0
+ ControlAmp: chs=3, dir=In, idx=0, ofs=0
+ Device: name="ALC887-VD Analog", type="Audio", device=0
+ Amp-In caps: ofs=0x10, nsteps=0x2e, stepsize=0x03, mute=1
+ Amp-In vals: [0x1c 0x1c]
+ Converter: stream=4, channel=0
+ SDI-Select: 0
+ PCM:
+ rates [0x560]: 44100 48000 96000 192000
+ bits [0xe]: 16 20 24
+ formats [0x1]: PCM
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+ Connection: 1
+ 0x23
+Node 0x09 [Audio Input] wcaps 0x10051b: Stereo Amp-In
+ Control: name="Capture Volume", index=1, device=0
+ ControlAmp: chs=3, dir=In, idx=0, ofs=0
+ Control: name="Capture Switch", index=1, device=0
+ ControlAmp: chs=3, dir=In, idx=0, ofs=0
+ Device: name="ALC887-VD Alt Analog", type="Audio", device=2
+ Amp-In caps: ofs=0x10, nsteps=0x2e, stepsize=0x03, mute=1
+ Amp-In vals: [0x80 0x80]
+ Converter: stream=0, channel=0
+ SDI-Select: 0
+ PCM:
+ rates [0x560]: 44100 48000 96000 192000
+ bits [0xe]: 16 20 24
+ formats [0x1]: PCM
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+ Connection: 1
+ 0x22
+Node 0x0a [Audio Input] wcaps 0x100711: Stereo Digital
+ Converter: stream=0, channel=0
+ SDI-Select: 0
+ Digital:
+ Digital category: 0x0
+ IEC Coding Type: 0x0
+ PCM:
+ rates [0x560]: 44100 48000 96000 192000
+ bits [0xe]: 16 20 24
+ formats [0x1]: PCM
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+ Connection: 1
+ 0x1f
+Node 0x0b [Audio Mixer] wcaps 0x20010b: Stereo Amp-In
+ Control: name="Rear Mic Playback Volume", index=0, device=0
+ ControlAmp: chs=3, dir=In, idx=0, ofs=0
+ Control: name="Rear Mic Playback Switch", index=0, device=0
+ ControlAmp: chs=3, dir=In, idx=0, ofs=0
+ Control: name="Front Mic Playback Volume", index=0, device=0
+ ControlAmp: chs=3, dir=In, idx=1, ofs=0
+ Control: name="Front Mic Playback Switch", index=0, device=0
+ ControlAmp: chs=3, dir=In, idx=1, ofs=0
+ Control: name="Line Playback Volume", index=0, device=0
+ ControlAmp: chs=3, dir=In, idx=2, ofs=0
+ Control: name="Line Playback Switch", index=0, device=0
+ ControlAmp: chs=3, dir=In, idx=2, ofs=0
+ Control: name="CD Playback Volume", index=0, device=0
+ ControlAmp: chs=3, dir=In, idx=4, ofs=0
+ Control: name="CD Playback Switch", index=0, device=0
+ ControlAmp: chs=3, dir=In, idx=4, ofs=0
+ Control: name="Beep Playback Volume", index=0, device=0
+ ControlAmp: chs=3, dir=In, idx=5, ofs=0
+ Control: name="Beep Playback Switch", index=0, device=0
+ ControlAmp: chs=3, dir=In, idx=5, ofs=0
+ Amp-In caps: ofs=0x17, nsteps=0x1f, stepsize=0x05, mute=1
+ Amp-In vals: [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80]
+ Connection: 10
+ 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x14 0x15 0x16 0x17
+Node 0x0c [Audio Mixer] wcaps 0x20010b: Stereo Amp-In
+ Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-In vals: [0x00 0x00] [0x00 0x00]
+ Connection: 2
+ 0x02 0x0b
+Node 0x0d [Audio Mixer] wcaps 0x20010b: Stereo Amp-In
+ Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-In vals: [0x00 0x00] [0x00 0x00]
+ Connection: 2
+ 0x03 0x0b
+Node 0x0e [Audio Mixer] wcaps 0x20010b: Stereo Amp-In
+ Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-In vals: [0x00 0x00] [0x00 0x00]
+ Connection: 2
+ 0x04 0x0b
+Node 0x0f [Audio Mixer] wcaps 0x20010b: Stereo Amp-In
+ Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-In vals: [0x00 0x00] [0x00 0x00]
+ Connection: 2
+ 0x05 0x0b
+Node 0x10 [Audio Output] wcaps 0x611: Stereo Digital
+ Converter: stream=0, channel=0
+ Digital:
+ Digital category: 0x0
+ IEC Coding Type: 0x0
+ PCM:
+ rates [0x5f0]: 32000 44100 48000 88200 96000 192000
+ bits [0xe]: 16 20 24
+ formats [0x1]: PCM
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+Node 0x11 [Pin Complex] wcaps 0x400781: Stereo Digital
+ Pincap 0x00000010: OUT
+ Pin Default 0x411110f0: [N/A] Speaker at Ext Rear
+ Conn = 1/8, Color = Black
+ DefAssociation = 0xf, Sequence = 0x0
+ Pin-ctls: 0x40: OUT
+ Unsolicited: tag=00, enabled=0
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+ Connection: 1
+ 0x10
+Node 0x12 [Pin Complex] wcaps 0x400401: Stereo
+ Pincap 0x00000020: IN
+ Pin Default 0x411111f0: [N/A] Speaker at Ext Rear
+ Conn = 1/8, Color = Black
+ DefAssociation = 0xf, Sequence = 0x0
+ Misc = NO_PRESENCE
+ Pin-ctls: 0x00:
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+Node 0x13 [Vendor Defined Widget] wcaps 0xf00000: Mono
+Node 0x14 [Pin Complex] wcaps 0x40058d: Stereo Amp-Out
+ Control: name="Front Playback Switch", index=0, device=0
+ ControlAmp: chs=3, dir=Out, idx=0, ofs=0
+ Control: name="Line Out Front Jack", index=0, device=0
+ Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-Out vals: [0x00 0x00]
+ Pincap 0x0001003e: IN OUT HP EAPD Detect Trigger
+ EAPD 0x2: EAPD
+ Pin Default 0x01014030: [Jack] Line Out at Ext Rear
+ Conn = 1/8, Color = Green
+ DefAssociation = 0x3, Sequence = 0x0
+ Pin-ctls: 0x40: OUT
+ Unsolicited: tag=05, enabled=1
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+ Connection: 1
+ 0x0c
+Node 0x15 [Pin Complex] wcaps 0x40058d: Stereo Amp-Out
+ Control: name="Center Playback Switch", index=0, device=0
+ ControlAmp: chs=1, dir=Out, idx=0, ofs=0
+ Control: name="LFE Playback Switch", index=0, device=0
+ ControlAmp: chs=2, dir=Out, idx=0, ofs=0
+ Control: name="Line Out CLFE Jack", index=0, device=0
+ Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-Out vals: [0x00 0x00]
+ Pincap 0x00000036: IN OUT Detect Trigger
+ Pin Default 0x01011031: [Jack] Line Out at Ext Rear
+ Conn = 1/8, Color = Black
+ DefAssociation = 0x3, Sequence = 0x1
+ Pin-ctls: 0x40: OUT
+ Unsolicited: tag=07, enabled=1
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+ Connection: 1
+ 0x0d
+Node 0x16 [Pin Complex] wcaps 0x40058d: Stereo Amp-Out
+ Control: name="Surround Playback Switch", index=0, device=0
+ ControlAmp: chs=3, dir=Out, idx=0, ofs=0
+ Control: name="Line Out Surround Jack", index=0, device=0
+ Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-Out vals: [0x00 0x00]
+ Pincap 0x00000036: IN OUT Detect Trigger
+ Pin Default 0x01016032: [Jack] Line Out at Ext Rear
+ Conn = 1/8, Color = Orange
+ DefAssociation = 0x3, Sequence = 0x2
+ Pin-ctls: 0x40: OUT
+ Unsolicited: tag=06, enabled=1
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+ Connection: 1
+ 0x0e
+Node 0x17 [Pin Complex] wcaps 0x40058d: Stereo Amp-Out
+ Control: name="Side Playback Switch", index=0, device=0
+ ControlAmp: chs=3, dir=Out, idx=0, ofs=0
+ Control: name="Line Out Side Jack", index=0, device=0
+ Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-Out vals: [0x00 0x00]
+ Pincap 0x00000036: IN OUT Detect Trigger
+ Pin Default 0x01012033: [Jack] Line Out at Ext Rear
+ Conn = 1/8, Color = Grey
+ DefAssociation = 0x3, Sequence = 0x3
+ Pin-ctls: 0x40: OUT
+ Unsolicited: tag=08, enabled=1
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+ Connection: 1
+ 0x0f
+Node 0x18 [Pin Complex] wcaps 0x40058f: Stereo Amp-In Amp-Out
+ Control: name="Rear Mic Boost Volume", index=0, device=0
+ ControlAmp: chs=3, dir=In, idx=0, ofs=0
+ Control: name="Rear Mic Jack", index=0, device=0
+ Amp-In caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0
+ Amp-In vals: [0x00 0x00]
+ Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-Out vals: [0x80 0x80]
+ Pincap 0x00003736: IN OUT Detect Trigger
+ Vref caps: HIZ 50 GRD 80 100
+ Pin Default 0x01a19850: [Jack] Mic at Ext Rear
+ Conn = 1/8, Color = Pink
+ DefAssociation = 0x5, Sequence = 0x0
+ Pin-ctls: 0x21: IN VREF_50
+ Unsolicited: tag=01, enabled=1
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+ Connection: 5
+ 0x0c* 0x0d 0x0e 0x0f 0x26
+Node 0x19 [Pin Complex] wcaps 0x40058f: Stereo Amp-In Amp-Out
+ Control: name="Front Mic Boost Volume", index=0, device=0
+ ControlAmp: chs=3, dir=In, idx=0, ofs=0
+ Control: name="Front Mic Jack", index=0, device=0
+ Amp-In caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0
+ Amp-In vals: [0x00 0x00]
+ Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-Out vals: [0x80 0x80]
+ Pincap 0x0000373e: IN OUT HP Detect Trigger
+ Vref caps: HIZ 50 GRD 80 100
+ Pin Default 0x02a19c80: [Jack] Mic at Ext Front
+ Conn = 1/8, Color = Pink
+ DefAssociation = 0x8, Sequence = 0x0
+ Pin-ctls: 0x24: IN VREF_80
+ Unsolicited: tag=02, enabled=1
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+ Connection: 5
+ 0x0c* 0x0d 0x0e 0x0f 0x26
+Node 0x1a [Pin Complex] wcaps 0x40058f: Stereo Amp-In Amp-Out
+ Control: name="Line Boost Volume", index=0, device=0
+ ControlAmp: chs=3, dir=In, idx=0, ofs=0
+ Control: name="Line Jack", index=0, device=0
+ Amp-In caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0
+ Amp-In vals: [0x00 0x00]
+ Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-Out vals: [0x80 0x80]
+ Pincap 0x00003736: IN OUT Detect Trigger
+ Vref caps: HIZ 50 GRD 80 100
+ Pin Default 0x01813051: [Jack] Line In at Ext Rear
+ Conn = 1/8, Color = Blue
+ DefAssociation = 0x5, Sequence = 0x1
+ Pin-ctls: 0x20: IN VREF_HIZ
+ Unsolicited: tag=03, enabled=1
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+ Connection: 5
+ 0x0c* 0x0d 0x0e 0x0f 0x26
+Node 0x1b [Pin Complex] wcaps 0x40058f: Stereo Amp-In Amp-Out
+ Control: name="Headphone Playback Switch", index=0, device=0
+ ControlAmp: chs=3, dir=Out, idx=0, ofs=0
+ Control: name="Front Headphone Phantom Jack", index=0, device=0
+ Amp-In caps: ofs=0x00, nsteps=0x03, stepsize=0x27, mute=0
+ Amp-In vals: [0x00 0x00]
+ Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-Out vals: [0x00 0x00]
+ Pincap 0x0001373e: IN OUT HP EAPD Detect Trigger
+ Vref caps: HIZ 50 GRD 80 100
+ EAPD 0x2: EAPD
+ Pin Default 0x02214c40: [Jack] HP Out at Ext Front
+ Conn = 1/8, Color = Green
+ DefAssociation = 0x4, Sequence = 0x0
+ Pin-ctls: 0xc0: OUT HP VREF_HIZ
+ Unsolicited: tag=00, enabled=0
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+ Connection: 5
+ 0x0c 0x0d 0x0e 0x0f 0x26*
+Node 0x1c [Pin Complex] wcaps 0x400481: Stereo
+ Control: name="CD Phantom Jack", index=0, device=0
+ Pincap 0x00000024: IN Detect
+ Pin Default 0x9933105f: [Fixed] CD at Int ATAPI
+ Conn = ATAPI, Color = Black
+ DefAssociation = 0x5, Sequence = 0xf
+ Pin-ctls: 0x20: IN
+ Unsolicited: tag=00, enabled=0
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+Node 0x1d [Pin Complex] wcaps 0x400400: Mono
+ Pincap 0x00000020: IN
+ Pin Default 0x00000100: [Jack] Line Out at Ext N/A
+ Conn = Unknown, Color = Unknown
+ DefAssociation = 0x0, Sequence = 0x0
+ Misc = NO_PRESENCE
+ Pin-ctls: 0x20: IN
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+Node 0x1e [Pin Complex] wcaps 0x400781: Stereo Digital
+ Control: name="SPDIF Phantom Jack", index=0, device=0
+ Pincap 0x00000010: OUT
+ Pin Default 0x01441070: [Jack] SPDIF Out at Ext Rear
+ Conn = RCA, Color = Black
+ DefAssociation = 0x7, Sequence = 0x0
+ Pin-ctls: 0x40: OUT
+ Unsolicited: tag=00, enabled=0
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+ Connection: 1
+ 0x06
+Node 0x1f [Pin Complex] wcaps 0x400681: Stereo Digital
+ Pincap 0x00000020: IN
+ Pin Default 0x41c46060: [N/A] SPDIF In at Ext Rear
+ Conn = RCA, Color = Orange
+ DefAssociation = 0x6, Sequence = 0x0
+ Pin-ctls: 0x20: IN
+ Unsolicited: tag=00, enabled=0
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+Node 0x20 [Vendor Defined Widget] wcaps 0xf00040: Mono
+ Processing caps: benign=0, ncoeff=24
+Node 0x21 [Vendor Defined Widget] wcaps 0xf00000: Mono
+Node 0x22 [Audio Mixer] wcaps 0x20010b: Stereo Amp-In
+ Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-In vals: [0x00 0x00] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80]
+ Connection: 12
+ 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x14 0x15 0x16 0x17 0x0b 0x12
+Node 0x23 [Audio Mixer] wcaps 0x20010b: Stereo Amp-In
+ Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-In vals: [0x80 0x80] [0x00 0x00] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80] [0x80 0x80]
+ Connection: 11
+ 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x14 0x15 0x16 0x17 0x0b
+Node 0x24 [Vendor Defined Widget] wcaps 0xf00000: Mono
+Node 0x25 [Audio Output] wcaps 0x41d: Stereo Amp-Out
+ Control: name="Headphone Playback Volume", index=0, device=0
+ ControlAmp: chs=3, dir=Out, idx=0, ofs=0
+ Amp-Out caps: ofs=0x40, nsteps=0x40, stepsize=0x03, mute=0
+ Amp-Out vals: [0x2c 0x2c]
+ Converter: stream=8, channel=0
+ PCM:
+ rates [0x560]: 44100 48000 96000 192000
+ bits [0xe]: 16 20 24
+ formats [0x1]: PCM
+ Power states: D0 D1 D2 D3 EPSS
+ Power: setting=D0, actual=D0
+Node 0x26 [Audio Mixer] wcaps 0x20010b: Stereo Amp-In
+ Amp-In caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-In vals: [0x00 0x00] [0x00 0x00]
+ Connection: 2
+ 0x25 0x0b
diff --git "a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/card0_codec\0433.log" "b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/card0_codec\0433.log"
new file mode 100644
index 0000000..a742b8e
--- /dev/null
+++ "b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/card0_codec\0433.log"
@@ -0,0 +1,108 @@
+Codec: Intel PantherPoint HDMI
+Address: 3
+AFG Function Id: 0x1 (unsol 0)
+Vendor Id: 0x80862806
+Subsystem Id: 0x80860101
+Revision Id: 0x100000
+No Modem Function Group found
+Default PCM:
+ rates [0x0]:
+ bits [0x0]:
+ formats [0x0]:
+Default Amp-In caps: N/A
+Default Amp-Out caps: N/A
+State of AFG node 0x01:
+ Power states: D0 D3 CLKSTOP EPSS
+ Power: setting=D0, actual=D0, Clock-stop-OK
+GPIO: io=0, o=0, i=0, unsolicited=0, wake=0
+Node 0x02 [Audio Output] wcaps 0x6611: 8-Channels Digital
+ Converter: stream=0, channel=0
+ Digital: Enabled
+ Digital category: 0x0
+ IEC Coding Type: 0x0
+ PCM:
+ rates [0x7f0]: 32000 44100 48000 88200 96000 176400 192000
+ bits [0x1e]: 16 20 24 32
+ formats [0x5]: PCM AC3
+ Power states: D0 D3 EPSS
+ Power: setting=D0, actual=D0
+Node 0x03 [Audio Output] wcaps 0x6611: 8-Channels Digital
+ Converter: stream=0, channel=0
+ Digital: Enabled
+ Digital category: 0x0
+ IEC Coding Type: 0x0
+ PCM:
+ rates [0x7f0]: 32000 44100 48000 88200 96000 176400 192000
+ bits [0x1e]: 16 20 24 32
+ formats [0x5]: PCM AC3
+ Power states: D0 D3 EPSS
+ Power: setting=D0, actual=D0
+Node 0x04 [Audio Output] wcaps 0x6611: 8-Channels Digital
+ Converter: stream=0, channel=0
+ Digital: Enabled
+ Digital category: 0x0
+ IEC Coding Type: 0x0
+ PCM:
+ rates [0x7f0]: 32000 44100 48000 88200 96000 176400 192000
+ bits [0x1e]: 16 20 24 32
+ formats [0x5]: PCM AC3
+ Power states: D0 D3 EPSS
+ Power: setting=D0, actual=D0
+Node 0x05 [Pin Complex] wcaps 0x40778d: 8-Channels Digital Amp-Out CP
+ Control: name="HDMI/DP,pcm=3 Jack", index=0, device=0
+ Control: name="IEC958 Playback Con Mask", index=0, device=0
+ Control: name="IEC958 Playback Pro Mask", index=0, device=0
+ Control: name="IEC958 Playback Default", index=0, device=0
+ Control: name="IEC958 Playback Switch", index=0, device=0
+ Control: name="ELD", index=0, device=3
+ Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-Out vals: [0x00 0x00]
+ Pincap 0x09000094: OUT Detect HBR HDMI DP
+ Pin Default 0x18560010: [Jack] Digital Out at Int HDMI
+ Conn = Digital, Color = Unknown
+ DefAssociation = 0x1, Sequence = 0x0
+ Pin-ctls: 0x40: OUT
+ Unsolicited: tag=01, enabled=1
+ Power states: D0 D3 EPSS
+ Power: setting=D0, actual=D0
+ Connection: 1
+ 0x02
+Node 0x06 [Pin Complex] wcaps 0x40778d: 8-Channels Digital Amp-Out CP
+ Control: name="HDMI/DP,pcm=7 Jack", index=0, device=0
+ Control: name="IEC958 Playback Con Mask", index=1, device=0
+ Control: name="IEC958 Playback Pro Mask", index=1, device=0
+ Control: name="IEC958 Playback Default", index=1, device=0
+ Control: name="IEC958 Playback Switch", index=1, device=0
+ Control: name="ELD", index=0, device=7
+ Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-Out vals: [0x00 0x00]
+ Pincap 0x09000094: OUT Detect HBR HDMI DP
+ Pin Default 0x18560010: [Jack] Digital Out at Int HDMI
+ Conn = Digital, Color = Unknown
+ DefAssociation = 0x1, Sequence = 0x0
+ Pin-ctls: 0x40: OUT
+ Unsolicited: tag=02, enabled=1
+ Power states: D0 D3 EPSS
+ Power: setting=D0, actual=D0
+ Connection: 1
+ 0x03
+Node 0x07 [Pin Complex] wcaps 0x40778d: 8-Channels Digital Amp-Out CP
+ Control: name="HDMI/DP,pcm=8 Jack", index=0, device=0
+ Control: name="IEC958 Playback Con Mask", index=2, device=0
+ Control: name="IEC958 Playback Pro Mask", index=2, device=0
+ Control: name="IEC958 Playback Default", index=2, device=0
+ Control: name="IEC958 Playback Switch", index=2, device=0
+ Control: name="ELD", index=0, device=8
+ Amp-Out caps: ofs=0x00, nsteps=0x00, stepsize=0x00, mute=1
+ Amp-Out vals: [0x00 0x00]
+ Pincap 0x09000094: OUT Detect HBR HDMI DP
+ Pin Default 0x18560010: [Jack] Digital Out at Int HDMI
+ Conn = Digital, Color = Unknown
+ DefAssociation = 0x1, Sequence = 0x0
+ Pin-ctls: 0x40: OUT
+ Unsolicited: tag=03, enabled=1
+ Power states: D0 D3 EPSS
+ Power: setting=D0, actual=D0
+ Connection: 1
+ 0x04
+Node 0x08 [Vendor Defined Widget] wcaps 0xf00000: Mono
diff --git a/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/cbmem-console.log b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/cbmem-console.log
new file mode 100644
index 0000000..4764b42
--- /dev/null
+++ b/gigabyte/ga-b75m-d3h/4.2-619-gd890b45/2015-12-26T19_53_49Z/tests/cbmem-console.log
@@ -0,0 +1,1780 @@
+
+
+coreboot-4.2-619-gd890b45 Sat Dec 26 19:53:49 UTC 2015 romstage starting...
+Setting up static southbridge registers... done.
+Disabling Watchdog reboot... done.
+Setting up static northbridge registers... done.
+Initializing Graphics...
+Back from sandybridge_early_initialization()
+POST: 0x38
+SMBus controller enabled.
+POST: 0x39
+POST: 0x3a
+CPU id(306a9): Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz
+AES supported, TXT supported, VT supported
+PCH type: B75, device id: 1e49, rev id 4
+Intel ME early init
+Intel ME firmware is ready
+ME: Requested 32MB UMA
+Starting native Platform init
+ Row addr bits : 16
+ Column addr bits : 10
+ Number of ranks : 1
+ DIMM Capacity : 4096 MB
+ CAS latencies : 5 6 7 8 9 10 11
+ tCKmin : 1.250 ns
+ tAAmin : 13.125 ns
+ tWRmin : 15.000 ns
+ tRCDmin : 13.125 ns
+ tRRDmin : 6.000 ns
+ tRPmin : 13.125 ns
+ tRASmin : 35.000 ns
+ tRCmin : 48.125 ns
+ tRFCmin : 260.000 ns
+ tWTRmin : 7.500 ns
+ tRTPmin : 7.500 ns
+ tFAWmin : 30.000 ns
+rankmap[0] = 0x1
+ Row addr bits : 16
+ Column addr bits : 10
+ Number of ranks : 1
+ DIMM Capacity : 4096 MB
+ CAS latencies : 5 6 7 8 9 10 11
+ tCKmin : 1.250 ns
+ tAAmin : 13.125 ns
+ tWRmin : 15.000 ns
+ tRCDmin : 13.125 ns
+ tRRDmin : 6.000 ns
+ tRPmin : 13.125 ns
+ tRASmin : 35.000 ns
+ tRCmin : 48.125 ns
+ tRFCmin : 260.000 ns
+ tWTRmin : 7.500 ns
+ tRTPmin : 7.500 ns
+ tFAWmin : 30.000 ns
+rankmap[1] = 0x1
+ PLL busy...done
+MCU frequency is set at : 800 MHz
+Selected DRAM frequency: 800 MHz
+Minimum CAS latency : 11T
+Selected CAS latency : 11T
+Selected CWL latency : 8T
+Selected tRCD : 11T
+Selected tRP : 11T
+Selected tRAS : 28T
+Selected tWR : 12T
+Selected tFAW : 24T
+Selected tRRD : 5T
+Selected tRTP : 6T
+Selected tWTR : 6T
+Selected tRFC : 208T
+[c14] = 1000000
+[320c] = 24000
+[d14] = 1000000
+[330c] = 24000
+[4000] = 1c8bbb
+[4004] = cc186465
+[400c] = a08b4
+[4298] = 6cd01860
+[42a4] = 41f88200
+[4400] = 1c8bbb
+[4404] = cc186465
+[440c] = a08b4
+[4698] = 6cd01860
+[46a4] = 41f88200
+Done dimm mapping
+PCI:[a0] = 0
+PCI:[a4] = 2
+PCI:[bc] = c2a00000
+PCI:[a8] = 3b600000
+PCI:[ac] = 2
+PCI:[b8] = c0000000
+PCI:[b0] = c0a00000
+PCI:[b4] = c0800000
+PCI:[7c] = 7f
+PCI:[70] = fe000000
+PCI:[74] = 1
+PCI:[78] = fe000c00
+Done memory map
+RCOMP...done
+COMP2 done
+COMP1 done
+FORCE RCOMP and wait 20us...done
+Done io registers
+Done jedec reset
+Done MRS commands
+High adjust 0:0000ffffffffffff
+High adjust 1:00000000ffffffff
+High adjust 2:00000000ffffffff
+High adjust 3:00000000ffffffff
+High adjust 4:00000000ffffffff
+High adjust 5:00000000ffffffff
+High adjust 6:00000000ffffffff
+High adjust 7:00000000ffffffff
+High adjust 0:0000fffffff
+
+*** Log truncated, 2653 characters dropped. ***
+
+Relocate MRC DATA from feffa79c to bffdd000 (1040 bytes)
+POST: 0x3c
+POST: 0x3d
+POST: 0x3f
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'fallback/ramstage'
+CBFS: Found @ offset 740100 size 108ab
+
+
+coreboot-4.2-619-gd890b45 Sat Dec 26 19:53:49 UTC 2015 ramstage starting...
+POST: 0x39
+Moving GDT to bfffe8a0...ok
+POST: 0x80
+Normal boot.
+POST: 0x70
+BS: BS_PRE_DEVICE times (us): entry 0 run 1054 exit 0
+POST: 0x71
+BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1054 exit 0
+POST: 0x72
+Enumerating buses...
+Show all devs... Before device enumeration.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 00: enabled 1
+APIC: acac: enabled 0
+DOMAIN: 0000: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 00:02.0: enabled 1
+PCI: 00:14.0: enabled 1
+PCI: 00:16.0: enabled 1
+PCI: 00:16.1: enabled 0
+PCI: 00:16.2: enabled 0
+PCI: 00:16.3: enabled 0
+PCI: 00:19.0: enabled 0
+PCI: 00:1a.0: enabled 1
+PCI: 00:1b.0: enabled 1
+PCI: 00:1c.0: enabled 1
+PCI: 00:1c.1: enabled 0
+PCI: 00:1c.2: enabled 0
+PCI: 00:1c.3: enabled 0
+PCI: 00:1c.4: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:1c.5: enabled 0
+PCI: 00:1c.6: enabled 0
+PCI: 00:1c.7: enabled 0
+PCI: 00:1d.0: enabled 1
+PCI: 00:1e.0: enabled 1
+PCI: 00:1f.0: enabled 1
+PNP: 002e.0: enabled 0
+PNP: 002e.1: enabled 1
+PNP: 002e.2: enabled 1
+PNP: 002e.3: enabled 1
+PNP: 002e.4: enabled 1
+PNP: 002e.5: enabled 1
+PNP: 002e.6: enabled 1
+PNP: 002e.7: enabled 0
+PNP: 002e.a: enabled 0
+PCI: 00:1f.2: enabled 1
+PCI: 00:1f.3: enabled 1
+PCI: 00:1f.4: enabled 0
+PCI: 00:1f.5: enabled 0
+Compare with tree...
+Root Device: enabled 1
+ CPU_CLUSTER: 0: enabled 1
+ APIC: 00: enabled 1
+ APIC: acac: enabled 0
+ DOMAIN: 0000: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:01.0: enabled 1
+ PCI: 00:02.0: enabled 1
+ PCI: 00:14.0: enabled 1
+ PCI: 00:16.0: enabled 1
+ PCI: 00:16.1: enabled 0
+ PCI: 00:16.2: enabled 0
+ PCI: 00:16.3: enabled 0
+ PCI: 00:19.0: enabled 0
+ PCI: 00:1a.0: enabled 1
+ PCI: 00:1b.0: enabled 1
+ PCI: 00:1c.0: enabled 1
+ PCI: 00:1c.1: enabled 0
+ PCI: 00:1c.2: enabled 0
+ PCI: 00:1c.3: enabled 0
+ PCI: 00:1c.4: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:1c.5: enabled 0
+ PCI: 00:1c.6: enabled 0
+ PCI: 00:1c.7: enabled 0
+ PCI: 00:1d.0: enabled 1
+ PCI: 00:1e.0: enabled 1
+ PCI: 00:1f.0: enabled 1
+ PNP: 002e.0: enabled 0
+ PNP: 002e.1: enabled 1
+ PNP: 002e.2: enabled 1
+ PNP: 002e.3: enabled 1
+ PNP: 002e.4: enabled 1
+ PNP: 002e.5: enabled 1
+ PNP: 002e.6: enabled 1
+ PNP: 002e.7: enabled 0
+ PNP: 002e.a: enabled 0
+ PCI: 00:1f.2: enabled 1
+ PCI: 00:1f.3: enabled 1
+ PCI: 00:1f.4: enabled 0
+ PCI: 00:1f.5: enabled 0
+Root Device scanning...
+root_dev_scan_bus for Root Device
+CPU_CLUSTER: 0 enabled
+DOMAIN: 0000 enabled
+DOMAIN: 0000 scanning...
+PCI: pci_scan_bus for bus 00
+POST: 0x24
+PCI: 00:00.0 [8086/0150] ops
+Normal boot.
+PCI: 00:00.0 [8086/0150] enabled
+Capability: type 0x0d @ 0x88
+Capability: type 0x01 @ 0x80
+Capability: type 0x05 @ 0x90
+Capability: type 0x10 @ 0xa0
+Capability: type 0x0d @ 0x88
+Capability: type 0x01 @ 0x80
+Capability: type 0x05 @ 0x90
+Capability: type 0x10 @ 0xa0
+PCI: 00:01.0 subordinate bus PCI Express
+PCI: 00:01.0 [8086/0151] enabled
+PCI: 00:02.0 [8086/0000] ops
+PCI: 00:02.0 [8086/0162] enabled
+PCI: 00:14.0 [8086/0000] ops
+PCI: 00:14.0 [8086/1e31] enabled
+PCI: 00:16.0 [8086/1e3a] ops
+PCI: 00:16.0 [8086/1e3a] enabled
+PCI: 00:16.1: Disabling device
+PCI: 00:16.1 [8086/1e3b] disabled No operations
+PCI: 00:16.2: Disabling device
+PCI: 00:16.2 [8086/1e3c] disabled No operations
+PCI: 00:16.3: Disabling device
+PCI: 00:16.3 [8086/1e3d] disabled No operations
+PCI: 00:19.0: Disabling device
+PCI: 00:1a.0 [8086/0000] ops
+PCI: 00:1a.0 [8086/1e2d] enabled
+PCI: 00:1b.0 [8086/0000] ops
+PCI: 00:1b.0 [8086/1e20] enabled
+PCI: 00:1c.0 [8086/0000] bus ops
+PCI: 00:1c.0 [8086/1e10] enabled
+PCI: 00:1c.1: Disabling device
+PCI: 00:1c.2: Disabling device
+PCI: 00:1c.3: Disabling device
+PCI: 00:1c.4 [8086/0000] bus ops
+PCI: 00:1c.4 [8086/1e18] enabled
+PCI: 00:1c.5: Disabling device
+PCI: 00:1c.6: Disabling device
+PCI: 00:1c.7: Disabling device
+PCH: RPFN 0x76543210 -> 0xfed4ba90
+PCI: 00:1d.0 [8086/0000] ops
+PCI: 00:1d.0 [8086/1e26] enabled
+Capability: type 0x0d @ 0x50
+Capability: type 0x0d @ 0x50
+PCI: 00:1e.0 [8086/244e] enabled
+PCI: 00:1f.0 [8086/0000] bus ops
+PCI: 00:1f.0 [8086/1e49] enabled
+PCI: 00:1f.2 [8086/0000] ops
+PCI: 00:1f.2 [8086/1e00] enabled
+PCI: 00:1f.3 [8086/0000] bus ops
+PCI: 00:1f.3 [8086/1e22] enabled
+PCI: 00:1f.4: Disabling device
+PCI: 00:1f.5: Disabling device
+POST: 0x25
+PCI: 00:01.0 scanning...
+do_pci_scan_bridge for PCI: 00:01.0
+PCI: pci_scan_bus for bus 01
+POST: 0x24
+POST: 0x25
+POST: 0x55
+scan_bus: scanning of bus PCI: 00:01.0 took 11259 usecs
+PCI: 00:1c.0 scanning...
+do_pci_scan_bridge for PCI: 00:1c.0
+PCI: pci_scan_bus for bus 02
+POST: 0x24
+PCI: 02:00.0 [1106/3432] enabled
+POST: 0x25
+POST: 0x55
+Capability: type 0x01 @ 0x80
+Capability: type 0x05 @ 0x90
+Capability: type 0x10 @ 0xc4
+Capability: type 0x10 @ 0x40
+Enabling Common Clock Configuration
+ASPM: Enabled None
+scan_bus: scanning of bus PCI: 00:1c.0 took 29765 usecs
+PCI: 00:1c.4 scanning...
+do_pci_scan_bridge for PCI: 00:1c.4
+PCI: pci_scan_bus for bus 03
+POST: 0x24
+PCI: 03:00.0 [10ec/8168] enabled
+POST: 0x25
+POST: 0x55
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x70
+Capability: type 0x10 @ 0x40
+Enabling Common Clock Configuration
+ASPM: Enabled L1
+scan_bus: scanning of bus PCI: 00:1c.4 took 29605 usecs
+PCI: 00:1e.0 scanning...
+do_pci_scan_bridge for PCI: 00:1e.0
+PCI: pci_scan_bus for bus 04
+POST: 0x24
+POST: 0x25
+POST: 0x55
+scan_bus: scanning of bus PCI: 00:1e.0 took 11287 usecs
+PCI: 00:1f.0 scanning...
+scan_lpc_bus for PCI: 00:1f.0
+PNP: 002e.0 disabled
+PNP: 002e.1 enabled
+PNP: 002e.2 enabled
+PNP: 002e.3 enabled
+PNP: 002e.4 enabled
+PNP: 002e.5 enabled
+PNP: 002e.6 enabled
+PNP: 002e.7 disabled
+PNP: 002e.a disabled
+scan_lpc_bus for PCI: 00:1f.0 done
+scan_bus: scanning of bus PCI: 00:1f.0 took 25006 usecs
+PCI: 00:1f.3 scanning...
+scan_smbus for PCI: 00:1f.3
+scan_smbus for PCI: 00:1f.3 done
+scan_bus: scanning of bus PCI: 00:1f.3 took 7748 usecs
+POST: 0x55
+scan_bus: scanning of bus DOMAIN: 0000 took 306736 usecs
+root_dev_scan_bus for Root Device done
+scan_bus: scanning of bus Root Device took 324480 usecs
+done
+BS: BS_DEV_ENUMERATE times (us): entry 0 run 522632 exit 0
+POST: 0x73
+found VGA at PCI: 00:02.0
+Setting up VGA for PCI: 00:02.0
+Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
+Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
+Allocating resources...
+Reading resources...
+Root Device read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
+DOMAIN: 0000 read_resources bus 0 link: 0
+Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000.
+PCI: 00:01.0 read_resources bus 1 link: 0
+PCI: 00:01.0 read_resources bus 1 link: 0 done
+PCI: 00:1c.0 read_resources bus 2 link: 0
+PCI: 00:1c.0 read_resources bus 2 link: 0 done
+PCI: 00:1c.4 read_resources bus 3 link: 0
+PCI: 00:1c.4 read_resources bus 3 link: 0 done
+PCI: 00:1e.0 read_resources bus 4 link: 0
+PCI: 00:1e.0 read_resources bus 4 link: 0 done
+PCI: 00:1f.0 read_resources bus 0 link: 0
+PCI: 00:1f.0 read_resources bus 0 link: 0 done
+DOMAIN: 0000 read_resources bus 0 link: 0 done
+Root Device read_resources bus 0 link: 0 done
+Done reading resources.
+Show resources in subtree (Root Device)...After reading.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 00
+ APIC: 00
+ APIC: acac
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
+ PCI: 00:00.0
+ PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
+ PCI: 00:01.0
+ PCI: 00:01.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:01.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 00:02.0
+ PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
+ PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
+ PCI: 00:14.0
+ PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:16.0
+ PCI: 00:16.0 resource base 0 size 10 align 12 gran 4 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:16.1
+ PCI: 00:16.2
+ PCI: 00:16.3
+ PCI: 00:19.0
+ PCI: 00:1a.0
+ PCI: 00:1a.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
+ PCI: 00:1b.0
+ PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:1c.0 child on link 0 PCI: 02:00.0
+ PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:1c.1
+ PCI: 00:1c.2
+ PCI: 00:1c.3
+ PCI: 00:1c.4 child on link 0 PCI: 03:00.0
+ PCI: 00:1c.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1c.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 03:00.0
+ PCI: 03:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
+ PCI: 03:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18
+ PCI: 03:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
+ PCI: 00:1c.5
+ PCI: 00:1c.6
+ PCI: 00:1c.7
+ PCI: 00:1d.0
+ PCI: 00:1d.0 resource base 0 size 400 align 12 gran 10 limit ffffffff flags 200 index 10
+ PCI: 00:1e.0
+ PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 00:1f.0 child on link 0 PNP: 002e.0
+ PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 002e.0
+ PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
+ PNP: 002e.1
+ PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
+ PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.2
+ PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags c0000100 index 60
+ PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.3
+ PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags c0000100 index 60
+ PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000800 index 74
+ PNP: 002e.4
+ PNP: 002e.4 resource base a30 size 8 align 3 gran 3 limit fff flags c0000100 index 60
+ PNP: 002e.4 resource base 9 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.4 resource base a20 size 8 align 3 gran 3 limit fff flags c0000100 index 62
+ PNP: 002e.5
+ PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60
+ PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62
+ PNP: 002e.6
+ PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 70
+ PNP: 002e.7
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
+ PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
+ PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.a
+ PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PCI: 00:1f.2
+ PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
+ PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
+ PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
+ PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
+ PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
+ PCI: 00:1f.2 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
+ PCI: 00:1f.3
+ PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
+ PCI: 00:1f.3 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:1f.4
+ PCI: 00:1f.5
+DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
+PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:01.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:1c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 03:00.0 10 * [0x0 - 0xff] io
+PCI: 00:1c.4 io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 00:1e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:1e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:1c.4 1c * [0x0 - 0xfff] io
+PCI: 00:02.0 20 * [0x1000 - 0x103f] io
+PCI: 00:1f.2 20 * [0x1040 - 0x105f] io
+PCI: 00:1f.2 10 * [0x1060 - 0x1067] io
+PCI: 00:1f.2 18 * [0x1068 - 0x106f] io
+PCI: 00:1f.2 14 * [0x1070 - 0x1073] io
+PCI: 00:1f.2 1c * [0x1074 - 0x1077] io
+DOMAIN: 0000 io: base: 1078 size: 1078 align: 12 gran: 0 limit: ffff done
+DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
+PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:01.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:01.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 02:00.0 10 * [0x0 - 0xfff] mem
+PCI: 00:1c.0 mem: base: 1000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1c.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 03:00.0 20 * [0x0 - 0x3fff] prefmem
+PCI: 03:00.0 18 * [0x4000 - 0x4fff] prefmem
+PCI: 00:1c.4 prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1c.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:1c.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:1e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:1e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:1e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:1e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
+PCI: 00:02.0 10 * [0x10000000 - 0x103fffff] mem
+PCI: 00:1c.0 20 * [0x10400000 - 0x104fffff] mem
+PCI: 00:1c.4 24 * [0x10500000 - 0x105fffff] prefmem
+PCI: 00:14.0 10 * [0x10600000 - 0x1060ffff] mem
+PCI: 00:1b.0 10 * [0x10610000 - 0x10613fff] mem
+PCI: 00:1f.2 24 * [0x10614000 - 0x106147ff] mem
+PCI: 00:1a.0 10 * [0x10615000 - 0x106153ff] mem
+PCI: 00:1d.0 10 * [0x10616000 - 0x106163ff] mem
+PCI: 00:1f.3 10 * [0x10617000 - 0x106170ff] mem
+PCI: 00:16.0 10 * [0x10618000 - 0x1061800f] mem
+DOMAIN: 0000 mem: base: 10618010 size: 10618010 align: 28 gran: 0 limit: ffffffff done
+avoid_fixed_resources: DOMAIN: 0000
+avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
+constrain_resources: PCI: 00:00.0 cf base f0000000 limit f3ffffff mem (fixed)
+constrain_resources: PCI: 00:1f.0 10000000 base 00000000 limit 00000fff io (fixed)
+avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 base d0000000 limit efffffff
+Setting resources...
+DOMAIN: 0000 io: base:1000 size:1078 align:12 gran:0 limit:ffff
+PCI: 00:1c.4 1c * [0x1000 - 0x1fff] io
+PCI: 00:02.0 20 * [0x2000 - 0x203f] io
+PCI: 00:1f.2 20 * [0x2040 - 0x205f] io
+PCI: 00:1f.2 10 * [0x2060 - 0x2067] io
+PCI: 00:1f.2 18 * [0x2068 - 0x206f] io
+PCI: 00:1f.2 14 * [0x2070 - 0x2073] io
+PCI: 00:1f.2 1c * [0x2074 - 0x2077] io
+DOMAIN: 0000 io: next_base: 2078 size: 1078 align: 12 gran: 0 done
+PCI: 00:01.0 io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:01.0 io: next_base: ffff size: 0 align: 12 gran: 12 done
+PCI: 00:1c.0 io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:1c.0 io: next_base: ffff size: 0 align: 12 gran: 12 done
+PCI: 00:1c.4 io: base:1000 size:1000 align:12 gran:12 limit:1fff
+PCI: 03:00.0 10 * [0x1000 - 0x10ff] io
+PCI: 00:1c.4 io: next_base: 1100 size: 1000 align: 12 gran: 12 done
+PCI: 00:1e.0 io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:1e.0 io: next_base: ffff size: 0 align: 12 gran: 12 done
+DOMAIN: 0000 mem: base:d0000000 size:10618010 align:28 gran:0 limit:efffffff
+PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem
+PCI: 00:02.0 10 * [0xe0000000 - 0xe03fffff] mem
+PCI: 00:1c.0 20 * [0xe0400000 - 0xe04fffff] mem
+PCI: 00:1c.4 24 * [0xe0500000 - 0xe05fffff] prefmem
+PCI: 00:14.0 10 * [0xe0600000 - 0xe060ffff] mem
+PCI: 00:1b.0 10 * [0xe0610000 - 0xe0613fff] mem
+PCI: 00:1f.2 24 * [0xe0614000 - 0xe06147ff] mem
+PCI: 00:1a.0 10 * [0xe0615000 - 0xe06153ff] mem
+PCI: 00:1d.0 10 * [0xe0616000 - 0xe06163ff] mem
+PCI: 00:1f.3 10 * [0xe0617000 - 0xe06170ff] mem
+PCI: 00:16.0 10 * [0xe0618000 - 0xe061800f] mem
+DOMAIN: 0000 mem: next_base: e0618010 size: 10618010 align: 28 gran: 0 done
+PCI: 00:01.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:01.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:01.0 mem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:01.0 mem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1c.0 mem: base:e0400000 size:100000 align:20 gran:20 limit:e04fffff
+PCI: 02:00.0 10 * [0xe0400000 - 0xe0400fff] mem
+PCI: 00:1c.0 mem: next_base: e0401000 size: 100000 align: 20 gran: 20 done
+PCI: 00:1c.4 prefmem: base:e0500000 size:100000 align:20 gran:20 limit:e05fffff
+PCI: 03:00.0 20 * [0xe0500000 - 0xe0503fff] prefmem
+PCI: 03:00.0 18 * [0xe0504000 - 0xe0504fff] prefmem
+PCI: 00:1c.4 prefmem: next_base: e0505000 size: 100000 align: 20 gran: 20 done
+PCI: 00:1c.4 mem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1c.4 mem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1e.0 prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1e.0 prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done
+PCI: 00:1e.0 mem: base:efffffff size:0 align:20 gran:20 limit:efffffff
+PCI: 00:1e.0 mem: next_base: efffffff size: 0 align: 20 gran: 20 done
+Root Device assign_resources, bus 0 link: 0
+TOUUD 0x23b600000 TOLUD 0xc2a00000 TOM 0x200000000
+MEBASE 0x1fe000000
+IGD decoded, subtracting 32M UMA and 2M GTT
+TSEG base 0xc0000000 size 8M
+Available memory below 4GB: 3072M
+Available memory above 4GB: 5046M
+Adding PCIe config bar base=0xf0000000 size=0x4000000
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem<mmconfig>
+PCI: 00:01.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
+PCI: 00:01.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem
+PCI: 00:01.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 mem
+PCI: 00:02.0 10 <- [0x00e0000000 - 0x00e03fffff] size 0x00400000 gran 0x16 mem64
+PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64
+PCI: 00:02.0 20 <- [0x0000002000 - 0x000000203f] size 0x00000040 gran 0x06 io
+PCI: 00:14.0 10 <- [0x00e0600000 - 0x00e060ffff] size 0x00010000 gran 0x10 mem64
+PCI: 00:16.0 10 <- [0x00e0618000 - 0x00e061800f] size 0x00000010 gran 0x04 mem64
+PCI: 00:1a.0 10 <- [0x00e0615000 - 0x00e06153ff] size 0x00000400 gran 0x0a mem
+PCI: 00:1b.0 10 <- [0x00e0610000 - 0x00e0613fff] size 0x00004000 gran 0x0e mem64
+PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
+PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem
+PCI: 00:1c.0 20 <- [0x00e0400000 - 0x00e04fffff] size 0x00100000 gran 0x14 bus 02 mem
+PCI: 00:1c.0 assign_resources, bus 2 link: 0
+PCI: 02:00.0 10 <- [0x00e0400000 - 0x00e0400fff] size 0x00001000 gran 0x0c mem
+PCI: 00:1c.0 assign_resources, bus 2 link: 0
+PCI: 00:1c.4 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 03 io
+PCI: 00:1c.4 24 <- [0x00e0500000 - 0x00e05fffff] size 0x00100000 gran 0x14 bus 03 prefmem
+PCI: 00:1c.4 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem
+PCI: 00:1c.4 assign_resources, bus 3 link: 0
+PCI: 03:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
+PCI: 03:00.0 18 <- [0x00e0504000 - 0x00e0504fff] size 0x00001000 gran 0x0c prefmem64
+PCI: 03:00.0 20 <- [0x00e0500000 - 0x00e0503fff] size 0x00004000 gran 0x0e prefmem64
+PCI: 00:1c.4 assign_resources, bus 3 link: 0
+PCI: 00:1d.0 10 <- [0x00e0616000 - 0x00e06163ff] size 0x00000400 gran 0x0a mem
+PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io
+PCI: 00:1e.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem
+PCI: 00:1e.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 mem
+PCI: 00:1f.0 assign_resources, bus 0 link: 0
+PNP: 002e.1 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io
+PNP: 002e.1 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq
+PNP: 002e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io
+PNP: 002e.2 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq
+PNP: 002e.3 60 <- [0x0000000378 - 0x000000037b] size 0x00000004 gran 0x02 io
+PNP: 002e.3 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq
+PNP: 002e.3 74 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 drq
+PNP: 002e.4 60 <- [0x0000000a30 - 0x0000000a37] size 0x00000008 gran 0x03 io
+PNP: 002e.4 70 <- [0x0000000009 - 0x0000000009] size 0x00000001 gran 0x00 irq
+PNP: 002e.4 62 <- [0x0000000a20 - 0x0000000a27] size 0x00000008 gran 0x03 io
+PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io
+PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq
+PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io
+PNP: 002e.6 70 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq
+PCI: 00:1f.0 assign_resources, bus 0 link: 0
+PCI: 00:1f.2 10 <- [0x0000002060 - 0x0000002067] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 14 <- [0x0000002070 - 0x0000002073] size 0x00000004 gran 0x02 io
+PCI: 00:1f.2 18 <- [0x0000002068 - 0x000000206f] size 0x00000008 gran 0x03 io
+PCI: 00:1f.2 1c <- [0x0000002074 - 0x0000002077] size 0x00000004 gran 0x02 io
+PCI: 00:1f.2 20 <- [0x0000002040 - 0x000000205f] size 0x00000020 gran 0x05 io
+PCI: 00:1f.2 24 <- [0x00e0614000 - 0x00e06147ff] size 0x00000800 gran 0x0b mem
+PCI: 00:1f.3 10 <- [0x00e0617000 - 0x00e06170ff] size 0x00000100 gran 0x08 mem64
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+Root Device assign_resources, bus 0 link: 0
+Done setting resources.
+Show resources in subtree (Root Device)...After assigning values.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 00
+ APIC: 00
+ APIC: acac
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 1000 size 1078 align 12 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base d0000000 size 10618010 align 28 gran 0 limit efffffff flags 40040200 index 10000100
+ DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3
+ DOMAIN: 0000 resource base 100000 size bff00000 align 0 gran 0 limit 0 flags e0004200 index 4
+ DOMAIN: 0000 resource base 100000000 size 13b600000 align 0 gran 0 limit 0 flags e0004200 index 5
+ DOMAIN: 0000 resource base c0000000 size 2a00000 align 0 gran 0 limit 0 flags f0000200 index 6
+ DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7
+ DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 8
+ DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 9
+ DOMAIN: 0000 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
+ DOMAIN: 0000 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
+ PCI: 00:00.0
+ PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf
+ PCI: 00:01.0
+ PCI: 00:01.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:01.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:01.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20
+ PCI: 00:02.0
+ PCI: 00:02.0 resource base e0000000 size 400000 align 22 gran 22 limit e03fffff flags 60000201 index 10
+ PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit dfffffff flags 60001201 index 18
+ PCI: 00:02.0 resource base 2000 size 40 align 6 gran 6 limit 203f flags 60000100 index 20
+ PCI: 00:14.0
+ PCI: 00:14.0 resource base e0600000 size 10000 align 16 gran 16 limit e060ffff flags 60000201 index 10
+ PCI: 00:16.0
+ PCI: 00:16.0 resource base e0618000 size 10 align 12 gran 4 limit e061800f flags 60000201 index 10
+ PCI: 00:16.1
+ PCI: 00:16.2
+ PCI: 00:16.3
+ PCI: 00:19.0
+ PCI: 00:1a.0
+ PCI: 00:1a.0 resource base e0615000 size 400 align 12 gran 10 limit e06153ff flags 60000200 index 10
+ PCI: 00:1b.0
+ PCI: 00:1b.0 resource base e0610000 size 4000 align 14 gran 14 limit e0613fff flags 60000201 index 10
+ PCI: 00:1c.0 child on link 0 PCI: 02:00.0
+ PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1c.0 resource base e0400000 size 100000 align 20 gran 20 limit e04fffff flags 60080202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base e0400000 size 1000 align 12 gran 12 limit e0400fff flags 60000200 index 10
+ PCI: 00:1c.1
+ PCI: 00:1c.2
+ PCI: 00:1c.3
+ PCI: 00:1c.4 child on link 0 PCI: 03:00.0
+ PCI: 00:1c.4 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c
+ PCI: 00:1c.4 resource base e0500000 size 100000 align 20 gran 20 limit e05fffff flags 60081202 index 24
+ PCI: 00:1c.4 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20
+ PCI: 03:00.0
+ PCI: 03:00.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 10
+ PCI: 03:00.0 resource base e0504000 size 1000 align 12 gran 12 limit e0504fff flags 60001201 index 18
+ PCI: 03:00.0 resource base e0500000 size 4000 align 14 gran 14 limit e0503fff flags 60001201 index 20
+ PCI: 00:1c.5
+ PCI: 00:1c.6
+ PCI: 00:1c.7
+ PCI: 00:1d.0
+ PCI: 00:1d.0 resource base e0616000 size 400 align 12 gran 10 limit e06163ff flags 60000200 index 10
+ PCI: 00:1e.0
+ PCI: 00:1e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:1e.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24
+ PCI: 00:1e.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20
+ PCI: 00:1f.0 child on link 0 PNP: 002e.0
+ PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:1f.0 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 002e.0
+ PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74
+ PNP: 002e.1
+ PNP: 002e.1 resource base 3f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
+ PNP: 002e.1 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.2
+ PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit fff flags e0000100 index 60
+ PNP: 002e.2 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.3
+ PNP: 002e.3 resource base 378 size 4 align 2 gran 2 limit fff flags e0000100 index 60
+ PNP: 002e.3 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000800 index 74
+ PNP: 002e.4
+ PNP: 002e.4 resource base a30 size 8 align 3 gran 3 limit fff flags e0000100 index 60
+ PNP: 002e.4 resource base 9 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.4 resource base a20 size 8 align 3 gran 3 limit fff flags e0000100 index 62
+ PNP: 002e.5
+ PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60
+ PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62
+ PNP: 002e.6
+ PNP: 002e.6 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 70
+ PNP: 002e.7
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60
+ PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 62
+ PNP: 002e.7 resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 64
+ PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PNP: 002e.a
+ PNP: 002e.a resource base 0 size 8 align 3 gran 3 limit fff flags 100 index 60
+ PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70
+ PCI: 00:1f.2
+ PCI: 00:1f.2 resource base 2060 size 8 align 3 gran 3 limit 2067 flags 60000100 index 10
+ PCI: 00:1f.2 resource base 2070 size 4 align 2 gran 2 limit 2073 flags 60000100 index 14
+ PCI: 00:1f.2 resource base 2068 size 8 align 3 gran 3 limit 206f flags 60000100 index 18
+ PCI: 00:1f.2 resource base 2074 size 4 align 2 gran 2 limit 2077 flags 60000100 index 1c
+ PCI: 00:1f.2 resource base 2040 size 20 align 5 gran 5 limit 205f flags 60000100 index 20
+ PCI: 00:1f.2 resource base e0614000 size 800 align 12 gran 11 limit e06147ff flags 60000200 index 24
+ PCI: 00:1f.3
+ PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20
+ PCI: 00:1f.3 resource base e0617000 size 100 align 12 gran 8 limit e06170ff flags 60000201 index 10
+ PCI: 00:1f.4
+ PCI: 00:1f.5
+Done allocating resources.
+BS: BS_DEV_RESOURCES times (us): entry 0 run 2299218 exit 0
+POST: 0x74
+Enabling resources...
+PCI: 00:00.0 subsystem <- 1458/5000
+PCI: 00:00.0 cmd <- 06
+PCI: 00:01.0 bridge ctrl <- 0003
+PCI: 00:01.0 cmd <- 00
+PCI: 00:02.0 subsystem <- 1458/d000
+PCI: 00:02.0 cmd <- 03
+PCI: 00:14.0 subsystem <- 1458/5007
+PCI: 00:14.0 cmd <- 102
+PCI: 00:16.0 subsystem <- 1458/5000
+PCI: 00:16.0 cmd <- 02
+PCI: 00:1a.0 subsystem <- 1458/5006
+PCI: 00:1a.0 cmd <- 102
+PCI: 00:1b.0 subsystem <- 1458/a002
+PCI: 00:1b.0 cmd <- 102
+PCI: 00:1c.0 bridge ctrl <- 0003
+PCI: 00:1c.0 subsystem <- 1458/5000
+PCI: 00:1c.0 cmd <- 106
+PCI: 00:1c.4 bridge ctrl <- 0003
+PCI: 00:1c.4 subsystem <- 1458/5000
+PCI: 00:1c.4 cmd <- 107
+PCI: 00:1d.0 subsystem <- 1458/5006
+PCI: 00:1d.0 cmd <- 102
+PCI: 00:1e.0 bridge ctrl <- 0003
+PCI: 00:1e.0 cmd <- 100
+pch_decode_init
+PCI: 00:1f.0 subsystem <- 1458/5001
+PCI: 00:1f.0 cmd <- 107
+PCI: 00:1f.2 subsystem <- 1458/b005
+PCI: 00:1f.2 cmd <- 03
+PCI: 00:1f.3 subsystem <- 1458/5001
+PCI: 00:1f.3 cmd <- 103
+PCI: 02:00.0 cmd <- 02
+PCI: 03:00.0 subsystem <- 1458/e000
+PCI: 03:00.0 cmd <- 103
+done.
+BS: BS_DEV_ENABLE times (us): entry 0 run 93275 exit 0
+POST: 0x75
+Initializing devices...
+Root Device init ...
+Root Device init finished in 1921 usecs
+POST: 0x75
+CPU_CLUSTER: 0 init ...
+start_eip=0x00001000, code_size=0x00000031
+Setting up SMI for CPU
+Loading module at 00038000 with entry 00038000. filesize: 0x160 memsize: 0x160
+Processing 10 relocs. Offset value of 0x00038000
+SMM Module: stub loaded at 00038000. Will call 00113e0a(001316a0)
+Installing SMM handler to 0xc0000000
+Loading module at c0010000 with entry c001010c. filesize: 0xed0 memsize: 0x4ef0
+Processing 50 relocs. Offset value of 0xc0010000
+Loading module at c0008000 with entry c0008000. filesize: 0x160 memsize: 0x160
+Processing 10 relocs. Offset value of 0xc0008000
+SMM Module: placing jmp sequence at c0007c00 rel16 0x03fd
+SMM Module: placing jmp sequence at c0007800 rel16 0x07fd
+SMM Module: placing jmp sequence at c0007400 rel16 0x0bfd
+SMM Module: placing jmp sequence at c0007000 rel16 0x0ffd
+SMM Module: placing jmp sequence at c0006c00 rel16 0x13fd
+SMM Module: placing jmp sequence at c0006800 rel16 0x17fd
+SMM Module: placing jmp sequence at c0006400 rel16 0x1bfd
+SMM Module: stub loaded at c0008000. Will call c001010c(00000000)
+Initializing southbridge SMI... ... pmbase = 0x0500
+
+SMI_STS: PM1
+PM1_STS: PRBTNOR PWRBTN TMROF
+GPE0_STS: GPIO14 GPIO11 GPIO10 GPIO9 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 TCO_SCI
+ALT_GP_SMI_STS: GPI14 GPI11 GPI10 GPI9 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0
+TCO_STS:
+ ... raise SMI#
+In relocation handler: cpu 0
+New SMBASE=0xc0000000 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Relocation complete.
+Locking SMM.
+Initializing CPU #0
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+POST: 0x60
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 700180 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x1b
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Physical address space:
+0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
+0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
+0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6
+0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 0
+0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1
+0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0
+0x0000000100000000 - 0x000000023b600000 size 0x13b600000 type 6
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+MTRR: default type WB/UC MTRR counts: 3/10.
+MTRR: WB selected as default type.
+MTRR: 0 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0
+MTRR: 1 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1
+MTRR: 2 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+Setting up local apic... apic_id: 0x00 done.
+POST: 0x9b
+Enabling VMX
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+Turbo is available but hidden
+Turbo has been enabled
+CPU: 0 has 4 cores, 2 threads per core
+CPU: 0 has core 1
+CPU1: stack_base 0012b000, stack_end 0012bff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 1.
+After apic_write.
+In relocation handler: cpu 1
+New SMBASE=0xbffffc00 IEDBASE=0xc0400000 @ 0003fc00
+Startup point 1.
+Waiting for send to finish...
++Writing SMRR. base = 0xc0000006, mask=0xff800800
+Sending STARTUP #2 to 1.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+Initializing CPU #1
+CPU: 0 has core 2
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+POST: 0x60
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 700180 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x1b
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+Setting up local apic... apic_id: 0x01 done.
+POST: 0x9b
+Enabling VMX
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #1 initialized
+CPU2: stack_base 0012a000, stack_end 0012aff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 2.
+After apic_write.
+In relocation handler: cpu 2
+Startup point 1.
+Waiting for send to finish...
++New SMBASE=0xbffff800 IEDBASE=0xc0400000 @ 0003fc00
+Sending STARTUP #2 to 2.
+After apic_write.
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 3
+Initializing CPU #2
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+POST: 0x60
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 700180 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x0
+microcode: updated to revision 0x1b date=2014-05-29
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+Setting up local apic... apic_id: 0x02 done.
+POST: 0x9b
+Enabling VMX
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #2 initialized
+CPU3: stack_base 00129000, stack_end 00129ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 3.
+After apic_write.
+In relocation handler: cpu 3
+New SMBASE=0xbffff400 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 3.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 4
+Initializing CPU #3
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+POST: 0x60
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 700180 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x1b
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+Setting up local apic... apic_id: 0x03 done.
+POST: 0x9b
+Enabling VMX
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #3 initialized
+CPU4: stack_base 00128000, stack_end 00128ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 4.
+After apic_write.
+In relocation handler: cpu 4
+Startup point 1.
+Waiting for send to finish...
++New SMBASE=0xbffff000 IEDBASE=0xc0400000 @ 0003fc00
+Sending STARTUP #2 to 4.
+After apic_write.
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 5
+Initializing CPU #4
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+POST: 0x60
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 700180 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x0
+microcode: updated to revision 0x1b date=2014-05-29
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+Setting up local apic... apic_id: 0x04 done.
+POST: 0x9b
+Enabling VMX
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #4 initialized
+CPU5: stack_base 00127000, stack_end 00127ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 5.
+After apic_write.
+In relocation handler: cpu 5
+New SMBASE=0xbfffec00 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 5.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 6
+Initializing CPU #5
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+POST: 0x60
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 700180 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x1b
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+Setting up local apic... apic_id: 0x05 done.
+POST: 0x9b
+Enabling VMX
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #5 initialized
+CPU6: stack_base 00126000, stack_end 00126ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 6.
+After apic_write.
+In relocation handler: cpu 6
+Startup point 1.
+Waiting for send to finish...
++New SMBASE=0xbfffe800 IEDBASE=0xc0400000 @ 0003fc00
+Sending STARTUP #2 to 6.
+After apic_write.
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU: 0 has core 7
+Initializing CPU #6
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+POST: 0x60
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 700180 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x0
+microcode: updated to revision 0x1b date=2014-05-29
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+Setting up local apic... apic_id: 0x06 done.
+POST: 0x9b
+Enabling VMX
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #6 initialized
+CPU7: stack_base 00125000, stack_end 00125ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 7.
+After apic_write.
+In relocation handler: cpu 7
+New SMBASE=0xbfffe400 IEDBASE=0xc0400000 @ 0003fc00
+Writing SMRR. base = 0xc0000006, mask=0xff800800
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 7.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+CPU #0 initialized
+Waiting for 1 CPUS to stop
+Initializing CPU #7
+CPU: vendor Intel device 306a9
+CPU: family 06, model 3a, stepping 09
+POST: 0x60
+Enabling cache
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'cpu_microcode_blob.bin'
+CBFS: Found @ offset 700180 size 5800
+microcode: sig=0x306a9 pf=0x2 revision=0x1b
+CPU: Intel(R) Core(TM) i7-3770 CPU @ 3.40GHz.
+MTRR: Fixed MSR 0x250 0x0606060606060606
+MTRR: Fixed MSR 0x258 0x0606060606060606
+MTRR: Fixed MSR 0x259 0x0000000000000000
+MTRR: Fixed MSR 0x268 0x0606060606060606
+MTRR: Fixed MSR 0x269 0x0606060606060606
+MTRR: Fixed MSR 0x26a 0x0606060606060606
+MTRR: Fixed MSR 0x26b 0x0606060606060606
+MTRR: Fixed MSR 0x26c 0x0606060606060606
+MTRR: Fixed MSR 0x26d 0x0606060606060606
+MTRR: Fixed MSR 0x26e 0x0606060606060606
+MTRR: Fixed MSR 0x26f 0x0606060606060606
+call enable_fixed_mtrr()
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+POST: 0x93
+Setting up local apic... apic_id: 0x07 done.
+POST: 0x9b
+Enabling VMX
+model_x06ax: energy policy set to 6
+model_x06ax: frequency set to 3400
+CPU #7 initialized
+All AP CPUs stopped (213381 loops)
+CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cacc, stack used: 1332 bytes
+CPU1: stack: 0012b000 - 0012c000, lowest used address 0012bc78, stack used: 904 bytes
+CPU2: stack: 0012a000 - 0012b000, lowest used address 0012ac78, stack used: 904 bytes
+CPU3: stack: 00129000 - 0012a000, lowest used address 00129c78, stack used: 904 bytes
+CPU4: stack: 00128000 - 00129000, lowest used address 00128c78, stack used: 904 bytes
+CPU5: stack: 00127000 - 00128000, lowest used address 00127c78, stack used: 904 bytes
+CPU6: stack: 00126000 - 00127000, lowest used address 00126c78, stack used: 904 bytes
+CPU7: stack: 00125000 - 00126000, lowest used address 00125c78, stack used: 904 bytes
+CPU_CLUSTER: 0 init finished in 24301122 usecs
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+PCI: 00:00.0 init ...
+Disabling PEG12.
+Disabling PEG11.
+Disabling PEG60.
+Set BIOS_RESET_CPL
+CPU TDP: 77 Watts
+PCI: 00:00.0 init finished in 11130 usecs
+POST: 0x75
+POST: 0x75
+PCI: 00:02.0 init ...
+GT Power Management Init
+IVB GT2 35W Power Meter Weights
+GT Power Management Init (post VBIOS)
+PCI: 00:02.0 init finished in 10919 usecs
+POST: 0x75
+PCI: 00:14.0 init ...
+XHCI: Setting up controller.. done.
+PCI: 00:14.0 init finished in 5241 usecs
+POST: 0x75
+PCI: 00:16.0 init ...
+ME: FW Partition Table : OK
+ME: Bringup Loader Failure : NO
+ME: Firmware Init Complete : YES
+ME: Manufacturing Mode : YES
+ME: Boot Options Present : NO
+ME: Update In Progress : NO
+ME: Current Working State : Normal
+ME: Current Operation State : M0 with UMA
+ME: Current Operation Mode : Normal
+ME: Error Code : No Error
+ME: Progress Phase : Host Communication
+ME: Power Management Event : Moff->Mx wake after an error
+ME: Progress Phase State : Host communication established
+ME: BIOS path: Normal
+ME: Extend SHA-256: f0b1b87824433f0a421ddc0cf152d1cd3d2b5e3ce7a373b3333a70ce98dd821d
+ME: MBP item header 00020103
+ME: MBP item header 00050102
+ME: MBP item header 00020501
+ME: MBP item header 00020201
+ME: MBP item header 02030101
+ME: MBP item header 02060301
+ME: MBP item header 02090401
+ME: mbp read OK after 1 cycles
+ME: found version 8.1.30.1350
+ME Capability: Full Network manageability : disabled
+ME Capability: Regular Network manageability : disabled
+ME Capability: Manageability : enabled
+ME Capability: Small business technology : enabled
+ME Capability: Level III manageability : disabled
+ME Capability: IntelR Anti-Theft (AT) : enabled
+ME Capability: IntelR Capability Licensing Service (CLS) : enabled
+ME Capability: IntelR Power Sharing Technology (MPC) : enabled
+ME Capability: ICC Over Clocking : enabled
+ME Capability: Protected Audio Video Path (PAVP) : enabled
+ME Capability: IPV6 : disabled
+ME Capability: KVM Remote Control (KVM) : disabled
+ME Capability: Outbreak Containment Heuristic (OCH) : disabled
+ME Capability: Virtual LAN (VLAN) : enabled
+ME Capability: TLS : enabled
+ME Capability: Wireless LAN (WLAN) : disabled
+PCI: 00:16.0 init finished in 177781 usecs
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+PCI: 00:1a.0 init ...
+EHCI: Setting up controller.. done.
+PCI: 00:1a.0 init finished in 5248 usecs
+POST: 0x75
+PCI: 00:1b.0 init ...
+Azalia: base = e0610000
+Azalia: codec_mask = 0c
+Azalia: Initializing codec #3
+Azalia: codec viddid: 80862806
+Azalia: No verb!
+Azalia: Initializing codec #2
+Azalia: codec viddid: 10ec0887
+Azalia: No verb!
+PCI: 00:1b.0 init finished in 22535 usecs
+POST: 0x75
+PCI: 00:1c.0 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.0 init finished in 4710 usecs
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+PCI: 00:1c.4 init ...
+Initializing PCH PCIe bridge.
+PCI: 00:1c.4 init finished in 4710 usecs
+POST: 0x75
+POST: 0x75
+POST: 0x75
+POST: 0x75
+PCI: 00:1d.0 init ...
+EHCI: Setting up controller.. done.
+PCI: 00:1d.0 init finished in 5248 usecs
+POST: 0x75
+POST: 0x75
+PCI: 00:1f.0 init ...
+pch: lpc_init
+IOAPIC: Initializing IOAPIC at 0xfec00000
+IOAPIC: Bootstrap Processor Local APIC = 0x00
+IOAPIC: ID = 0x02
+IOAPIC: Dumping registers
+ reg 0x0000: 0x02000000
+ reg 0x0001: 0x00170020
+ reg 0x0002: 0x00170020
+Set power off after power failure.
+NMI sources disabled.
+PantherPoint PM init
+rtc_failed = 0x0
+RTC Init
+Enabling BIOS updates outside of SMM... Disabling ACPI via APMC:
+done.
+pch_spi_init
+PCI: 00:1f.0 init finished in 39221 usecs
+POST: 0x75
+PCI: 00:1f.2 init ...
+SATA: Initializing...
+SATA: Controller in AHCI mode.
+ABAR: e0614000
+PCI: 00:1f.2 init finished in 8264 usecs
+POST: 0x75
+PCI: 00:1f.3 init ...
+PCI: 00:1f.3 init finished in 2012 usecs
+POST: 0x75
+POST: 0x75
+POST: 0x75
+PCI: 02:00.0 init ...
+PCI: 02:00.0 init finished in 2007 usecs
+POST: 0x75
+PCI: 03:00.0 init ...
+PCI: 03:00.0 init finished in 2005 usecs
+POST: 0x75
+POST: 0x75
+PNP: 002e.1 init ...
+PNP: 002e.1 init finished in 1919 usecs
+POST: 0x75
+PNP: 002e.2 init ...
+PNP: 002e.2 init finished in 1919 usecs
+POST: 0x75
+PNP: 002e.3 init ...
+PNP: 002e.3 init finished in 1919 usecs
+POST: 0x75
+PNP: 002e.4 init ...
+ITE IT8728F Super I/O HWM: Initializing Hardware Monitor..
+ITE IT8728F Super I/O HWM: Base Address at 0xa35
+PNP: 002e.4 init finished in 11494 usecs
+POST: 0x75
+PNP: 002e.5 init ...
+PNP: 002e.5 init finished in 1947 usecs
+POST: 0x75
+PNP: 002e.6 init ...
+PNP: 002e.6 init finished in 1918 usecs
+POST: 0x75
+POST: 0x75
+Devices initialized
+Show all devs... After init.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 00: enabled 1
+APIC: acac: enabled 0
+DOMAIN: 0000: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 00:02.0: enabled 1
+PCI: 00:14.0: enabled 1
+PCI: 00:16.0: enabled 1
+PCI: 00:16.1: enabled 0
+PCI: 00:16.2: enabled 0
+PCI: 00:16.3: enabled 0
+PCI: 00:19.0: enabled 0
+PCI: 00:1a.0: enabled 1
+PCI: 00:1b.0: enabled 1
+PCI: 00:1c.0: enabled 1
+PCI: 00:1c.1: enabled 0
+PCI: 00:1c.2: enabled 0
+PCI: 00:1c.3: enabled 0
+PCI: 00:1c.4: enabled 1
+PCI: 03:00.0: enabled 1
+PCI: 00:1c.5: enabled 0
+PCI: 00:1c.6: enabled 0
+PCI: 00:1c.7: enabled 0
+PCI: 00:1d.0: enabled 1
+PCI: 00:1e.0: enabled 1
+PCI: 00:1f.0: enabled 1
+PNP: 002e.0: enabled 0
+PNP: 002e.1: enabled 1
+PNP: 002e.2: enabled 1
+PNP: 002e.3: enabled 1
+PNP: 002e.4: enabled 1
+PNP: 002e.5: enabled 1
+PNP: 002e.6: enabled 1
+PNP: 002e.7: enabled 0
+PNP: 002e.a: enabled 0
+PCI: 00:1f.2: enabled 1
+PCI: 00:1f.3: enabled 1
+PCI: 00:1f.4: enabled 0
+PCI: 00:1f.5: enabled 0
+PCI: 02:00.0: enabled 1
+APIC: 01: enabled 1
+APIC: 02: enabled 1
+APIC: 03: enabled 1
+APIC: 04: enabled 1
+APIC: 05: enabled 1
+APIC: 06: enabled 1
+APIC: 07: enabled 1
+BS: BS_DEV_INIT times (us): entry 5 run 24867283 exit 0
+POST: 0x76
+Finalize devices...
+PCI: 00:1f.0 final
+Devices finalized
+BS: BS_POST_DEVICE times (us): entry 0 run 6295 exit 0
+POST: 0x77
+BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1054 exit 0
+Updating MRC cache data.
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'mrc.cache'
+CBFS: Found @ offset 7300c0 size 10000
+find_current_mrc_cache_local: picked entry 4 from cache block
+SF: Detected W25Q64 with sector size 0x1000, total 0x800000
+find_next_mrc_cache: picked next entry from cache block at fff35100
+Finally: write MRC cache update to flash at fff35100
+POST: 0x79
+POST: 0x9c
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'fallback/dsdt.aml'
+CBFS: Found @ offset 706580 size 261c
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'fallback/slic'
+CBFS: 'fallback/slic' not found.
+ACPI: Writing ACPI tables at bfeb9000.
+ACPI: * FACS
+ACPI: * DSDT
+ACPI: * IGD OpRegion
+GET_VBIOS: 87b4 1a1b 29 fe b0
+VBIOS not found.
+ACPI: * FADT
+ACPI: added table 1/32, length now 40
+ACPI: * SSDT
+Found 1 CPU(s) with 8 core(s) each.
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+PSS: 3401MHz power 77000 control 0x2700 status 0x2700
+PSS: 3400MHz power 77000 control 0x2200 status 0x2200
+PSS: 2800MHz power 59061 control 0x1c00 status 0x1c00
+PSS: 2400MHz power 48259 control 0x1800 status 0x1800
+PSS: 2000MHz power 38348 control 0x1400 status 0x1400
+PSS: 1600MHz power 29132 control 0x1000 status 0x1000
+ACPI: added table 2/32, length now 44
+ACPI: * MCFG
+ACPI: * TCPA
+TCPA log created at bfea6000
+ACPI: added table 3/32, length now 48
+ACPI: * MADT
+ACPI: added table 4/32, length now 52
+current = bfebe200
+ACPI: * DMAR
+ACPI: added table 5/32, length now 56
+current = bfebe2b0
+ACPI: * HPET
+ACPI: added table 6/32, length now 60
+ACPI: done.
+ACPI tables: 21232 bytes.
+smbios_write_tables: bfea5000
+Root Device (GIGABYTE GA-B75M-D3H)
+CPU_CLUSTER: 0 (Intel SandyBridge/IvyBridge integrated Northbridge)
+APIC: 00 (unknown)
+APIC: acac (Intel SandyBridge/IvyBridge CPU)
+DOMAIN: 0000 (Intel SandyBridge/IvyBridge integrated Northbridge)
+PCI: 00:00.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
+PCI: 00:01.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
+PCI: 00:02.0 (Intel SandyBridge/IvyBridge integrated Northbridge)
+PCI: 00:14.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:16.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:16.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:16.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:16.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:19.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1a.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1b.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.1 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 03:00.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.6 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1c.7 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1d.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1e.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1f.0 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PNP: 002e.0 (ITE IT8728F Super I/O)
+PNP: 002e.1 (ITE IT8728F Super I/O)
+PNP: 002e.2 (ITE IT8728F Super I/O)
+PNP: 002e.3 (ITE IT8728F Super I/O)
+PNP: 002e.4 (ITE IT8728F Super I/O)
+PNP: 002e.5 (ITE IT8728F Super I/O)
+PNP: 002e.6 (ITE IT8728F Super I/O)
+PNP: 002e.7 (ITE IT8728F Super I/O)
+PNP: 002e.a (ITE IT8728F Super I/O)
+PCI: 00:1f.2 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1f.3 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1f.4 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 00:1f.5 (Intel Series 6/7 (Cougar Point/Panther Point) Southbridge)
+PCI: 02:00.0 (unknown)
+APIC: 01 (unknown)
+APIC: 02 (unknown)
+APIC: 03 (unknown)
+APIC: 04 (unknown)
+APIC: 05 (unknown)
+APIC: 06 (unknown)
+APIC: 07 (unknown)
+SMBIOS tables: 355 bytes.
+POST: 0x9e
+POST: 0x9d
+Writing table forward entry at 0x00000500
+Wrote coreboot table at: 00000500, 0x10 bytes, checksum 6ff4
+Table forward entry ends at 0x00000528.
+... aligned to 0x00001000
+Writing coreboot table at 0xbfe9d000
+rom_table_end = 0xbfe9d000
+... aligned to 0xbfea0000
+ 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
+ 1. 0000000000001000-000000000009ffff: RAM
+ 2. 00000000000a0000-00000000000fffff: RESERVED
+ 3. 0000000000100000-00000000bfe9cfff: RAM
+ 4. 00000000bfe9d000-00000000bfffffff: CONFIGURATION TABLES
+ 5. 00000000c0000000-00000000c29fffff: RESERVED
+ 6. 00000000f0000000-00000000f3ffffff: RESERVED
+ 7. 00000000fed90000-00000000fed91fff: RESERVED
+ 8. 0000000100000000-000000023b5fffff: RAM
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+No FMAP found at 0 offset.
+Wrote coreboot table at: bfe9d000, 0x2f0 bytes, checksum 925f
+coreboot table: 776 bytes.
+IMD ROOT 0. bffff000 00001000
+IMD SMALL 1. bfffe000 00001000
+CONSOLE 2. bffde000 00020000
+MRC DATA 3. bffdd000 00000420
+ACPI RESUME 4. bfedd000 00100000
+ACPI 5. bfeb9000 00024000
+ACPI GNVS 6. bfeb8000 00001000
+4f444749 7. bfeb6000 00002000
+TCPA LOG 8. bfea6000 00010000
+SMBIOS 9. bfea5000 00000800
+COREBOOT 10. bfe9d000 00008000
+IMD small region:
+ IMD ROOT 0. bfffec00 00000400
+ CAR GLOBALS 1. bfffeac0 00000140
+ ROMSTAGE 2. bfffeaa0 00000004
+ GDT 3. bfffe8a0 00000200
+BS: BS_WRITE_TABLES times (us): entry 2093317 run 4791474 exit 0
+POST: 0x7a
+CBFS: 'Master Header Locator' located CBFS at [0:7fffc0)
+CBFS: Locating 'fallback/payload'
+CBFS: Found @ offset 721180 size ed70
+Loading segment from rom address 0xfff211b8
+ code (compression=1)
+ New segment dstaddr 0xe44a4 memsize 0x1bb5c srcaddr 0xfff211f0 filesize 0xed38
+Loading segment from rom address 0xfff211d4
+ Entry Point 0x000ff06e
+Payload being loaded below 1MiB without region being marked as RAM usable.
+Bounce Buffer at bfe32000, 437792 bytes
+Loading Segment: addr: 0x00000000000e44a4 memsz: 0x000000000001bb5c filesz: 0x000000000000ed38
+lb: [0x0000000000100000, 0x0000000000135710)
+Post relocation: addr: 0x00000000000e44a4 memsz: 0x000000000001bb5c filesz: 0x000000000000ed38
+using LZMA
+[ 0x000e44a4, 00100000, 0x00100000) <- fff211f0
+dest 000e44a4, end 00100000, bouncebuffer bfe32000
+Loaded segments
+BS: BS_PAYLOAD_LOAD times (us): entry 0 run 2147231 exit 0
+POST: 0x7b
+PCH watchdog disabled
+Jumping to boot code at 000ff06e(bfe9d000)
+POST: 0xf8
+CPU0: stack: 0012c000 - 0012d000, lowest used address 0012cacc, stack used: 1332 bytes
+entry = 0x000ff06e
+lb_start = 0x00100000
+lb_size = 0x00035710
+buffer = 0xbfe32000
+SeaBIOS (ver