hp/pavilion_m6_1035dx/4.0-7494-g4568f19-dirty/2014-12-06T10:30:54Z
diff --git a/hp/pavilion_m6_1035dx/4.0-7494-g4568f19-dirty/2014-12-06T10:30:54Z/coreboot_console.txt b/hp/pavilion_m6_1035dx/4.0-7494-g4568f19-dirty/2014-12-06T10:30:54Z/coreboot_console.txt
new file mode 100644
index 0000000..f54f4e3
--- /dev/null
+++ b/hp/pavilion_m6_1035dx/4.0-7494-g4568f19-dirty/2014-12-06T10:30:54Z/coreboot_console.txt
@@ -0,0 +1,1578 @@
+coreboot-4.0-7494-g4568f19-nuclearis Sat Dec 6 04:03:30 CST 2014 booting...
+BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
+BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 7 exit 0
+Enumerating buses...
+Show all devs...Before device enumeration.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 10: enabled 1
+DOMAIN: 0000: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 00:01.1: enabled 1
+PCI: 00:03.0: enabled 0
+PCI: 00:04.0: enabled 1
+PCI: 00:05.0: enabled 1
+PCI: 00:08.0: enabled 0
+PCI: 00:10.0: enabled 1
+PCI: 00:11.0: enabled 1
+PCI: 00:12.0: enabled 1
+PCI: 00:12.2: enabled 1
+PCI: 00:13.0: enabled 1
+PCI: 00:13.2: enabled 1
+PCI: 00:14.0: enabled 1
+I2C: 00:50: enabled 1
+I2C: 00:51: enabled 1
+PCI: 00:14.2: enabled 1
+PCI: 00:14.3: enabled 1
+PNP: 00ff.1: enabled 1
+PCI: 00:14.4: enabled 1
+PCI: 00:14.5: enabled 1
+PCI: 00:14.6: enabled 0
+PCI: 00:14.7: enabled 1
+PCI: 00:15.0: enabled 0
+PCI: 00:15.1: enabled 0
+PCI: 00:15.2: enabled 0
+PCI: 00:15.3: enabled 0
+PCI: 00:18.0: enabled 1
+PCI: 00:18.1: enabled 1
+PCI: 00:18.2: enabled 1
+PCI: 00:18.3: enabled 1
+PCI: 00:18.4: enabled 1
+PCI: 00:18.5: enabled 1
+Compare with tree...
+Root Device: enabled 1
+ CPU_CLUSTER: 0: enabled 1
+ APIC: 10: enabled 1
+ DOMAIN: 0000: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:01.0: enabled 1
+ PCI: 00:01.1: enabled 1
+ PCI: 00:03.0: enabled 0
+ PCI: 00:04.0: enabled 1
+ PCI: 00:05.0: enabled 1
+ PCI: 00:08.0: enabled 0
+ PCI: 00:10.0: enabled 1
+ PCI: 00:11.0: enabled 1
+ PCI: 00:12.0: enabled 1
+ PCI: 00:12.2: enabled 1
+ PCI: 00:13.0: enabled 1
+ PCI: 00:13.2: enabled 1
+ PCI: 00:14.0: enabled 1
+ I2C: 00:50: enabled 1
+ I2C: 00:51: enabled 1
+ PCI: 00:14.2: enabled 1
+ PCI: 00:14.3: enabled 1
+ PNP: 00ff.1: enabled 1
+ PCI: 00:14.4: enabled 1
+ PCI: 00:14.5: enabled 1
+ PCI: 00:14.6: enabled 0
+ PCI: 00:14.7: enabled 1
+ PCI: 00:15.0: enabled 0
+ PCI: 00:15.1: enabled 0
+ PCI: 00:15.2: enabled 0
+ PCI: 00:15.3: enabled 0
+ PCI: 00:18.0: enabled 1
+ PCI: 00:18.1: enabled 1
+ PCI: 00:18.2: enabled 1
+ PCI: 00:18.3: enabled 1
+ PCI: 00:18.4: enabled 1
+ PCI: 00:18.5: enabled 1
+Mainboard Pavilion m6 1035dx Enable.
+scan_static_bus for Root Device
+setup_bsp_ramtop, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000
+setup_bsp_ramtop, TOP MEM2: msr.lo = 0x00000000, msr.hi = 0x00000000
+setup_uma_memory: uma size 0x20000000, memory start 0x5f000000
+CPU_CLUSTER: 0 enabled
+DOMAIN: 0000 enabled
+CPU_CLUSTER: 0 scanning...
+PCI: 00:18.5 family15h, core_max=0x10, core_nums=0xf, siblings=0x3
+lpaicid_start=0x10 node 0x0 core 0x0 apicid=0x10
+CPU: APIC: 10 enabled
+lpaicid_start=0x10 node 0x0 core 0x1 apicid=0x11
+CPU: APIC: 11 enabled
+lpaicid_start=0x10 node 0x0 core 0x2 apicid=0x12
+CPU: APIC: 12 enabled
+lpaicid_start=0x10 node 0x0 core 0x3 apicid=0x13
+CPU: APIC: 13 enabled
+DOMAIN: 0000 scanning...
+PCI: pci_scan_bus for bus 00
+PCI: 00:00.0 [1022/1410] enabled
+PCI: 00:01.0 [1002/9900] enabled
+PCI: 00:01.1 [1002/9902] enabled
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Capability: type 0x05 @ 0xa0
+Capability: type 0x0d @ 0xb0
+Capability: type 0x08 @ 0xb8
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+PCI: 00:04.0 subordinate bus PCI Express
+PCI: 00:04.0 [1022/1414] enabled
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Capability: type 0x05 @ 0xa0
+Capability: type 0x0d @ 0xb0
+Capability: type 0x08 @ 0xb8
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+PCI: 00:05.0 subordinate bus PCI Express
+PCI: 00:05.0 [1022/1415] enabled
+hudson_enable()
+PCI: 00:10.0 [1022/7812] enabled
+hudson_enable()
+PCI: 00:11.0 [1022/7801] ops
+PCI: 00:11.0 [1022/7801] enabled
+hudson_enable()
+PCI: 00:12.0 [1022/7807] ops
+PCI: 00:12.0 [1022/7807] enabled
+hudson_enable()
+PCI: 00:12.2 [1022/7808] ops
+PCI: 00:12.2 [1022/7808] enabled
+hudson_enable()
+PCI: 00:13.0 [1022/7807] ops
+PCI: 00:13.0 [1022/7807] enabled
+hudson_enable()
+PCI: 00:13.2 [1022/7808] ops
+PCI: 00:13.2 [1022/7808] enabled
+hudson_enable()
+PCI: 00:14.0 [1022/780b] bus ops
+PCI: 00:14.0 [1022/780b] enabled
+hudson_enable()
+PCI: 00:14.2 [1022/780d] ops
+PCI: 00:14.2 [1022/780d] enabled
+hudson_enable()
+PCI: 00:14.3 [1022/780e] bus ops
+PCI: 00:14.3 [1022/780e] enabled
+hudson_enable()
+PCI: 00:14.4 [1022/780f] bus ops
+PCI: 00:14.4 [1022/780f] enabled
+hudson_enable()
+PCI: 00:14.5 [1022/7809] ops
+PCI: 00:14.5 [1022/7809] enabled
+hudson_enable()
+hudson_enable()
+PCI: 00:14.7 [1022/7806] enabled
+hudson_enable()
+hudson_enable()
+hudson_enable()
+hudson_enable()
+PCI: 00:18.0 [1022/1400] ops
+PCI: 00:18.0 [1022/1400] enabled
+PCI: 00:18.1 [1022/1401] enabled
+PCI: 00:18.2 [1022/1402] enabled
+PCI: 00:18.3 [1022/1403] enabled
+PCI: 00:18.4 [1022/1404] enabled
+PCI: 00:18.5 [1022/1405] enabled
+do_pci_scan_bridge for PCI: 00:04.0
+PCI: pci_scan_bus for bus 01
+PCI: 01:00.0 [10ec/5289] enabled
+PCI: 01:00.2 [10ec/8168] enabled
+PCI: pci_scan_bus returning with max=001
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x70
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Enabling Common Clock Configuration
+ASPM: Enabled L1
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x70
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Enabling Common Clock Configuration
+ASPM: Enabled L1
+do_pci_scan_bridge returns max 1
+do_pci_scan_bridge for PCI: 00:05.0
+PCI: pci_scan_bus for bus 02
+PCI: 02:00.0 [168c/0032] enabled
+PCI: pci_scan_bus returning with max=002
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x70
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Enabling Common Clock Configuration
+ASPM: Enabled L0s and L1
+do_pci_scan_bridge returns max 2
+scan_static_bus for PCI: 00:14.0
+smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled
+smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled
+scan_static_bus for PCI: 00:14.0 done
+scan_static_bus for PCI: 00:14.3
+PNP: 00ff.1 enabled
+PNP: 00ff.0 enabled
+scan_static_bus for PCI: 00:14.3 done
+do_pci_scan_bridge for PCI: 00:14.4
+PCI: pci_scan_bus for bus 03
+PCI: pci_scan_bus returning with max=003
+do_pci_scan_bridge returns max 3
+PCI: pci_scan_bus returning with max=003
+scan_static_bus for Root Device done
+done
+BS: BS_DEV_ENUMERATE times (us): entry 0 run 6782 exit 0
+found VGA at PCI: 00:01.0
+Setting up VGA for PCI: 00:01.0
+Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
+Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
+Allocating resources...
+Reading resources...
+Root Device read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0
+APIC: 10 missing read_resources
+APIC: 11 missing read_resources
+APIC: 12 missing read_resources
+APIC: 13 missing read_resources
+CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
+fx_devs=0x1
+DOMAIN: 0000 read_resources bus 0 link: 0
+PCI: 00:04.0 read_resources bus 1 link: 0
+PCI: 00:04.0 read_resources bus 1 link: 0 done
+PCI: 00:05.0 read_resources bus 2 link: 0
+PCI: 00:05.0 read_resources bus 2 link: 0 done
+PCI: 00:14.0 read_resources bus 1 link: 0
+I2C: 01:50 missing read_resources
+I2C: 01:51 missing read_resources
+PCI: 00:14.0 read_resources bus 1 link: 0 done
+PCI: 00:14.3 read_resources bus 0 link: 0
+PNP: 00ff.1 missing read_resources
+PCI: 00:14.3 read_resources bus 0 link: 0 done
+PCI: 00:14.4 read_resources bus 3 link: 0
+PCI: 00:14.4 read_resources bus 3 link: 0 done
+PCI: 00:18.0 read_resources bus 0 link: 0
+PCI: 00:18.0 read_resources bus 0 link: 0 done
+PCI: 00:18.0 read_resources bus 0 link: 1
+PCI: 00:18.0 read_resources bus 0 link: 1 done
+PCI: 00:18.0 read_resources bus 0 link: 2
+PCI: 00:18.0 read_resources bus 0 link: 2 done
+PCI: 00:18.0 read_resources bus 0 link: 3
+PCI: 00:18.0 read_resources bus 0 link: 3 done
+DOMAIN: 0000 read_resources bus 0 link: 0 done
+Root Device read_resources bus 0 link: 0 done
+Done reading resources.
+Show resources in subtree (Root Device)...After reading.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 10
+ APIC: 10
+ APIC: 11
+ APIC: 12
+ APIC: 13
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
+ PCI: 00:00.0
+ PCI: 00:01.0
+ PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10
+ PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
+ PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 18
+ PCI: 00:01.1
+ PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
+ PCI: 00:03.0
+ PCI: 00:04.0 child on link 0 PCI: 01:00.0
+ PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
+ PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 01:00.0
+ PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 10
+ PCI: 01:00.2
+ PCI: 01:00.2 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
+ PCI: 01:00.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18
+ PCI: 01:00.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
+ PCI: 00:05.0 child on link 0 PCI: 02:00.0
+ PCI: 00:05.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
+ PCI: 00:05.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:05.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffffffffffff flags 201 index 10
+ PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
+ PCI: 00:08.0
+ PCI: 00:10.0
+ PCI: 00:10.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:11.0
+ PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
+ PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
+ PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
+ PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
+ PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
+ PCI: 00:11.0 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
+ PCI: 00:12.0
+ PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:12.2
+ PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
+ PCI: 00:13.0
+ PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:13.2
+ PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
+ PCI: 00:14.0 child on link 0 I2C: 01:50
+ I2C: 01:50
+ I2C: 01:51
+ PCI: 00:14.2
+ PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:14.3 child on link 0 PNP: 00ff.1
+ PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2
+ PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 00ff.1
+ PNP: 00ff.0
+ PCI: 00:14.4
+ PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
+ PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 00:14.5
+ PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:14.6
+ PCI: 00:14.7
+ PCI: 00:14.7 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:15.0
+ PCI: 00:15.1
+ PCI: 00:15.2
+ PCI: 00:15.3
+ PCI: 00:18.0
+ PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
+ PCI: 00:18.1
+ PCI: 00:18.2
+ PCI: 00:18.3
+ PCI: 00:18.4
+ PCI: 00:18.5
+DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
+PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
+PCI: 01:00.2 10 * [0x0 - 0xff] io
+PCI: 00:04.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 00:05.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
+PCI: 00:05.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
+PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:04.0 1c * [0x0 - 0xfff] io
+PCI: 00:01.0 14 * [0x1000 - 0x10ff] io
+PCI: 00:11.0 20 * [0x1400 - 0x140f] io
+PCI: 00:11.0 10 * [0x1410 - 0x1417] io
+PCI: 00:11.0 18 * [0x1418 - 0x141f] io
+PCI: 00:11.0 14 * [0x1420 - 0x1423] io
+PCI: 00:11.0 1c * [0x1424 - 0x1427] io
+DOMAIN: 0000 compute_resources_io: base: 1428 size: 1428 align: 12 gran: 0 limit: ffff done
+DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
+PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 01:00.2 20 * [0x0 - 0x3fff] prefmem
+PCI: 01:00.2 18 * [0x4000 - 0x4fff] prefmem
+PCI: 00:04.0 compute_resources_prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 01:00.0 10 * [0x0 - 0xffff] mem
+PCI: 00:04.0 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:05.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:05.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:05.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 02:00.0 10 * [0x0 - 0x7ffff] mem
+PCI: 02:00.0 30 * [0x80000 - 0x8ffff] mem
+PCI: 00:05.0 compute_resources_mem: base: 90000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:01.0 10 * [0x0 - 0xfffffff] prefmem
+PCI: 00:04.0 24 * [0x10000000 - 0x100fffff] prefmem
+PCI: 00:04.0 20 * [0x10100000 - 0x101fffff] mem
+PCI: 00:05.0 20 * [0x10200000 - 0x102fffff] mem
+PCI: 00:01.0 18 * [0x10300000 - 0x1033ffff] mem
+PCI: 00:01.1 10 * [0x10340000 - 0x10343fff] mem
+PCI: 00:14.2 10 * [0x10344000 - 0x10347fff] mem
+PCI: 00:10.0 10 * [0x10348000 - 0x10349fff] mem
+PCI: 00:12.0 10 * [0x1034a000 - 0x1034afff] mem
+PCI: 00:13.0 10 * [0x1034b000 - 0x1034bfff] mem
+PCI: 00:14.5 10 * [0x1034c000 - 0x1034cfff] mem
+PCI: 00:11.0 24 * [0x1034d000 - 0x1034d7ff] mem
+PCI: 00:12.2 10 * [0x1034d800 - 0x1034d8ff] mem
+PCI: 00:13.2 10 * [0x1034d900 - 0x1034d9ff] mem
+PCI: 00:14.7 10 * [0x1034da00 - 0x1034daff] mem
+DOMAIN: 0000 compute_resources_mem: base: 1034db00 size: 1034db00 align: 28 gran: 0 limit: ffffffff done
+avoid_fixed_resources: DOMAIN: 0000
+avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
+constrain_resources: DOMAIN: 0000
+constrain_resources: PCI: 00:00.0
+constrain_resources: PCI: 00:01.0
+constrain_resources: PCI: 00:01.1
+constrain_resources: PCI: 00:04.0
+constrain_resources: PCI: 01:00.0
+constrain_resources: PCI: 01:00.2
+constrain_resources: PCI: 00:05.0
+constrain_resources: PCI: 02:00.0
+constrain_resources: PCI: 00:10.0
+constrain_resources: PCI: 00:11.0
+constrain_resources: PCI: 00:12.0
+constrain_resources: PCI: 00:12.2
+constrain_resources: PCI: 00:13.0
+constrain_resources: PCI: 00:13.2
+constrain_resources: PCI: 00:14.0
+constrain_resources: I2C: 01:50
+constrain_resources: I2C: 01:51
+constrain_resources: PCI: 00:14.2
+constrain_resources: PCI: 00:14.3
+constrain_resources: PNP: 00ff.1
+constrain_resources: PNP: 00ff.0
+constrain_resources: PCI: 00:14.4
+constrain_resources: PCI: 00:14.5
+constrain_resources: PCI: 00:14.7
+constrain_resources: PCI: 00:18.0
+constrain_resources: PCI: 00:18.1
+constrain_resources: PCI: 00:18.2
+constrain_resources: PCI: 00:18.3
+constrain_resources: PCI: 00:18.4
+constrain_resources: PCI: 00:18.5
+avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff
+ lim->base 00001000 lim->limit 0000ffff
+avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff
+ lim->base 00000000 lim->limit f7ffffff
+Setting resources...
+DOMAIN: 0000 allocate_resources_io: base:1000 size:1428 align:12 gran:0 limit:ffff
+Assigned: PCI: 00:04.0 1c * [0x1000 - 0x1fff] io
+Assigned: PCI: 00:01.0 14 * [0x2000 - 0x20ff] io
+Assigned: PCI: 00:11.0 20 * [0x2400 - 0x240f] io
+Assigned: PCI: 00:11.0 10 * [0x2410 - 0x2417] io
+Assigned: PCI: 00:11.0 18 * [0x2418 - 0x241f] io
+Assigned: PCI: 00:11.0 14 * [0x2420 - 0x2423] io
+Assigned: PCI: 00:11.0 1c * [0x2424 - 0x2427] io
+DOMAIN: 0000 allocate_resources_io: next_base: 2428 size: 1428 align: 12 gran: 0 done
+PCI: 00:04.0 allocate_resources_io: base:1000 size:1000 align:12 gran:12 limit:ffff
+Assigned: PCI: 01:00.2 10 * [0x1000 - 0x10ff] io
+PCI: 00:04.0 allocate_resources_io: next_base: 1100 size: 1000 align: 12 gran: 12 done
+PCI: 00:05.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:05.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
+PCI: 00:14.4 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff
+PCI: 00:14.4 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done
+DOMAIN: 0000 allocate_resources_mem: base:e0000000 size:1034db00 align:28 gran:0 limit:f7ffffff
+Assigned: PCI: 00:01.0 10 * [0xe0000000 - 0xefffffff] prefmem
+Assigned: PCI: 00:04.0 24 * [0xf0000000 - 0xf00fffff] prefmem
+Assigned: PCI: 00:04.0 20 * [0xf0100000 - 0xf01fffff] mem
+Assigned: PCI: 00:05.0 20 * [0xf0200000 - 0xf02fffff] mem
+Assigned: PCI: 00:01.0 18 * [0xf0300000 - 0xf033ffff] mem
+Assigned: PCI: 00:01.1 10 * [0xf0340000 - 0xf0343fff] mem
+Assigned: PCI: 00:14.2 10 * [0xf0344000 - 0xf0347fff] mem
+Assigned: PCI: 00:10.0 10 * [0xf0348000 - 0xf0349fff] mem
+Assigned: PCI: 00:12.0 10 * [0xf034a000 - 0xf034afff] mem
+Assigned: PCI: 00:13.0 10 * [0xf034b000 - 0xf034bfff] mem
+Assigned: PCI: 00:14.5 10 * [0xf034c000 - 0xf034cfff] mem
+Assigned: PCI: 00:11.0 24 * [0xf034d000 - 0xf034d7ff] mem
+Assigned: PCI: 00:12.2 10 * [0xf034d800 - 0xf034d8ff] mem
+Assigned: PCI: 00:13.2 10 * [0xf034d900 - 0xf034d9ff] mem
+Assigned: PCI: 00:14.7 10 * [0xf034da00 - 0xf034daff] mem
+DOMAIN: 0000 allocate_resources_mem: next_base: f034db00 size: 1034db00 align: 28 gran: 0 done
+PCI: 00:04.0 allocate_resources_prefmem: base:f0000000 size:100000 align:20 gran:20 limit:f7ffffff
+Assigned: PCI: 01:00.2 20 * [0xf0000000 - 0xf0003fff] prefmem
+Assigned: PCI: 01:00.2 18 * [0xf0004000 - 0xf0004fff] prefmem
+PCI: 00:04.0 allocate_resources_prefmem: next_base: f0005000 size: 100000 align: 20 gran: 20 done
+PCI: 00:04.0 allocate_resources_mem: base:f0100000 size:100000 align:20 gran:20 limit:f7ffffff
+Assigned: PCI: 01:00.0 10 * [0xf0100000 - 0xf010ffff] mem
+PCI: 00:04.0 allocate_resources_mem: next_base: f0110000 size: 100000 align: 20 gran: 20 done
+PCI: 00:05.0 allocate_resources_prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
+PCI: 00:05.0 allocate_resources_prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
+PCI: 00:05.0 allocate_resources_mem: base:f0200000 size:100000 align:20 gran:20 limit:f7ffffff
+Assigned: PCI: 02:00.0 10 * [0xf0200000 - 0xf027ffff] mem
+Assigned: PCI: 02:00.0 30 * [0xf0280000 - 0xf028ffff] mem
+PCI: 00:05.0 allocate_resources_mem: next_base: f0290000 size: 100000 align: 20 gran: 20 done
+PCI: 00:14.4 allocate_resources_prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
+PCI: 00:14.4 allocate_resources_prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
+PCI: 00:14.4 allocate_resources_mem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff
+PCI: 00:14.4 allocate_resources_mem: next_base: f7ffffff size: 0 align: 20 gran: 20 done
+Root Device assign_resources, bus 0 link: 0
+node 0: mmio_basek=00380000, basek=00000300, limitk=001e0000
+CBMEM region 5ec20000-5effffff (cbmem_late_set_table)
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+PCI: 00:01.0 10 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem
+PCI: 00:01.0 14 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io
+PCI: 00:01.0 18 <- [0x00f0300000 - 0x00f033ffff] size 0x00040000 gran 0x12 mem
+PCI: 00:01.1 10 <- [0x00f0340000 - 0x00f0343fff] size 0x00004000 gran 0x0e mem
+PCI: 00:04.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io
+PCI: 00:04.0 24 <- [0x00f0000000 - 0x00f00fffff] size 0x00100000 gran 0x14 bus 01 prefmem
+PCI: 00:04.0 20 <- [0x00f0100000 - 0x00f01fffff] size 0x00100000 gran 0x14 bus 01 mem
+PCI: 00:04.0 assign_resources, bus 1 link: 0
+PCI: 01:00.0 10 <- [0x00f0100000 - 0x00f010ffff] size 0x00010000 gran 0x10 mem
+PCI: 01:00.2 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io
+PCI: 01:00.2 18 <- [0x00f0004000 - 0x00f0004fff] size 0x00001000 gran 0x0c prefmem64
+PCI: 01:00.2 20 <- [0x00f0000000 - 0x00f0003fff] size 0x00004000 gran 0x0e prefmem64
+PCI: 00:04.0 assign_resources, bus 1 link: 0
+PCI: 00:05.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io
+PCI: 00:05.0 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem
+PCI: 00:05.0 20 <- [0x00f0200000 - 0x00f02fffff] size 0x00100000 gran 0x14 bus 02 mem
+PCI: 00:05.0 assign_resources, bus 2 link: 0
+PCI: 02:00.0 10 <- [0x00f0200000 - 0x00f027ffff] size 0x00080000 gran 0x13 mem64
+PCI: 02:00.0 30 <- [0x00f0280000 - 0x00f028ffff] size 0x00010000 gran 0x10 romem
+PCI: 00:05.0 assign_resources, bus 2 link: 0
+PCI: 00:10.0 10 <- [0x00f0348000 - 0x00f0349fff] size 0x00002000 gran 0x0d mem64
+PCI: 00:11.0 10 <- [0x0000002410 - 0x0000002417] size 0x00000008 gran 0x03 io
+PCI: 00:11.0 14 <- [0x0000002420 - 0x0000002423] size 0x00000004 gran 0x02 io
+PCI: 00:11.0 18 <- [0x0000002418 - 0x000000241f] size 0x00000008 gran 0x03 io
+PCI: 00:11.0 1c <- [0x0000002424 - 0x0000002427] size 0x00000004 gran 0x02 io
+PCI: 00:11.0 20 <- [0x0000002400 - 0x000000240f] size 0x00000010 gran 0x04 io
+PCI: 00:11.0 24 <- [0x00f034d000 - 0x00f034d7ff] size 0x00000800 gran 0x0b mem
+PCI: 00:12.0 10 <- [0x00f034a000 - 0x00f034afff] size 0x00001000 gran 0x0c mem
+PCI: 00:12.2 10 <- [0x00f034d800 - 0x00f034d8ff] size 0x00000100 gran 0x08 mem
+PCI: 00:13.0 10 <- [0x00f034b000 - 0x00f034bfff] size 0x00001000 gran 0x0c mem
+PCI: 00:13.2 10 <- [0x00f034d900 - 0x00f034d9ff] size 0x00000100 gran 0x08 mem
+PCI: 00:14.2 10 <- [0x00f0344000 - 0x00f0347fff] size 0x00004000 gran 0x0e mem64
+PCI: 00:14.3 assign_resources, bus 0 link: 0
+PCI: 00:14.3 assign_resources, bus 0 link: 0
+PCI: 00:14.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io
+PCI: 00:14.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 03 prefmem
+PCI: 00:14.4 20 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 03 mem
+PCI: 00:14.5 10 <- [0x00f034c000 - 0x00f034cfff] size 0x00001000 gran 0x0c mem
+PCI: 00:14.7 10 <- [0x00f034da00 - 0x00f034daff] size 0x00000100 gran 0x08 mem64
+PCI: 00:18.0 c0010058 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x00 mem <mmconfig>
+DOMAIN: 0000 assign_resources, bus 0 link: 0
+Root Device assign_resources, bus 0 link: 0
+Done setting resources.
+Show resources in subtree (Root Device)...After assigning values.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 10
+ APIC: 10
+ APIC: 11
+ APIC: 12
+ APIC: 13
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 1000 size 1428 align 12 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base e0000000 size 1034db00 align 28 gran 0 limit f7ffffff flags 40040200 index 10000100
+ DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10
+ DOMAIN: 0000 resource base c0000 size 77f40000 align 0 gran 0 limit 0 flags e0004200 index 20
+ DOMAIN: 0000 resource base 5f000000 size 20000000 align 0 gran 0 limit 0 flags f0000200 index 7
+ PCI: 00:00.0
+ PCI: 00:01.0
+ PCI: 00:01.0 resource base e0000000 size 10000000 align 28 gran 28 limit f7ffffff flags 60001200 index 10
+ PCI: 00:01.0 resource base 2000 size 100 align 8 gran 8 limit ffff flags 60000100 index 14
+ PCI: 00:01.0 resource base f0300000 size 40000 align 18 gran 18 limit f7ffffff flags 60000200 index 18
+ PCI: 00:01.1
+ PCI: 00:01.1 resource base f0340000 size 4000 align 14 gran 14 limit f7ffffff flags 60000200 index 10
+ PCI: 00:03.0
+ PCI: 00:04.0 child on link 0 PCI: 01:00.0
+ PCI: 00:04.0 resource base 1000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:04.0 resource base f0000000 size 100000 align 20 gran 20 limit f7ffffff flags 60081202 index 24
+ PCI: 00:04.0 resource base f0100000 size 100000 align 20 gran 20 limit f7ffffff flags 60080202 index 20
+ PCI: 01:00.0
+ PCI: 01:00.0 resource base f0100000 size 10000 align 16 gran 16 limit f7ffffff flags 60000200 index 10
+ PCI: 01:00.2
+ PCI: 01:00.2 resource base 1000 size 100 align 8 gran 8 limit ffff flags 60000100 index 10
+ PCI: 01:00.2 resource base f0004000 size 1000 align 12 gran 12 limit f7ffffff flags 60001201 index 18
+ PCI: 01:00.2 resource base f0000000 size 4000 align 14 gran 14 limit f7ffffff flags 60001201 index 20
+ PCI: 00:05.0 child on link 0 PCI: 02:00.0
+ PCI: 00:05.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:05.0 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
+ PCI: 00:05.0 resource base f0200000 size 100000 align 20 gran 20 limit f7ffffff flags 60080202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base f0200000 size 80000 align 19 gran 19 limit f7ffffff flags 60000201 index 10
+ PCI: 02:00.0 resource base f0280000 size 10000 align 16 gran 16 limit f7ffffff flags 60002200 index 30
+ PCI: 00:08.0
+ PCI: 00:10.0
+ PCI: 00:10.0 resource base f0348000 size 2000 align 13 gran 13 limit f7ffffff flags 60000201 index 10
+ PCI: 00:11.0
+ PCI: 00:11.0 resource base 2410 size 8 align 3 gran 3 limit ffff flags 60000100 index 10
+ PCI: 00:11.0 resource base 2420 size 4 align 2 gran 2 limit ffff flags 60000100 index 14
+ PCI: 00:11.0 resource base 2418 size 8 align 3 gran 3 limit ffff flags 60000100 index 18
+ PCI: 00:11.0 resource base 2424 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c
+ PCI: 00:11.0 resource base 2400 size 10 align 4 gran 4 limit ffff flags 60000100 index 20
+ PCI: 00:11.0 resource base f034d000 size 800 align 11 gran 11 limit f7ffffff flags 60000200 index 24
+ PCI: 00:12.0
+ PCI: 00:12.0 resource base f034a000 size 1000 align 12 gran 12 limit f7ffffff flags 60000200 index 10
+ PCI: 00:12.2
+ PCI: 00:12.2 resource base f034d800 size 100 align 8 gran 8 limit f7ffffff flags 60000200 index 10
+ PCI: 00:13.0
+ PCI: 00:13.0 resource base f034b000 size 1000 align 12 gran 12 limit f7ffffff flags 60000200 index 10
+ PCI: 00:13.2
+ PCI: 00:13.2 resource base f034d900 size 100 align 8 gran 8 limit f7ffffff flags 60000200 index 10
+ PCI: 00:14.0 child on link 0 I2C: 01:50
+ I2C: 01:50
+ I2C: 01:51
+ PCI: 00:14.2
+ PCI: 00:14.2 resource base f0344000 size 4000 align 14 gran 14 limit f7ffffff flags 60000201 index 10
+ PCI: 00:14.3 child on link 0 PNP: 00ff.1
+ PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2
+ PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 00ff.1
+ PNP: 00ff.0
+ PCI: 00:14.4
+ PCI: 00:14.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c
+ PCI: 00:14.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24
+ PCI: 00:14.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60080202 index 20
+ PCI: 00:14.5
+ PCI: 00:14.5 resource base f034c000 size 1000 align 12 gran 12 limit f7ffffff flags 60000200 index 10
+ PCI: 00:14.6
+ PCI: 00:14.7
+ PCI: 00:14.7 resource base f034da00 size 100 align 8 gran 8 limit f7ffffff flags 60000201 index 10
+ PCI: 00:15.0
+ PCI: 00:15.1
+ PCI: 00:15.2
+ PCI: 00:15.3
+ PCI: 00:18.0
+ PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
+ PCI: 00:18.1
+ PCI: 00:18.2
+ PCI: 00:18.3
+ PCI: 00:18.4
+ PCI: 00:18.5
+Done allocating resources.
+BS: BS_DEV_RESOURCES times (us): entry 0 run 1661 exit 0
+Warning: Can't write PCI_INTR 0xC00/0xC01 registers because
+'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL
+Warning: Can't write PCI IRQ assignments because 'mainboard_pirq_data' structure does not exist
+Enabling resources...
+agesawrapper_amdinitmid() returned AGESA_SUCCESS
+ ader - leaving domain_enable_resources.
+PCI: 00:00.0 subsystem <- 1022/1410
+PCI: 00:00.0 cmd <- 06
+PCI: 00:01.0 subsystem <- 1022/1410
+PCI: 00:01.0 cmd <- 07
+PCI: 00:01.1 subsystem <- 1022/1410
+PCI: 00:01.1 cmd <- 02
+PCI: 00:04.0 bridge ctrl <- 0003
+PCI: 00:04.0 cmd <- 07
+PCI: 00:05.0 bridge ctrl <- 0003
+PCI: 00:05.0 cmd <- 06
+PCI: 00:10.0 subsystem <- 1022/1410
+PCI: 00:10.0 cmd <- 02
+PCI: 00:11.0 cmd <- 03
+PCI: 00:12.0 subsystem <- 1022/1410
+PCI: 00:12.0 cmd <- 02
+PCI: 00:12.2 subsystem <- 1022/1410
+PCI: 00:12.2 cmd <- 02
+PCI: 00:13.0 subsystem <- 1022/1410
+PCI: 00:13.0 cmd <- 02
+PCI: 00:13.2 subsystem <- 1022/1410
+PCI: 00:13.2 cmd <- 02
+PCI: 00:14.0 subsystem <- 1022/1410
+PCI: 00:14.0 cmd <- 403
+PCI: 00:14.2 subsystem <- 1022/1410
+PCI: 00:14.2 cmd <- 02
+PCI: 00:14.3 subsystem <- 1022/1410
+PCI: 00:14.3 cmd <- 0f
+PCI: 00:14.4 bridge ctrl <- 0003
+PCI: 00:14.4 cmd <- 00
+PCI: 00:14.5 subsystem <- 1022/1410
+PCI: 00:14.5 cmd <- 02
+PCI: 00:14.7 subsystem <- 1022/1410
+PCI: 00:14.7 cmd <- 06
+PCI: 00:18.0 cmd <- 00
+PCI: 00:18.1 subsystem <- 1022/1410
+PCI: 00:18.1 cmd <- 00
+PCI: 00:18.2 subsystem <- 1022/1410
+PCI: 00:18.2 cmd <- 00
+PCI: 00:18.3 subsystem <- 1022/1410
+PCI: 00:18.3 cmd <- 00
+PCI: 00:18.4 subsystem <- 1022/1410
+PCI: 00:18.4 cmd <- 00
+PCI: 00:18.5 subsystem <- 1022/1410
+PCI: 00:18.5 cmd <- 00
+PCI: 01:00.0 cmd <- 02
+PCI: 01:00.2 cmd <- 03
+PCI: 02:00.0 cmd <- 02
+done.
+BS: BS_DEV_ENABLE times (us): entry 2 run 7041 exit 0
+Initializing devices...
+Root Device init
+Root Device init 0 usecs
+CPU_CLUSTER: 0 init
+start_eip=0x00001000, code_size=0x00000031
+Initializing CPU #0
+CPU: vendor AMD device 610f01
+CPU: family 15, model 10, stepping 01
+Using generic cpu ops (good)
+Model 15 Init.
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Enabling cache
+Setting up local apic... apic_id: 0x10 done.
+siblings = 03, Initializing SMM for CPU 0
+CPU #0 initialized
+CPU1: stack_base 001d1000, stack_end 001d1ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 17.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 17.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+Initializing CPU #1
+CPU: vendor AMD device 610f01
+CPU: family 15, model 10, stepping 01
+Using generic cpu ops (good)
+Model 15 Init.
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Enabling cache
+Setting up local apic... apic_id: 0x11 done.
+siblings = 03, Initializing SMM for CPU 1
+CPU #1 initialized
+CPU2: stack_base 001d0000, stack_end 001d0ff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 18.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 18.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+Initializing CPU #2
+CPU: vendor AMD device 610f01
+CPU: family 15, model 10, stepping 01
+Using generic cpu ops (good)
+Model 15 Init.
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Enabling cache
+Setting up local apic... apic_id: 0x12 done.
+siblings = 03, Initializing SMM for CPU 2
+CPU #2 initialized
+CPU3: stack_base 001cf000, stack_end 001cfff8
+Asserting INIT.
+Waiting for send to finish...
++Deasserting INIT.
+Waiting for send to finish...
++#startup loops: 2.
+Sending STARTUP #1 to 19.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++Sending STARTUP #2 to 19.
+After apic_write.
+Startup point 1.
+Waiting for send to finish...
++After Startup.
+Initializing CPU #3
+Waiting for 1 CPUS to stop
+CPU: vendor AMD device 610f01
+CPU: family 15, model 10, stepping 01
+Using generic cpu ops (good)
+Model 15 Init.
+
+MTRR check
+Fixed MTRRs : Enabled
+Variable MTRRs: Enabled
+
+Enabling cache
+Setting up local apic... apic_id: 0x13 done.
+siblings = 03, Initializing SMM for CPU 3
+CPU #3 initialized
+All AP CPUs stopped (42 loops)
+CPU1: stack: 001d1000 - 001d2000, lowest used address 001d1dd0, stack used: 560 bytes
+CPU2: stack: 001d0000 - 001d1000, lowest used address 001d0dd0, stack used: 560 bytes
+CPU3: stack: 001cf000 - 001d0000, lowest used address 001cfdd0, stack used: 560 bytes
+CPU_CLUSTER: 0 init 36317 usecs
+PCI: 00:00.0 init
+PCI: 00:00.0 init 0 usecs
+PCI: 00:01.0 init
+In CBFS, ROM address for PCI: 00:01.0 = ffc00778
+PCI expansion ROM, signature 0xaa55, INIT size 0xfa00, data ptr 0x01b4
+PCI ROM image, vendor ID 1002, device ID 9900,
+PCI ROM image, Class Code 030000, Code Type 00
+Copying VGA ROM Image from ffc00778 to 0xc0000, 0xfa00 bytes
+Real mode stub @00000600: 867 bytes
+Calling Option ROM...
+... Option ROM returned.
+VBE: Getting information about VESA mode 4117
+VBE: resolution: 1024x768@16
+VBE: framebuffer: e0000000
+VBE: Setting VESA mode 4117
+VGA Option ROM was run
+PCI: 00:01.0 init 70693 usecs
+PCI: 00:01.1 init
+PCI: 00:01.1 init 1 usecs
+PCI: 00:10.0 init
+PCI: 00:10.0 init 1 usecs
+PCI: 00:11.0 init
+PCI: 00:11.0 init 0 usecs
+PCI: 00:12.0 init
+PCI: 00:12.0 init 0 usecs
+PCI: 00:12.2 init
+PCI: 00:12.2 init 1 usecs
+PCI: 00:13.0 init
+PCI: 00:13.0 init 0 usecs
+PCI: 00:13.2 init
+PCI: 00:13.2 init 0 usecs
+PCI: 00:14.0 init
+IOAPIC: Initializing IOAPIC at 0xfec00000
+IOAPIC: Bootstrap Processor Local APIC = 0x10
+IOAPIC: ID = 0x04
+IOAPIC: Dumping registers
+ reg 0x0000: 0x04000000
+ reg 0x0001: 0x00178021
+ reg 0x0002: 0x04000000
+IOAPIC: 24 interrupts
+IOAPIC: Enabling interrupts on FSB
+IOAPIC: reg 0x00000000 value 0x10000000 0x00000700
+IOAPIC: reg 0x00000001 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000002 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000003 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000004 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000005 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000006 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000007 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000008 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000009 value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000a value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000b value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000c value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000d value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000e value 0x00000000 0x00010000
+IOAPIC: reg 0x0000000f value 0x00000000 0x00010000
+IOAPIC: reg 0x00000010 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000011 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000012 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000013 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000014 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000015 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000016 value 0x00000000 0x00010000
+IOAPIC: reg 0x00000017 value 0x00000000 0x00010000
+PCI: 00:14.0 init 21 usecs
+PCI: 00:14.2 init
+PCI: 00:14.2 init 1 usecs
+PCI: 00:14.3 init
+RTC Init
+RTC: coreboot checksum invalid
+PCI: 00:14.3 init 166 usecs
+PCI: 00:14.4 init
+PCI: 00:14.4 init 0 usecs
+PCI: 00:14.5 init
+PCI: 00:14.5 init 0 usecs
+PCI: 00:14.7 init
+PCI: 00:14.7 init 1 usecs
+PCI: 00:18.0 init
+PCI: 00:18.0 init 0 usecs
+PCI: 00:18.1 init
+PCI: 00:18.1 init 0 usecs
+PCI: 00:18.2 init
+PCI: 00:18.2 init 1 usecs
+PCI: 00:18.3 init
+PCI: 00:18.3 init 0 usecs
+PCI: 00:18.4 init
+PCI: 00:18.4 init 0 usecs
+PCI: 00:18.5 init
+PCI: 00:18.5 init 1 usecs
+PCI: 01:00.0 init
+PCI: 01:00.0 init 0 usecs
+PCI: 01:00.2 init
+PCI: 01:00.2 init 0 usecs
+PCI: 02:00.0 init
+PCI: 02:00.0 init 1 usecs
+PNP: 00ff.0 init
+Compal ENE932: Initializing keyboard.
+PNP: 00ff.0 init 1 usecs
+Devices initialized
+Show all devs...After init.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 10: enabled 1
+DOMAIN: 0000: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 00:01.1: enabled 1
+PCI: 00:03.0: enabled 0
+PCI: 00:04.0: enabled 1
+PCI: 00:05.0: enabled 1
+PCI: 00:08.0: enabled 0
+PCI: 00:10.0: enabled 1
+PCI: 00:11.0: enabled 1
+PCI: 00:12.0: enabled 1
+PCI: 00:12.2: enabled 1
+PCI: 00:13.0: enabled 1
+PCI: 00:13.2: enabled 1
+PCI: 00:14.0: enabled 1
+I2C: 01:50: enabled 1
+I2C: 01:51: enabled 1
+PCI: 00:14.2: enabled 1
+PCI: 00:14.3: enabled 1
+PNP: 00ff.1: enabled 1
+PCI: 00:14.4: enabled 1
+PCI: 00:14.5: enabled 1
+PCI: 00:14.6: enabled 0
+PCI: 00:14.7: enabled 1
+PCI: 00:15.0: enabled 0
+PCI: 00:15.1: enabled 0
+PCI: 00:15.2: enabled 0
+PCI: 00:15.3: enabled 0
+PCI: 00:18.0: enabled 1
+PCI: 00:18.1: enabled 1
+PCI: 00:18.2: enabled 1
+PCI: 00:18.3: enabled 1
+PCI: 00:18.4: enabled 1
+PCI: 00:18.5: enabled 1
+APIC: 11: enabled 1
+APIC: 12: enabled 1
+APIC: 13: enabled 1
+PCI: 01:00.0: enabled 1
+PCI: 01:00.2: enabled 1
+PCI: 02:00.0: enabled 1
+PNP: 00ff.0: enabled 1
+BS: BS_DEV_INIT times (us): entry 8 run 107257 exit 0
+CBMEM region 5ec20000-5effffff (cbmem_check_toc)
+CBMEM region 5ec20000-5effffff (cbmem_initialize_empty)
+Adding CBMEM entry as no. 1
+Moving GDT to 5ec20200...ok
+Adding CBMEM entry as no. 2
+Finalize devices...
+Devices finalized
+Adding CBMEM entry as no. 3
+agesawrapper_amdinitlate() returned AGESA_SUCCESS
+DmiTable:0, AcpiPstatein: 10010126, AcpiSrat:0,AcpiSlit:0, Mce:100111ba, Cmc:1001127c,Alib:100123c3, AcpiIvrs:0 in agesawrapper_amdinitlate
+agesawrapper_amdS3Save() returned AGESA_SUCCESS
+SF: Detected W25Q32 with page size 1000, total 400000
+SF: Successfully erased 4096 bytes @ 0xffff7000
+SF: Detected W25Q32 with page size 1000, total 400000
+SF: Successfully erased 24576 bytes @ 0xffff0000
+SF: Detected W25Q32 with page size 1000, total 400000
+SF: Successfully erased 4096 bytes @ 0xffff6000
+BS: BS_POST_DEVICE times (us): entry 9 run 2 exit 280541
+Adding CBMEM entry as no. 4
+Adding CBMEM entry as no. 5
+BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0
+Writing IRQ routing tables to 0xf0000...write_pirq_routing_table done.
+Adding CBMEM entry as no. 6
+Writing IRQ routing tables to 0x5efd1600...write_pirq_routing_table done.
+PIRQ table: 48 bytes.
+Wrote the mp table end at: 000f0410 - 000f0624
+Adding CBMEM entry as no. 7
+Wrote the mp table end at: 5efd2610 - 5efd2824
+MP table: 548 bytes.
+Adding CBMEM entry as no. 8
+ACPI: Writing ACPI tables at 5efd3600.
+ACPI: * FACS
+ACPI: * DSDT
+ACPI: * FADT
+pm_base: 0x0800
+ACPI: added table 1/32, length now 40
+ACPI: * SSDT
+ACPI: added table 2/32, length now 44
+ACPI: * MCFG
+ACPI: * MADT
+ACPI: added table 3/32, length now 48
+current = 5efd5e20
+ACPI: * HPET
+ACPI: added table 4/32, length now 52
+ACPI: added table 5/32, length now 56
+ACPI: * IVRS at 5efd6030
+ AGESA IVRS table NULL. Skipping.
+ACPI: * SRAT at 5efd6030
+ AGESA SRAT table NULL. Skipping.
+ACPI: * SLIT at 5efd6030
+ AGESA SLIT table NULL. Skipping.
+ACPI: * AGESA ALIB SSDT at 5efd6030
+ACPI: added table 6/32, length now 60
+ACPI: * SSDT at 5efd7f10
+ACPI: added table 7/32, length now 64
+ACPI: * SSDT for PState at 5efd8aac
+ACPI: done.
+ACPI tables: 21680 bytes.
+Adding CBMEM entry as no. 9
+smbios_write_tables: 5efdea00
+Root Device (HP Pavilion m6 1035dx)
+CPU_CLUSTER: 0 (AMD FAM15tn Root Complex)
+APIC: 10 (AMD CPU Family 15h)
+DOMAIN: 0000 (AMD FAM15tn Root Complex)
+PCI: 00:00.0 (AMD FAM15 Northbridge)
+PCI: 00:01.0 (AMD FAM15 Northbridge)
+PCI: 00:01.1 (AMD FAM15 Northbridge)
+PCI: 00:03.0 (AMD FAM15 Northbridge)
+PCI: 00:04.0 (AMD FAM15 Northbridge)
+PCI: 00:05.0 (AMD FAM15 Northbridge)
+PCI: 00:08.0 (AMD FAM15 Northbridge)
+PCI: 00:10.0 (ATI HUDSON)
+PCI: 00:11.0 (ATI HUDSON)
+PCI: 00:12.0 (ATI HUDSON)
+PCI: 00:12.2 (ATI HUDSON)
+PCI: 00:13.0 (ATI HUDSON)
+PCI: 00:13.2 (ATI HUDSON)
+PCI: 00:14.0 (ATI HUDSON)
+I2C: 01:50 (unknown)
+I2C: 01:51 (unknown)
+PCI: 00:14.2 (ATI HUDSON)
+PCI: 00:14.3 (ATI HUDSON)
+PNP: 00ff.1 (COMPAL ENE932 EC)
+PCI: 00:14.4 (ATI HUDSON)
+PCI: 00:14.5 (ATI HUDSON)
+PCI: 00:14.6 (ATI HUDSON)
+PCI: 00:14.7 (ATI HUDSON)
+PCI: 00:15.0 (ATI HUDSON)
+PCI: 00:15.1 (ATI HUDSON)
+PCI: 00:15.2 (ATI HUDSON)
+PCI: 00:15.3 (ATI HUDSON)
+PCI: 00:18.0 (AMD FAM15 Northbridge)
+PCI: 00:18.1 (AMD FAM15 Northbridge)
+PCI: 00:18.2 (AMD FAM15 Northbridge)
+PCI: 00:18.3 (AMD FAM15 Northbridge)
+PCI: 00:18.4 (AMD FAM15 Northbridge)
+PCI: 00:18.5 (AMD FAM15 Northbridge)
+APIC: 11 (unknown)
+APIC: 12 (unknown)
+APIC: 13 (unknown)
+PCI: 01:00.0 (unknown)
+PCI: 01:00.2 (unknown)
+PCI: 02:00.0 (unknown)
+PNP: 00ff.0 (unknown)
+SMBIOS tables: 344 bytes.
+Adding CBMEM entry as no. 10
+Writing table forward entry at 0x00000500
+Wrote coreboot table at: 00000500, 0x10 bytes, checksum aee0
+Table forward entry ends at 0x00000528.
+... aligned to 0x00001000
+Writing coreboot table at 0x5efdf200
+rom_table_end = 0x5efdf200
+... aligned to 0x5efe0000
+ 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
+ 1. 0000000000001000-000000000009ffff: RAM
+ 2. 00000000000c0000-000000005ec1ffff: RAM
+ 3. 000000005ec20000-000000005effffff: CONFIGURATION TABLES
+ 4. 000000005f000000-000000007effffff: RESERVED
+ 5. 00000000f8000000-00000000fbffffff: RESERVED
+Wrote coreboot table at: 5efdf200, 0x888 bytes, checksum 52ed
+coreboot table: 2208 bytes.
+FREE SPACE 0. 5efe7200 00018e00
+GDT 1. 5ec20200 00000200
+CONSOLE 2. 5ec20400 00010000
+TIME STAMP 3. 5ec30400 00000200
+ACPI RESUME 4. 5ec30600 00300000
+ACPISCRATCH 5. 5ef30600 000a1000
+IRQ TABLE 6. 5efd1600 00001000
+SMP TABLE 7. 5efd2600 00001000
+ACPI 8. 5efd3600 0000b400
+SMBIOS 9. 5efdea00 00000800
+COREBOOT 10. 5efdf200 00008000
+BS: BS_WRITE_TABLES times (us): entry 0 run 680 exit 0
+CBFS: located payload @ ffc107b8, 51774 bytes.
+Loading segment from rom address 0xffc107b8
+ code (compression=1)
+ New segment dstaddr 0xe7d4c memsize 0x182b4 srcaddr 0xffc107f0 filesize 0xca06
+ (cleaned up) New segment addr 0xe7d4c size 0x182b4 offset 0xffc107f0 filesize 0xca06
+Loading segment from rom address 0xffc107d4
+ Entry Point 0x000fd587
+Bounce Buffer at 5e8f9000, 3301472 bytes
+Loading Segment: addr: 0x00000000000e7d4c memsz: 0x00000000000182b4 filesz: 0x000000000000ca06
+lb: [0x0000000000100000, 0x0000000000293030)
+Post relocation: addr: 0x00000000000e7d4c memsz: 0x00000000000182b4 filesz: 0x000000000000ca06
+using LZMA
+[ 0x000e7d4c, 00100000, 0x00100000) <- ffc107f0
+dest 000e7d4c, end 00100000, bouncebuffer 5e8f9000
+Loaded segments
+BS: BS_PAYLOAD_LOAD times (us): entry 0 run 11793 exit 0
+Jumping to boot code at 000fd587
+CPU0: stack: 001d2000 - 001d3000, lowest used address 001d25e0, stack used: 2592 bytes
+entry = 0x000fd587
+lb_start = 0x00100000
+lb_size = 0x00193030
+buffer = 0x5e8f9000
+SeaBIOS (version rel-1.7.5-0-ge51488c-20141205_193904-nuclearis2.gtech)
+Found coreboot cbmem console @ 5ec20400
+Found mainboard HP Pavilion m6 1035dx
+Relocating init from 0x000e8eb1 to 0x5ebd59e0 (size 42332)
+Found CBFS header at 0xfffffa68
+CPU Mhz=2297
+Found 26 PCI devices (max PCI bus is 03)
+Copying PIR from 0x5efd1600 to 0x000f33e0
+Copying MPTABLE from 0x5efd2600/5efd2610 to 0x000f31b0
+Copying ACPI RSDP from 0x5efd3600 to 0x000f3180
+Copying SMBIOS entry point from 0x5efdea00 to 0x000f3160
+Using pmtimer, ioport 0x818
+Scan for VGA option rom
+Running option rom at c000:0003
+Turning on vga text mode console
+SeaBIOS (version rel-1.7.5-0-ge51488c-20141205_193904-nuclearis2.gtech)
+XHCI init on dev 00:10.0: regs @ 0xf0348000, 4 ports, 32 slots, 32 byte contexts
+XHCI extcap 0x1 @ f0348500
+XHCI protocol USB 3.00, 2 ports (offset 1), def 0
+XHCI protocol USB 2.00, 2 ports (offset 3), def 0
+EHCI init on dev 00:12.2 (regs=0xf034d820)
+Found 0 serial ports
+AHCI controller at 11.0, iobase f034d000, irq 0
+EHCI init on dev 00:13.2 (regs=0xf034d920)
+Searching bootorder for: /pci@i0cf8/*@11/drive@0/disk@0
+AHCI/0: registering: "AHCI/0: Hitachi HTS547564A9E384 ATA-8 Hard-Disk (596 GiBytes)"
+OHCI init on dev 00:12.0 (regs=0xf034a000)
+OHCI init on dev 00:13.0 (regs=0xf034b000)
+OHCI init on dev 00:14.5 (regs=0xf034c000)
+XHCI no devices found
+PS2 keyboard initialized
+All threads complete.
+Scan for option roms
+
+Press F12 for boot menu.
+
+Searching bootorder for: HALT
+drive 0x000f30f0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=1250263728
+Space available for UMB: d0000-ee800, f0000-f30f0
+Returned 258048 bytes of ZoneHigh
+e820 map has 6 items:
+ 0: 0000000000000000 - 000000000009fc00 = 1 RAM
+ 1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
+ 2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
+ 3: 0000000000100000 - 000000005ec1f000 = 1 RAM
+ 4: 000000005ec1f000 - 000000007f000000 = 2 RESERVED
+ 5: 00000000f8000000 - 00000000fc000000 = 2 RESERVED
+enter handle_19:
+ NULL
+Booting from Hard Disk...
+Booting from 0000:7c00
+coreboot-4.0-7494-g4568f19-nuclearis Sat Dec 6 04:03:30 CST 2014 booting...
+BS: BS_PRE_DEVICE times (us): entry 0 run 0 exit 0
+BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 2 exit 0
+Enumerating buses...
+Show all devs...Before device enumeration.
+Root Device: enabled 1
+CPU_CLUSTER: 0: enabled 1
+APIC: 10: enabled 1
+DOMAIN: 0000: enabled 1
+PCI: 00:00.0: enabled 1
+PCI: 00:01.0: enabled 1
+PCI: 00:01.1: enabled 1
+PCI: 00:03.0: enabled 0
+PCI: 00:04.0: enabled 1
+PCI: 00:05.0: enabled 1
+PCI: 00:08.0: enabled 0
+PCI: 00:10.0: enabled 1
+PCI: 00:11.0: enabled 1
+PCI: 00:12.0: enabled 1
+PCI: 00:12.2: enabled 1
+PCI: 00:13.0: enabled 1
+PCI: 00:13.2: enabled 1
+PCI: 00:14.0: enabled 1
+I2C: 00:50: enabled 1
+I2C: 00:51: enabled 1
+PCI: 00:14.2: enabled 1
+PCI: 00:14.3: enabled 1
+PNP: 00ff.1: enabled 1
+PCI: 00:14.4: enabled 1
+PCI: 00:14.5: enabled 1
+PCI: 00:14.6: enabled 0
+PCI: 00:14.7: enabled 1
+PCI: 00:15.0: enabled 0
+PCI: 00:15.1: enabled 0
+PCI: 00:15.2: enabled 0
+PCI: 00:15.3: enabled 0
+PCI: 00:18.0: enabled 1
+PCI: 00:18.1: enabled 1
+PCI: 00:18.2: enabled 1
+PCI: 00:18.3: enabled 1
+PCI: 00:18.4: enabled 1
+PCI: 00:18.5: enabled 1
+Compare with tree...
+Root Device: enabled 1
+ CPU_CLUSTER: 0: enabled 1
+ APIC: 10: enabled 1
+ DOMAIN: 0000: enabled 1
+ PCI: 00:00.0: enabled 1
+ PCI: 00:01.0: enabled 1
+ PCI: 00:01.1: enabled 1
+ PCI: 00:03.0: enabled 0
+ PCI: 00:04.0: enabled 1
+ PCI: 00:05.0: enabled 1
+ PCI: 00:08.0: enabled 0
+ PCI: 00:10.0: enabled 1
+ PCI: 00:11.0: enabled 1
+ PCI: 00:12.0: enabled 1
+ PCI: 00:12.2: enabled 1
+ PCI: 00:13.0: enabled 1
+ PCI: 00:13.2: enabled 1
+ PCI: 00:14.0: enabled 1
+ I2C: 00:50: enabled 1
+ I2C: 00:51: enabled 1
+ PCI: 00:14.2: enabled 1
+ PCI: 00:14.3: enabled 1
+ PNP: 00ff.1: enabled 1
+ PCI: 00:14.4: enabled 1
+ PCI: 00:14.5: enabled 1
+ PCI: 00:14.6: enabled 0
+ PCI: 00:14.7: enabled 1
+ PCI: 00:15.0: enabled 0
+ PCI: 00:15.1: enabled 0
+ PCI: 00:15.2: enabled 0
+ PCI: 00:15.3: enabled 0
+ PCI: 00:18.0: enabled 1
+ PCI: 00:18.1: enabled 1
+ PCI: 00:18.2: enabled 1
+ PCI: 00:18.3: enabled 1
+ PCI: 00:18.4: enabled 1
+ PCI: 00:18.5: enabled 1
+Mainboard Pavilion m6 1035dx Enable.
+scan_static_bus for Root Device
+setup_bsp_ramtop, TOP MEM: msr.lo = 0x7f000000, msr.hi = 0x00000000
+setup_bsp_ramtop, TOP MEM2: msr.lo = 0x00000000, msr.hi = 0x00000000
+setup_uma_memory: uma size 0x20000000, memory start 0x5f000000
+CPU_CLUSTER: 0 enabled
+DOMAIN: 0000 enabled
+CPU_CLUSTER: 0 scanning...
+PCI: 00:18.5 family15h, core_max=0x10, core_nums=0xf, siblings=0x3
+lpaicid_start=0x10 node 0x0 core 0x0 apicid=0x10
+CPU: APIC: 10 enabled
+lpaicid_start=0x10 node 0x0 core 0x1 apicid=0x11
+CPU: APIC: 11 enabled
+lpaicid_start=0x10 node 0x0 core 0x2 apicid=0x12
+CPU: APIC: 12 enabled
+lpaicid_start=0x10 node 0x0 core 0x3 apicid=0x13
+CPU: APIC: 13 enabled
+DOMAIN: 0000 scanning...
+PCI: pci_scan_bus for bus 00
+PCI: 00:00.0 [1022/1410] enabled
+PCI: 00:01.0 [1002/9900] enabled
+PCI: 00:01.1 [1002/9902] enabled
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Capability: type 0x05 @ 0xa0
+Capability: type 0x0d @ 0xb0
+Capability: type 0x08 @ 0xb8
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+PCI: 00:04.0 subordinate bus PCI Express
+PCI: 00:04.0 [1022/1414] enabled
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Capability: type 0x05 @ 0xa0
+Capability: type 0x0d @ 0xb0
+Capability: type 0x08 @ 0xb8
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+PCI: 00:05.0 subordinate bus PCI Express
+PCI: 00:05.0 [1022/1415] enabled
+hudson_enable()
+PCI: 00:10.0 [1022/7812] enabled
+hudson_enable()
+PCI: 00:11.0 [1022/7801] ops
+PCI: 00:11.0 [1022/7801] enabled
+hudson_enable()
+PCI: 00:12.0 [1022/7807] ops
+PCI: 00:12.0 [1022/7807] enabled
+hudson_enable()
+PCI: 00:12.2 [1022/7808] ops
+PCI: 00:12.2 [1022/7808] enabled
+hudson_enable()
+PCI: 00:13.0 [1022/7807] ops
+PCI: 00:13.0 [1022/7807] enabled
+hudson_enable()
+PCI: 00:13.2 [1022/7808] ops
+PCI: 00:13.2 [1022/7808] enabled
+hudson_enable()
+PCI: 00:14.0 [1022/780b] bus ops
+PCI: 00:14.0 [1022/780b] enabled
+hudson_enable()
+PCI: 00:14.2 [1022/780d] ops
+PCI: 00:14.2 [1022/780d] enabled
+hudson_enable()
+PCI: 00:14.3 [1022/780e] bus ops
+PCI: 00:14.3 [1022/780e] enabled
+hudson_enable()
+PCI: 00:14.4 [1022/780f] bus ops
+PCI: 00:14.4 [1022/780f] enabled
+hudson_enable()
+PCI: 00:14.5 [1022/7809] ops
+PCI: 00:14.5 [1022/7809] enabled
+hudson_enable()
+hudson_enable()
+PCI: 00:14.7 [1022/7806] enabled
+hudson_enable()
+hudson_enable()
+hudson_enable()
+hudson_enable()
+PCI: 00:18.0 [1022/1400] ops
+PCI: 00:18.0 [1022/1400] enabled
+PCI: 00:18.1 [1022/1401] enabled
+PCI: 00:18.2 [1022/1402] enabled
+PCI: 00:18.3 [1022/1403] enabled
+PCI: 00:18.4 [1022/1404] enabled
+PCI: 00:18.5 [1022/1405] enabled
+do_pci_scan_bridge for PCI: 00:04.0
+PCI: pci_scan_bus for bus 01
+PCI: 01:00.0 [10ec/5289] enabled
+PCI: 01:00.2 [10ec/8168] enabled
+PCI: pci_scan_bus returning with max=001
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x70
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Enabling Common Clock Configuration
+ASPM: Enabled L1
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x70
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Enabling Common Clock Configuration
+ASPM: Enabled L1
+do_pci_scan_bridge returns max 1
+do_pci_scan_bridge for PCI: 00:05.0
+PCI: pci_scan_bus for bus 02
+PCI: 02:00.0 [168c/0032] enabled
+PCI: pci_scan_bus returning with max=002
+Capability: type 0x01 @ 0x40
+Capability: type 0x05 @ 0x50
+Capability: type 0x10 @ 0x70
+Capability: type 0x01 @ 0x50
+Capability: type 0x10 @ 0x58
+Enabling Common Clock Configuration
+ASPM: Enabled L0s and L1
+do_pci_scan_bridge returns max 2
+scan_static_bus for PCI: 00:14.0
+smbus: PCI: 00:14.0[0]->I2C: 01:50 enabled
+smbus: PCI: 00:14.0[0]->I2C: 01:51 enabled
+scan_static_bus for PCI: 00:14.0 done
+scan_static_bus for PCI: 00:14.3
+PNP: 00ff.1 enabled
+PNP: 00ff.0 enabled
+scan_static_bus for PCI: 00:14.3 done
+do_pci_scan_bridge for PCI: 00:14.4
+PCI: pci_scan_bus for bus 03
+PCI: pci_scan_bus returning with max=003
+do_pci_scan_bridge returns max 3
+PCI: pci_scan_bus returning with max=003
+scan_static_bus for Root Device done
+done
+BS: BS_DEV_ENUMERATE times (us): entry 0 run 3825 exit 0
+found VGA at PCI: 00:01.0
+Setting up VGA for PCI: 00:01.0
+Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
+Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
+Allocating resources...
+Reading resources...
+Root Device read_resources bus 0 link: 0
+CPU_CLUSTER: 0 read_resources bus 0 link: 0
+APIC: 10 missing read_resources
+APIC: 11 missing read_resources
+APIC: 12 missing read_resources
+APIC: 13 missing read_resources
+CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
+fx_devs=0x1
+DOMAIN: 0000 read_resources bus 0 link: 0
+PCI: 00:04.0 read_resources bus 1 link: 0
+PCI: 00:04.0 read_resources bus 1 link: 0 done
+PCI: 00:05.0 read_resources bus 2 link: 0
+PCI: 00:05.0 read_resources bus 2 link: 0 done
+PCI: 00:14.0 read_resources bus 1 link: 0
+I2C: 01:50 missing read_resources
+I2C: 01:51 missing read_resources
+PCI: 00:14.0 read_resources bus 1 link: 0 done
+PCI: 00:14.3 read_resources bus 0 link: 0
+PNP: 00ff.1 missing read_resources
+PCI: 00:14.3 read_resources bus 0 link: 0 done
+PCI: 00:14.4 read_resources bus 3 link: 0
+PCI: 00:14.4 read_resources bus 3 link: 0 done
+PCI: 00:18.0 read_resources bus 0 link: 0
+PCI: 00:18.0 read_resources bus 0 link: 0 done
+PCI: 00:18.0 read_resources bus 0 link: 1
+PCI: 00:18.0 read_resources bus 0 link: 1 done
+PCI: 00:18.0 read_resources bus 0 link: 2
+PCI: 00:18.0 read_resources bus 0 link: 2 done
+PCI: 00:18.0 read_resources bus 0 link: 3
+PCI: 00:18.0 read_resources bus 0 link: 3 done
+DOMAIN: 0000 read_resources bus 0 link: 0 done
+Root Device read_resources bus 0 link: 0 done
+Done reading resources.
+Show resources in subtree (Root Device)...After reading.
+ Root Device child on link 0 CPU_CLUSTER: 0
+ CPU_CLUSTER: 0 child on link 0 APIC: 10
+ APIC: 10
+ APIC: 11
+ APIC: 12
+ APIC: 13
+ DOMAIN: 0000 child on link 0 PCI: 00:00.0
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
+ DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
+ PCI: 00:00.0
+ PCI: 00:01.0
+ PCI: 00:01.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 10
+ PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 14
+ PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 18
+ PCI: 00:01.1
+ PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffff flags 200 index 10
+ PCI: 00:03.0
+ PCI: 00:04.0 child on link 0 PCI: 01:00.0
+ PCI: 00:04.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
+ PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:04.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 01:00.0
+ PCI: 01:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 200 index 10
+ PCI: 01:00.2
+ PCI: 01:00.2 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10
+ PCI: 01:00.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 1201 index 18
+ PCI: 01:00.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 1201 index 20
+ PCI: 00:05.0 child on link 0 PCI: 02:00.0
+ PCI: 00:05.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c
+ PCI: 00:05.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
+ PCI: 00:05.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 02:00.0
+ PCI: 02:00.0 resource base 0 size 80000 align 19 gran 19 limit ffffffffffffffff flags 201 index 10
+ PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30
+ PCI: 00:08.0
+ PCI: 00:10.0
+ PCI: 00:10.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:11.0
+ PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10
+ PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14
+ PCI: 00:11.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
+ PCI: 00:11.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
+ PCI: 00:11.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20
+ PCI: 00:11.0 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24
+ PCI: 00:12.0
+ PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:12.2
+ PCI: 00:12.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
+ PCI: 00:13.0
+ PCI: 00:13.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:13.2
+ PCI: 00:13.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10
+ PCI: 00:14.0 child on link 0 I2C: 01:50
+ I2C: 01:50
+ I2C: 01:51
+ PCI: 00:14.2
+ PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:14.3 child on link 0 PNP: 00ff.1
+ PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000
+ PCI: 00:14.3 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100
+ PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2
+ PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3
+ PNP: 00ff.1
+ PNP: 00ff.0
+ PCI: 00:14.4
+ PCI: 00:14.4 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
+ PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24
+ PCI: 00:14.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
+ PCI: 00:14.5
+ PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
+ PCI: 00:14.6
+ PCI: 00:14.7
+ PCI: 00:14.7 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10
+ PCI: 00:15.0
+ PCI: 00:15.1
+ PCI: 00:15.2
+ PCI: 00:15.3
+ PCI: 00:18.0
+ PCI: 00:18.0 resource base 0 size 0 align 0 gran 0 limit 0 flags 1 index 1080
+ PCI: 00:18.0 resource base 0 size 0 align 0 gran 0 limit 0 flags 1 index 1088
+ PCI: 00:18.0 resource base 0 size 0 align 0 gran 0 limit 0 flags 1 index 10c0
+ PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058
+ PCI: 00:18.1
+ PCI: 00:18.2
+ PCI: 00:18.3
+ PCI: 00:18.4
+ PCI: 00:18.5
+DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
+PCI: 00:04.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
+PCI: 01:00.2 10 * [0x0 - 0xff] io
+PCI: 00:04.0 compute_resources_io: base: 100 size: 1000 align: 12 gran: 12 limit: ffff done
+PCI: 00:05.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff
+PCI: 00:05.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done
+PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
+PCI: 00:14.4 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
+PCI: 00:04.0 1c * [0x0 - 0xfff] io
+PCI: 00:01.0 14 * [0x1000 - 0x10ff] io
+PCI: 00:11.0 20 * [0x1400 - 0x140f] io
+PCI: 00:11.0 10 * [0x1410 - 0x1417] io
+PCI: 00:11.0 18 * [0x1418 - 0x141f] io
+PCI: 00:11.0 14 * [0x1420 - 0x1423] io
+PCI: 00:11.0 1c * [0x1424 - 0x1427] io
+DOMAIN: 0000 compute_resources_io: base: 1428 size: 1428 align: 12 gran: 0 limit: ffff done
+DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
+PCI: 00:04.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 01:00.2 20 * [0x0 - 0x3fff] prefmem
+PCI: 01:00.2 18 * [0x4000 - 0x4fff] prefmem
+PCI: 00:04.0 compute_resources_prefmem: base: 5000 size: 100000 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:04.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 01:00.0 10 * [0x0 - 0xffff] mem
+PCI: 00:04.0 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:05.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
+PCI: 00:05.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
+PCI: 00:05.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 02:00.0 10 * [0x0 - 0x7ffff] mem
+PCI: 02:00.0 30 * [0x80000 - 0x8ffff] mem
+PCI: 00:05.0 compute_resources_mem: base: 90000 size: 100000 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:14.4 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
+PCI: 00:14.4 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done
+PCI: 00:01.0 10 * [0x0 - 0xfffffff] prefmem
+PCI: 00:04.0 24 * [0x10000000 - 0x100fffff] prefmem
+PCI: 00:04.0 20 * [0x10100000 - 0x101fffff] mem
+PCI: 00:05.0 20 * [0x10200000 - 0x102fffff] mem
+PCI: 00:01.0 18 * [0x10300000 - 0x1033ffff] mem
+PCI: 00:01.1 10 * [0x10340000 - 0x10343fff] mem
+PCI: 00:14.2 10 * [0x10344000 - 0x10347fff] mem
+PCI: 00:10.0 10 * [0x10348000 - 0x10349fff] mem
+PCI: 00:12.0 10 * [0x1034a000 - 0x1034afff] mem
+PCI: 00:13.0 10 * [0x1034b000 - 0x1034bfff] mem
+PCI: 00:14.5 10 * [0x1034c000 - 0x1034cfff] mem
+PCI: 00:11.0 24 * [0x1034d000 - 0x1034d7ff] mem
+PCI: 00:12.2 10 * [0x1034d800 - 0x1034d8ff] mem
+PCI: 00:13.2 10 * [0x1034d900 - 0x1034d9ff] mem
+PCI: 00:14.7 10 * [0x1034da00 - 0x1034daff] mem
+DOMAIN: 0000 compute_resources_mem: base: 1034db00 size: 1034db00 align: 28 gran: 0 limit: ffffffff done
+avoid_fixed_resources: DOMAIN: 0000
+avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
+avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
+constrain_resources: DOMAIN: 0000
+constrain_resources: PCI: 00:00.0
+constrain_resources: PCI: 00:01.0
+constrain_resources: PCI: 00:01.1
+constrain_resources: PCI: 00:04.0
+constrain_resources: PCI: 01:00.0
+constrain_resources: PCI: 01:00.2
+constrain_resources: PCI: 00:05.0
+constrain_resources: PCI: 02:00.0
+constrain_resources: PCI: 00:10.0
+constrain_resources: PCI: 00:11.0
+constrain_resources: PCI: 00:12.0
+constrain_resources: PCI: 00:12.2
+constrain_resources: PCI: 00:13.0
+constrain_resources: PCI: 00:13.2
+constrain_resources: PCI: 00:14.0
+constrain_resources: I2C: 01:50
+constrain_resources: I2C: 01:51
+constrain_resources: PCI: 00:14.2
+constrain_resources: PCI: 00:14.3
+constrain_resources: PNP: 00ff.1
+constrain_resources: PNP: 00ff.0
+constrain_resources: PCI: 00:14.4
+constrain_resources: PCI: 00:14.5
+constrain_resources: PCI: 00:14.7
+constrain_resources: PCI: 00:18.0
+constrain_resources: PCI: 00:18.1
+constrain_resources: PCI: 00:18.2
+constrain_resources: PCI: 00:18.3
+constrain_resources: PCI: 00:18.4
+constrain_resources: PCI: 00:18.5
+avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff
+ lim->base 00001000 lim->limit 0000ffff
+avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff
+ lim->base 00000000 lim->limit f7ffffff
+Setting resources...
+DOMAIN: 0000 allocate_resources_io: base:1000 size:1428 align:12 gran:0 limit:ffff
+Assigned: PCI: 00:04.0 1c * [0x1000 - 0x1fff] io
+Assigned: PCI: 00:01.0 14 * [0x2000 - 0x20ff] io
+Assigned: PCI: 00:11.0 20 * [0x2400 - 0x240f] io
+Assigned: PCI: 00:11.0 10 * [0x2410 - 0x2417] io
+Assigned: PCI: 00:11.0 18 * [0x2418 - 0x241f] io
+Assigned: PCI: 00:11.0 14 * [0x2420 - 0x2423] io
+Assigned: PCI: 00:11.0 1c * [0x2424 - 0x2427] io
+DOMAIN: 0000 alloc
+
+*** Log truncated, 21517 characters dropped. ***
+
+Finalize devices...
+Devices
+388 bytes lost